JP7723506B2 - 半導体装置及びこれを含むデータ格納システム - Google Patents

半導体装置及びこれを含むデータ格納システム

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Publication number
JP7723506B2
JP7723506B2 JP2021101424A JP2021101424A JP7723506B2 JP 7723506 B2 JP7723506 B2 JP 7723506B2 JP 2021101424 A JP2021101424 A JP 2021101424A JP 2021101424 A JP2021101424 A JP 2021101424A JP 7723506 B2 JP7723506 B2 JP 7723506B2
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JP
Japan
Prior art keywords
region
substrate
insulating layer
barrier structure
semiconductor device
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JP2021101424A
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English (en)
Japanese (ja)
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JP2022032028A5 (enExample
JP2022032028A (ja
Inventor
相 勳 千
智 煥 金
信 煥 姜
智 勳 韓
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of JP2022032028A5 publication Critical patent/JP2022032028A5/ja
Application granted granted Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2021101424A 2020-08-10 2021-06-18 半導体装置及びこれを含むデータ格納システム Active JP7723506B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020200100043A KR102898248B1 (ko) 2020-08-10 2020-08-10 반도체 장치 및 이를 포함하는 데이터 저장 시스템
KR10-2020-0100043 2020-08-10

Publications (3)

Publication Number Publication Date
JP2022032028A JP2022032028A (ja) 2022-02-24
JP2022032028A5 JP2022032028A5 (enExample) 2024-06-12
JP7723506B2 true JP7723506B2 (ja) 2025-08-14

Family

ID=79686168

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JP2021101424A Active JP7723506B2 (ja) 2020-08-10 2021-06-18 半導体装置及びこれを含むデータ格納システム

Country Status (5)

Country Link
US (1) US12302580B2 (enExample)
JP (1) JP7723506B2 (enExample)
KR (1) KR102898248B1 (enExample)
CN (1) CN114078878A (enExample)
DE (1) DE102021113524A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102885508B1 (ko) 2020-09-15 2025-11-13 삼성전자주식회사 반도체 장치 및 이를 포함하는 데이터 저장 시스템
KR102932178B1 (ko) * 2021-06-11 2026-03-04 삼성전자주식회사 반도체 장치 및 데이터 저장 시스템
KR20230148611A (ko) * 2022-04-18 2023-10-25 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR20250000778A (ko) * 2023-06-27 2025-01-03 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019087747A (ja) 2017-11-07 2019-06-06 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． ３次元半導体メモリ装置
JP2019220534A (ja) 2018-06-18 2019-12-26 キオクシア株式会社 半導体記憶装置およびその製造方法
JP2020047810A (ja) 2018-09-20 2020-03-26 キオクシア株式会社 半導体記憶装置及びその製造方法
JP2020515084A (ja) 2017-03-08 2020-05-21 ヤンツー・メモリー・テクノロジーズ・カンパニー・リミテッド ３次元メモリデバイスのハイブリッドボンディングコンタクト構造

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160013756A (ko) 2014-07-28 2016-02-05 에스케이하이닉스 주식회사 연결구조물, 반도체 장치 및 그 제조 방법
KR102282138B1 (ko) * 2014-12-09 2021-07-27 삼성전자주식회사 반도체 소자
US20170104000A1 (en) 2015-10-13 2017-04-13 Joo-Hee PARK Vertical memory devices
US9818759B2 (en) * 2015-12-22 2017-11-14 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device
US9985040B2 (en) 2016-01-14 2018-05-29 Micron Technology, Inc. Integrated circuitry and 3D memory
US9917093B2 (en) 2016-06-28 2018-03-13 Sandisk Technologies Llc Inter-plane offset in backside contact via structures for a three-dimensional memory device
US9905307B1 (en) * 2016-08-24 2018-02-27 Sandisk Technologies Llc Leakage current detection in 3D memory
US10685914B2 (en) 2017-08-31 2020-06-16 SK Hynix Inc. Semiconductor device and manufacturing method thereof
JP2019160922A (ja) 2018-03-09 2019-09-19 東芝メモリ株式会社 半導体装置
KR102614849B1 (ko) 2018-05-21 2023-12-18 삼성전자주식회사 지지대를 갖는 3d 반도체 소자 및 그 형성 방법
US10971432B2 (en) 2018-08-06 2021-04-06 Samsung Electronics Co., Ltd. Semiconductor device including a through wiring area
JP2020035921A (ja) 2018-08-30 2020-03-05 キオクシア株式会社 半導体記憶装置
US11282783B2 (en) * 2020-01-07 2022-03-22 Sandisk Technologies Llc Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020515084A (ja) 2017-03-08 2020-05-21 ヤンツー・メモリー・テクノロジーズ・カンパニー・リミテッド ３次元メモリデバイスのハイブリッドボンディングコンタクト構造
JP2019087747A (ja) 2017-11-07 2019-06-06 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． ３次元半導体メモリ装置
JP2019220534A (ja) 2018-06-18 2019-12-26 キオクシア株式会社 半導体記憶装置およびその製造方法
JP2020047810A (ja) 2018-09-20 2020-03-26 キオクシア株式会社 半導体記憶装置及びその製造方法

Also Published As

Publication number Publication date
KR20220019522A (ko) 2022-02-17
CN114078878A (zh) 2022-02-22
JP2022032028A (ja) 2022-02-24
KR102898248B1 (ko) 2025-12-10
US20220045084A1 (en) 2022-02-10
DE102021113524A1 (de) 2022-02-10
US12302580B2 (en) 2025-05-13

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