JP7666652B2 - 量子演算装置及び量子演算装置の製造方法 - Google Patents

量子演算装置及び量子演算装置の製造方法 Download PDF

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Publication number
JP7666652B2
JP7666652B2 JP2023572319A JP2023572319A JP7666652B2 JP 7666652 B2 JP7666652 B2 JP 7666652B2 JP 2023572319 A JP2023572319 A JP 2023572319A JP 2023572319 A JP2023572319 A JP 2023572319A JP 7666652 B2 JP7666652 B2 JP 7666652B2
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substrate
quantum
cover
bit
processing device
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JPWO2023132063A5 (https=
JPWO2023132063A1 (https=
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剛 高橋
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H10N60/815—Containers; Mountings for Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0912—Manufacture or treatment of Josephson-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0109—Bonding an individual cap on the substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0172—Seals
    • B81C2203/019—Seals characterised by the material or arrangement of seals between parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Semiconductor Memories (AREA)
JP2023572319A 2022-01-07 2022-01-07 量子演算装置及び量子演算装置の製造方法 Active JP7666652B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/000384 WO2023132063A1 (ja) 2022-01-07 2022-01-07 量子演算装置及び量子演算装置の製造方法

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JPWO2023132063A1 JPWO2023132063A1 (https=) 2023-07-13
JPWO2023132063A5 JPWO2023132063A5 (https=) 2024-07-10
JP7666652B2 true JP7666652B2 (ja) 2025-04-22

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US (1) US20260082822A1 (https=)
EP (1) EP4475176B1 (https=)
JP (1) JP7666652B2 (https=)
WO (1) WO2023132063A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025046715A1 (ja) * 2023-08-28 2025-03-06 富士通株式会社 量子ビットデバイス及び量子ビットデバイスの製造方法
JP2025112080A (ja) * 2024-01-18 2025-07-31 富士通株式会社 量子ビットデバイスの製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180013052A1 (en) 2015-07-23 2018-01-11 Massachusetts Institute Of Technology Qubit and Coupler Circuit Structures and Coupling Techniques
JP2019532505A (ja) 2016-09-13 2019-11-07 グーグル エルエルシー 積層量子デバイス内の損失の低減

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04338683A (ja) * 1991-05-16 1992-11-25 Fujitsu Ltd 超伝導集積回路素子とその実装方法
JP3118562B2 (ja) * 1997-12-08 2000-12-18 工業技術院長 超電導集積回路構造及びその製造方法
US6528875B1 (en) * 2001-04-20 2003-03-04 Amkor Technology, Inc. Vacuum sealed package for semiconductor chip
US9836699B1 (en) * 2015-04-27 2017-12-05 Rigetti & Co. Microwave integrated quantum circuits with interposer
JP6974470B2 (ja) 2016-09-14 2021-12-01 グーグル エルエルシーGoogle LLC ローカル真空キャビティーを使用して量子デバイスの中の散逸および周波数ノイズを低減させること
CN110431568B (zh) 2017-03-13 2024-03-08 谷歌有限责任公司 在堆叠的量子计算装置中的集成电路元件
JP7427914B2 (ja) * 2019-10-30 2024-02-06 日本電気株式会社 超伝導回路装置、スペーサ、及び超伝導回路装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180013052A1 (en) 2015-07-23 2018-01-11 Massachusetts Institute Of Technology Qubit and Coupler Circuit Structures and Coupling Techniques
JP2019532505A (ja) 2016-09-13 2019-11-07 グーグル エルエルシー 積層量子デバイス内の損失の低減

Also Published As

Publication number Publication date
EP4475176A1 (en) 2024-12-11
WO2023132063A1 (ja) 2023-07-13
US20260082822A1 (en) 2026-03-19
EP4475176B1 (en) 2026-04-29
EP4475176A4 (en) 2025-10-29
JPWO2023132063A1 (https=) 2023-07-13

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