JP7482571B2 - Ｉｇｂｔデバイス - Google Patents

Ｉｇｂｔデバイス Download PDF

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JP7482571B2
JP7482571B2 JP2023501642A JP2023501642A JP7482571B2 JP 7482571 B2 JP7482571 B2 JP 7482571B2 JP 2023501642 A JP2023501642 A JP 2023501642A JP 2023501642 A JP2023501642 A JP 2023501642A JP 7482571 B2 JP7482571 B2 JP 7482571B2
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林敏之
▲劉▼磊
▲劉▼▲偉▼
袁▲願▼林
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蘇州東微半導体股▲ふん▼有限公司
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Description

本願は半導体パワーデバイスの技術分野に属し、例えば、ＩＧＢＴデバイスに関する。
本願は、２０２１年１２月１５日に中国専利局に出願された出願番号が第２０２１１１５３４４５９．６号の中国専利出願の優先権を主張し、当該出願の全部内容を参照によって本願に援用される。
絶縁ゲートバイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ，ＩＧＢＴ）デバイスは、金属酸化物半導体（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ，ＭＯＳ）トランジスタとバイポーラトランジスタにより複合したデバイスであり、ＩＧＢＴデバイスの入力極はＭＯＳトランジスタであり、出力極はＰＮＰ型トランジスタであり、これら２種類のトランジスタデバイスの特徴を融合しており、ＭＯＳトランジスタの駆動電力が小さくてスイッチング速度が速い特徴を有するとともに、バイポーラトランジスタの飽和電圧降下が低くて容量が大きい特徴も有する。ＩＧＢＴデバイスは、ｐ型ボディ領域とｎ型ドリフト領域の境界における正孔注入効率が低く、キャリア濃度分布が低いため、飽和電圧降下が上昇し、オフにするときに、ｎ型ドリフト領域内に大量の少数キャリアが蓄積され、ＩＧＢＴデバイスのターンオフ時のテール電流現象が深刻になり、ターンオフ損失が大きくなる。
本願はＩＧＢＴデバイスのターンオフ損失を低減するためにＩＧＢＴデバイスを提供する。
本願はＩＧＢＴデバイスを提供し、該ＩＧＢＴデバイスは、
ｐ型コレクタ領域と、
前記ｐ型コレクタ領域の上に位置するｎ型半導体層と、
前記ｎ型半導体層内に位置するいくつかのｐ型ボディ領域であって、それぞれのｐ型ボディ領域内にｎ型エミッタ領域が設けられるいくつかのｐ型ボディ領域と、
前記ｎ型半導体層内に位置し、且つ隣接する前記ｐ型ボディ領域の間に介在するゲートトレンチと、前記ゲートトレンチの下部内に位置するシールドゲートと、前記ゲートトレンチの上部内に位置するゲートとを含み、前記ゲート、前記シールドゲート、及び前記ｎ型半導体層の間は互いに絶縁分離され、
いくつかの前記ｐ型ボディ領域のうち、少なくとも１つの前記ｐ型ボディ領域は第１のドーピング濃度を有して第１のｐ型ボディ領域として定義され、且つ少なくとも１つの前記ｐ型ボディ領域は第２のドーピング濃度を有して第２のｐ型ボディ領域として定義され、前記第１のｐ型ボディ領域の第１のドーピング濃度は前記第２のｐ型ボディ領域の第２のドーピング濃度よりも小さく、
少なくとも１つの前記第１のｐ型ボディ領域に隣接する前記ゲートトレンチ内の前記シールドゲートは、ゲート電圧に外部接続され、残りの前記ゲートトレンチ内の前記シールドゲートは、エミッタ電圧に外部接続される。
本願に係るＩＧＢＴデバイスの第１の実施例の断面構造模式図である。 本願に係るＩＧＢＴデバイスの第２の実施例の断面構造模式図である。
以下、本願の実施例における図面を参照しながら、具体的形態によって本願の技術案を完全に説明する。もちろん、説明される実施例は本願の一部の実施例であり、すべての実施例ではない。同時に、本願の具体的な実施形態を明確に説明するために、明細書の図面に挙げられる模式図は、本願に記載される層と領域の厚みを拡大し、且つ挙げられる図形のサイズは実際の寸法を表していない。
図１は本願に係るＩＧＢＴデバイスの第１の実施例の断面構造模式図であり、図１に示すように、本願のＩＧＢＴデバイスはｐ型コレクタ領域２０と、ｐ型コレクタ領域２０の上に位置するｎ型半導体層２１と、ｎ型半導体層２１内に位置するいくつかのｐ型ボディ領域２２とを含み、それぞれのｐ型ボディ領域２２内にｎ型エミッタ領域２３が設けられる。
ｎ型半導体層２１内に位置し、且つ隣接するｐ型ボディ領域２２の間に位置するゲートトレンチと、前記ゲートトレンチの上部内に位置するゲート２５と、ゲートトレンチの下部内に位置するシールドゲート２７とを含み、シールドゲート２７はゲートトレンチの下部内のみに位置してもよく、これにより、ゲート２５とシールドゲート２７は上下構造であり、好ましくは、シールドゲート２７はゲートトレンチの下部内に位置してゲートトレンチの上部内まで上方に延びていてもよく、図１はシールドゲート２７がゲートトレンチの下部内に位置してゲートトレンチの上部内まで上方に延びていることを例として示している。同時に、ゲートトレンチの上部の幅はゲートトレンチの下部の幅よりも大きくてもよく、等しくてもよく、又は小さくてもよく、図１において、ゲートトレンチの上部の幅がゲートトレンチの下部の幅よりも大きいことを示している。
ゲート２５、シールドゲート２７、ｎ型半導体層２１の間は互いに絶縁分離され、図１において、ゲート２５はゲート誘電体層２４によってｎ型半導体層２１に絶縁分離され、シールドゲート２７はフィールド酸化層２６によってゲート２５とｎ型半導体層２１に分離される。
本願のいくつかのｐ型ボディ領域２２のうち、本願の実施例に４つのｐ型ボディ領域２２を例示的に示し、そのうち、少なくとも１つのｐ型ボディ領域２２は第１のドーピング濃度を有して第１のｐ型ボディ領域２２ａとして定義され、且つ少なくとも１つのｐ型ボディ領域２２は第２のドーピング濃度を有して第２のｐ型ボディ領域２２ｂとして定義され、第１のｐ型ボディ領域２２ａの第１のドーピング濃度は第２のｐ型ボディ領域２２ｂの第２のドーピング濃度よりも小さい。図１に１つの第１のｐ型ボディ領域２２ａと３つの第２のｐ型ボディ領域２２ｂを例示的に示している。
本願のＩＧＢＴデバイスにおいて、少なくとも１つの第１のｐ型ボディ領域２２ａに隣接するゲートトレンチ内のシールドゲート２７は、ゲート電圧に外部接続され、残りのゲートトレンチ内のシールドゲート２７は、エミッタ電圧に外部接続される。図１において、例示的に、第１のｐ型ボディ領域２２ａの右側に近いゲートトレンチ内のシールドゲート２７はゲート２５とともにゲート電圧（Ｇ）に外部接続され、残りのゲートトレンチ（即ち、ゲート電圧に外部接続されたシールドゲートが所在するゲートトレンチを除くゲートトレンチ）内のシールドゲート２７はｎ型エミッタ領域２３とともにエミッタ電圧に外部接続される（図１に示さない）。
本願のＩＧＢＴデバイスにおいて、第１のドーピング濃度を有する第１のｐ型ボディ領域２２ａ内の電流チャネルの閾値電圧Ｖｔｈ１は第２のドーピング濃度を有する第２のｐ型ボディ領域２２ｂ内の電流チャネルの閾値電圧Ｖｔｈ２よりも小さい。シールドゲート２７がゲート電圧に外部接続されると、該ゲートトレンチ内のゲート２５はより大きなゲート電荷Ｑｇ１を有し、シールドゲート２７がエミッタ電圧に外部接続されると、該ゲートトレンチ内のゲート２５は小さなゲート電荷Ｑｇ２を有する。少なくとも１つの第１のｐ型ボディ領域２２ａに隣接するゲートトレンチ内のシールドゲート２７をゲート電圧に外部接続し、残りのゲートトレンチ内のシールドゲート２７をエミッタ電圧に外部接続することで、低Ｖｔｈ１と大Ｑｇ１を組み合わせ、高Ｖｔｈ２と小Ｑｇ２を組み合わせることができ、これにより、ＩＧＢＴデバイスがオンからオフにする過程に、高Ｖｔｈ２と小Ｑｇ２を組み合わせた領域内の電流チャネルは速やかにオフにし、低Ｖｔｈ１と大Ｑｇ１を組み合わせた領域内の電流チャネルは遅れてオフにし、これにより、高Ｖｔｈ２と小Ｑｇ２を組み合わせた領域内の電流チャネルがオフになる直後に、低Ｖｔｈ１と大Ｑｇ１を組み合わせた領域内の電流チャネルは依然としてオン状態であり、ゲート電圧Ｖｇのさらなる低下に伴い、低Ｖｔｈ１と大Ｑｇ１を組み合わせた領域の電流チャネルはオフになる。これにより、ＩＧＢＴデバイスは、低Ｖｔｈ１と大Ｑｇ１を組み合わせた領域のターンオフ損失として外部に表現し、高Ｖｔｈ２と小Ｑｇ２を組み合わせた領域のターンオフ損失を低減し、全体としてＩＧＢＴデバイスのターンオフ損失を低減する。
図２は本願に係るＩＧＢＴデバイスの第２の実施例の断面構造模式図であり、図２に示すように、図１に示すＩＧＢＴデバイス構造を基に、本願のＩＧＢＴデバイスはｎ型半導体層２１内に位置するｎ型電荷蓄積領域３２をさらに含み、ｎ型電荷蓄積領域３２はゲート２５の下方に位置する。本願のＩＧＢＴデバイスはｎ型コレクタ領域３０をさらに含み、ｎ型コレクタ領域３０はｎ型半導体層２１の下方に位置し、且つｐ型コレクタ領域２０と交互に間隔をおいて設けられる。好ましくは、本願のＩＧＢＴデバイスはｎ型フィールドストップ領域３１をさらに含んでもよく、ｎ型フィールドストップ領域３１はｐ型コレクタ領域２０とｎ型半導体層２１の間に介在する。ｎ型電荷蓄積領域３２、ｎ型フィールドストップ領域３１及びｎ型コレクタ領域３０はいずれも公知の技術であり、本願の実施例では詳細に説明しない。

Claims (6)

  1. ｐ型コレクタ領域と、
    前記ｐ型コレクタ領域の上に位置するｎ型半導体層と、
    前記ｎ型半導体層内に位置するいくつかのｐ型ボディ領域であって、それぞれのｐ型ボディ領域内にｎ型エミッタ領域が設けられるいくつかのｐ型ボディ領域と、
    前記ｎ型半導体層内に位置し、且つ隣接する前記ｐ型ボディ領域の間に介在するゲートトレンチと、
    前記ゲートトレンチの下部内に位置するシールドゲートと、
    前記ゲートトレンチの上部内に位置するゲートとを含み、
    前記ゲート、前記シールドゲート、及び前記ｎ型半導体層の間は互いに絶縁分離され、
    いくつかの前記ｐ型ボディ領域のうち、少なくとも１つの前記ｐ型ボディ領域は第１のドーピング濃度を有して第１のｐ型ボディ領域として定義され、且つ少なくとも１つの前記ｐ型ボディ領域は第２のドーピング濃度を有して第２のｐ型ボディ領域として定義され、前記第１のｐ型ボディ領域の第１のドーピング濃度は前記第２のｐ型ボディ領域の第２のドーピング濃度よりも小さく、
    少なくとも１つの前記第１のｐ型ボディ領域に隣接する前記ゲートトレンチ内の前記シールドゲートは、ゲート電圧に外部接続され、ゲート電圧に外部接続されたシールドゲートが所在するゲートトレンチを除く前記ゲートトレンチ内の前記シールドゲートは、エミッタ電圧に外部接続されている、ＩＧＢＴデバイス。
  2. 前記シールドゲートは前記ゲートトレンチの下部から前記ゲートトレンチの上部内まで上方に延びている、請求項１に記載のＩＧＢＴデバイス。
  3. 前記ゲートトレンチの上部の幅は前記ゲートトレンチの下部の幅よりも大きい、請求項２に記載のＩＧＢＴデバイス。
  4. 前記ｎ型半導体層内に位置するｎ型電荷蓄積領域をさらに含み、前記ｎ型電荷蓄積領域は前記ゲートの下方に位置している、請求項３に記載のＩＧＢＴデバイス。
  5. ｎ型コレクタ領域をさらに含み、前記ｎ型コレクタ領域は前記ｎ型半導体層の下方に位置し、且つ前記ｐ型コレクタ領域と交互に間隔をおいて設けらていれる、請求項１に記載のＩＧＢＴデバイス。
  6. ｎ型フィールドストップ領域をさらに含み、前記ｎ型フィールドストップ領域は前記ｐ型コレクタ領域と前記ｎ型半導体層との間に介在している、請求項１に記載のＩＧＢＴデバイス。
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