JP7448957B2 - 集積回路デバイス及びその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims description 80
- 239000004065 semiconductor Substances 0.000 claims description 73
- 230000001939 inductive effect Effects 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 17
- 230000003071 parasitic effect Effects 0.000 claims description 13
- 239000002800 charge carrier Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 10
- 239000012212 insulator Substances 0.000 description 7
- 239000000969 carrier Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
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- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
[留意事項]
Claims (10)
- 集積回路デバイス(100)であって、当該集積回路デバイス(100)は、
少なくとも100Ω・cmの抵抗率を備えバルク部分を有する半導体基板(101)と、
前記半導体基板の前記バルク部分と接触する電気絶縁層(102)であって、前記半導体基板の前記バルク部分に、前記電気絶縁層とインターフェース接続する寄生表面伝導層を誘導しやすい電気絶縁層と、
前記電気絶縁層上に配置された電気回路(103)と、
を備え、
前記集積回路デバイスは、前記半導体基板の前記バルク部分に少なくとも部分的に含まれる連続する一連の空乏誘導接合部(107)を備え、当該連続する一連の空乏誘導接合部は、前記半導体基板の前記バルク部分に、前記電気絶縁層とインターフェース接続し、前記電気絶縁層から前記半導体基板の前記バルク部分に延びる複数の空乏帯(301)を自律的に誘導するように適合され、これにより、前記空乏誘導接合部は、以下の形、アレイ状及びチェッカーボード状の1つの形に配置され、かつ、これにより、前記連続する一連の空乏誘導接合部のうち少なくともいくつかの空乏誘導接合部は、前記電気回路の2つの部分(104、105)の中間に位置する前記電気絶縁層の一部分とインターフェース接続する集積回路デバイス。 - 空乏誘導接合部(108、109)は、前記半導体基板(101)の前記バルク部分の前記電気絶縁層(102)近傍にドーピング領域(108)を備え、当該ドーピング領域は、前記半導体基板の前記バルク部分が、前記電気絶縁層とインターフェース接続する隣接領域において、自由電荷キャリアの極性と逆の極性を有する、請求項1に記載の集積回路デバイス。
- 前記空乏誘導接合部(108、109)が、別のドーピング領域(109)を、前記半導体基板(101)の前記バルク部分の前記電気絶縁層(102)近傍に備え、前記一方のドーピング領域と前記他方のドーピング領域とは、相互にインターフェース接続し、逆の極性を有する、請求項2に記載の集積回路デバイス。
- 空乏誘導接合部は、前記電気絶縁層(1202)を横断し、前記半導体基板(1201)の前記バルク部分とインターフェース接続し、それにより、ショットキー接触を形成する導電体(1204)を備える、請求項1に記載の集積回路デバイス。
- バイアス電圧を前記連続する一連の空乏誘導接合部のうち少なくともいくつかの空乏誘導接合部にかけ得る一組の電気接点(701)を備える、請求項1~4のいずれかに記載の集積回路デバイス。
- アレイ状に配置された前記連続する一連の空乏誘導接合部のうち少なくともいくつかの空乏誘導接合部が、さらに、前記電気回路の2つの部分の少なくとも1つを囲むループ状に配置される、請求項1~5のいずれかに記載の集積回路デバイス。
- 請求項1~6のいずれかに記載の集積回路デバイス(100)を製造するように適合された半導体ウェハであって、当該半導体ウェハは、
少なくとも100Ω・cmの抵抗率を備えバルク部分を有する半導体基板と、
前記半導体基板の前記バルク部分と接触する電気絶縁層であって、前記半導体基板の前記バルク部分に、前記電気絶縁層とインターフェース接続する寄生表面伝導層を誘導しやすい電気絶縁層と、
前記電気回路が形成され得る前記電気絶縁層に配置された半導体層と、
を備え、
前記半導体ウェハは、前記半導体基板の前記バルク部分に少なくとも部分的に含まれる連続する一連の空乏誘導接合部(107)を備え、当該連続する一連の空乏誘導接合部は、前記半導体基板の前記バルク部分に、前記電気絶縁層とインターフェース接続し、前記電気絶縁層から前記半導体基板の前記バルク部分に延びる複数の空乏帯(301)を、自律的に誘導するように適合され、これによって、前記空乏誘導接合部は、前記以下の形、アレイ状及びチェッカーボード状の1つの形に配置される、半導体ウェハ。 - 連続する一連の空乏誘導接合部(107)を、少なくとも100Ω・cmの抵抗率を有する半導体基板のバルク部分に、少なくとも部分的に形成するステップを含み、前記空乏誘導接合部は、前記半導体基板の前記バルク部分に、前記電気絶縁層とインターフェース接続する寄生表面伝導層を前記半導体基板の前記バルク部分に誘導しやすい電気絶縁層の一部分とインターフェース接続する複数の空乏帯(301)を、自律的に誘導するように形成され、これによって、前記空乏誘導接合部は、これらが、以下の形、アレイ状及びチェッカーボード状の1つの形に配置されるように、かつ、前記空乏誘導接合部によって誘導された前記複数の空乏帯が前記電気絶縁層から前記半導体基板の前記バルク部分に延びるように、形成される、請求項1~6のいずれかに記載の集積回路デバイス(100)を製造する方法。
- 前記空乏誘導接合部が、前記電気回路を形成するためにも用いられる処理ステップを用いて形成される、請求項8に記載の製造方法。
- 前記空乏誘導接合部は、以下の技術、注入及び拡散の少なくとも1つを用いて、少なくとも部分的に形成される、請求項8に記載の製造方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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EP18170439.6A EP3564995A1 (en) | 2018-05-02 | 2018-05-02 | Integrated circuit device and method of manufacturing thereof |
EP18170439.6 | 2018-05-02 | ||
PCT/EP2019/061318 WO2019211412A1 (en) | 2018-05-02 | 2019-05-02 | Integrated circuit device and method of manufacturing thereof |
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JP2021522692A JP2021522692A (ja) | 2021-08-30 |
JP7448957B2 true JP7448957B2 (ja) | 2024-03-13 |
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JP2020561787A Active JP7448957B2 (ja) | 2018-05-02 | 2019-05-02 | 集積回路デバイス及びその製造方法 |
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US (1) | US11222944B2 (ja) |
EP (2) | EP3564995A1 (ja) |
JP (1) | JP7448957B2 (ja) |
KR (1) | KR20210006928A (ja) |
CN (1) | CN112074953A (ja) |
IL (1) | IL278199B2 (ja) |
SG (1) | SG11202010394YA (ja) |
WO (1) | WO2019211412A1 (ja) |
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FR3136887A1 (fr) * | 2022-06-21 | 2023-12-22 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Substrat rf comprenant des régions de désertion induites par effet de champ |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090146252A1 (en) | 2007-12-07 | 2009-06-11 | Kai-Yi Huang | Integrated inductor structure |
US20150228714A1 (en) | 2014-02-13 | 2015-08-13 | Rfaxis, Inc. | Isolation methods for leakage, loss and non-linearity mitigation in radio-frequency integrated circuits on high-resistivity silicon-on-insulator substrates |
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JPS57133657A (en) * | 1981-02-12 | 1982-08-18 | Mitsubishi Electric Corp | Semiconductor device |
KR100243658B1 (ko) * | 1996-12-06 | 2000-02-01 | 정선종 | 기판 변환기술을 이용한 인덕터 소자 및 그 제조 방법 |
US5994759A (en) * | 1998-11-06 | 1999-11-30 | National Semiconductor Corporation | Semiconductor-on-insulator structure with reduced parasitic capacitance |
US6310387B1 (en) * | 1999-05-03 | 2001-10-30 | Silicon Wave, Inc. | Integrated circuit inductor with high self-resonance frequency |
GB2440365A (en) * | 2006-07-21 | 2008-01-30 | X Fab Uk Ltd | A semiconductor device |
US7598575B1 (en) * | 2007-09-12 | 2009-10-06 | National Semiconductor Corporation | Semiconductor die with reduced RF attenuation |
US10269617B2 (en) * | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
EP4287239A1 (en) * | 2022-06-02 | 2023-12-06 | Imec VZW | A low loss semiconductor substrate |
-
2018
- 2018-05-02 EP EP18170439.6A patent/EP3564995A1/en not_active Withdrawn
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2019
- 2019-05-02 WO PCT/EP2019/061318 patent/WO2019211412A1/en active Search and Examination
- 2019-05-02 CN CN201980029795.XA patent/CN112074953A/zh active Pending
- 2019-05-02 IL IL278199A patent/IL278199B2/en unknown
- 2019-05-02 KR KR1020207034564A patent/KR20210006928A/ko not_active Application Discontinuation
- 2019-05-02 US US17/051,916 patent/US11222944B2/en active Active
- 2019-05-02 EP EP19720661.8A patent/EP3788652B1/en active Active
- 2019-05-02 SG SG11202010394YA patent/SG11202010394YA/en unknown
- 2019-05-02 JP JP2020561787A patent/JP7448957B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090146252A1 (en) | 2007-12-07 | 2009-06-11 | Kai-Yi Huang | Integrated inductor structure |
US20150228714A1 (en) | 2014-02-13 | 2015-08-13 | Rfaxis, Inc. | Isolation methods for leakage, loss and non-linearity mitigation in radio-frequency integrated circuits on high-resistivity silicon-on-insulator substrates |
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Publication number | Publication date |
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WO2019211412A1 (en) | 2019-11-07 |
IL278199B1 (en) | 2023-09-01 |
KR20210006928A (ko) | 2021-01-19 |
SG11202010394YA (en) | 2020-11-27 |
EP3788652B1 (en) | 2022-03-23 |
EP3564995A1 (en) | 2019-11-06 |
US20210118977A1 (en) | 2021-04-22 |
CN112074953A (zh) | 2020-12-11 |
EP3788652A1 (en) | 2021-03-10 |
IL278199A (en) | 2020-11-30 |
IL278199B2 (en) | 2024-01-01 |
US11222944B2 (en) | 2022-01-11 |
JP2021522692A (ja) | 2021-08-30 |
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