CN220627810U - 横向双极晶体管和包括其的电子电路 - Google Patents
横向双极晶体管和包括其的电子电路 Download PDFInfo
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- CN220627810U CN220627810U CN202321340849.4U CN202321340849U CN220627810U CN 220627810 U CN220627810 U CN 220627810U CN 202321340849 U CN202321340849 U CN 202321340849U CN 220627810 U CN220627810 U CN 220627810U
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- 239000000758 substrate Substances 0.000 claims abstract description 102
- 239000012212 insulator Substances 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000009413 insulation Methods 0.000 claims description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 21
- 230000015556 catabolic process Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 11
- 230000000694 effects Effects 0.000 description 8
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/735—Lateral transistors
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- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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Abstract
本公开的各实施例涉及横向双极晶体管和包括其的电子电路。一种横向双极晶体管,包括:发射极区域,掺杂有第一导电类型,具有第一宽度和第一平均掺杂浓度;集电极区域,掺杂有该第一导电类型,具有大于该发射极区域的该第一宽度的第二宽度和低于该第一平均掺杂浓度的第二平均掺杂浓度;以及基极区域,被定位在该发射极区域与该集电极区域之间。该发射极区域、该集电极区域和该基极区域被布置在衬底上的绝缘体层上的硅层中。被去除该硅层和该绝缘体层的衬底区域被定位在该集电极区域的一侧上。偏置电路被耦合,并且被配置为向该衬底区域递送偏置电压。该偏置电压被控制以调制该集电极区域的静电掺杂。
Description
技术领域
本公开总体上涉及电子元件并且更特别地,涉及双极晶体管及其制造方法。本公开尤其涉及横向双极晶体管和包括至少一个横向双极晶体管的电子电路。
背景技术
双极晶体管是晶体管家族中基于半导体的电子元件。其操作原理基于一个正向而另一个反向的两个PN结,这两个结由位于发射极区域和集电极区域之间的基极区域形成。
横向双极晶体管是一种双极晶体管,其中发射极、基极和集电极区域在半导体衬底内彼此相邻布置,并且在某些情况下,在半导体衬底的顶部,与竖直双极晶体管相反,在竖直双极晶体管中这些区域彼此相邻布置。横向双极晶体管非常适合于在CMOS(互补金属氧化物半导体)工艺中的集成,例如由于横向双极晶体管和金属氧化物半导体场效应(MOSFET)晶体管之间的许多结构类似性。
在某些应用中,期望提高横向双极晶体管的特性,例如以提高其开关速度和/或击穿电压,为此一般要寻找目标应用的最佳折衷。
本领域需要克服已知双极晶体管,特别是已知横向双极晶体管的全部或部分缺点。
实用新型内容
根据本公开的一个或多个方面,提供了一种横向双极晶体管,包括:掺杂有第一导电类型的发射极区域,具有第一宽度和平均掺杂浓度;掺杂有第一导电类型的集电极区域,具有比发射极区域的第一宽度大的第二宽度和比发射极区域的平均掺杂浓度低的平均掺杂浓度;掺杂有第二导电类型的基极区域,横向地定位在发射极区域和集电极区域之间;发射极区域、基极区域和集电极区域布置在硅层中,该硅层被布置在绝缘体层上,绝缘体层布置在半导体衬底上;被去除硅层和绝缘体层的衬底区域,并且横向地定位在集电极区域的一侧;以及偏置电路,耦合到衬底区域并且被配置为向衬底区域递送偏置电压以便调制集电极区域的静电掺杂。
根据实施例,该晶体管还包括非本征基极区域,该非本征基极区域具有第三宽度并且被布置在具有第四宽度的该基极区域上。
根据实施例,其中该非本征基极区域的该第三宽度小于该基极区域的该第四宽度。
根据实施例,其中该非本征基极区域相对于该基极区域基本居中。
根据实施例,该晶体管还包括该发射极区域的第一部分上的第一绝缘体部分和该集电极区域的第一部分上的第二绝缘体部分,其中该基极区域被定位在该发射极区域的该第一部分和该集电极区域的该第一部分之间,并且其中该非本征基极区域被定位在该第一绝缘体部分和该第二绝缘体部分之间。
根据实施例,其中该硅层具有在5纳米到15纳米的范围内的厚度。
根据实施例,其中该绝缘体层具有在10纳米到50纳米的范围内的厚度。
根据实施例,其中该发射极区域包括具有大于或等于1×1019at/cm3的平均掺杂浓度的该第一导电类型的重掺杂区域。
根据实施例,其中该集电极区域包括该第一导电类型的轻掺杂的第一子区域和该第一导电类型的重掺杂的第二子区域。
根据实施例,其中该集电极区域的该第一子区域被定位在该基极区域和该集电极区域的该第二子区域之间。
根据实施例,其中该集电极区域的该第一子区域具有的该第一导电类型的平均掺杂浓度低于该第二导电类型的该基极区域的平均掺杂浓度。
根据实施例,其中该基极区域包括硅锗合金。
根据实施例,该晶体管还包括跨该硅层、跨该绝缘体层并且部分地跨该半导体衬底的第一绝缘沟槽,该第一绝缘沟槽被横向地定位在该集电极区域和该衬底区域之间。
根据实施例,该晶体管还包括跨该硅层、跨该绝缘体层并且部分地跨该半导体衬底的第二绝缘沟槽,该发射极区域被横向地定位在该第二绝缘沟槽和该基极区域之间。
根据实施例,其中至少位于被去除该硅层、该绝缘体层和该集电极区域的该衬底区域下方的该衬底的区掺杂有在远离该衬底的该区域的方向上径向减少的逐渐掺杂。
根据实施例,该晶体管还包括到该发射极区域、该集电极区域、该衬底区域的接触件,其中硅化物部分位于每个接触件下方。
根据本公开的一个或多个方面,提供了一种电子电路,包括一种横向双极晶体管,包括:发射极区域,掺杂有第一导电类型,具有第一宽度和第一平均掺杂浓度;集电极区域,掺杂有第一导电类型,具有大于发射极区域的第一宽度的第二宽度和低于第一平均掺杂浓度的第二平均掺杂浓度;基极区域,掺杂有第二导电类型并且横向地定位在发射极区域和集电极区域之间;其中发射极区域、基极区域和集电极区域被布置在硅层中,硅层被布置在绝缘体层上,其中绝缘体层被布置在半导体衬底上;衬底区域,被去除硅层和绝缘体层并且横向地定位在集电极区域的一侧;以及偏置电路,耦合到衬底区域并且被配置为向衬底区域递送偏置电压,偏置电压调制集电极区域的静电掺杂。
根据本公开的一个或多个方面,提供了一种电子电路,包括多个晶体管,其中每个晶体管包括一种横向双极晶体管,包括:发射极区域,掺杂有第一导电类型,具有第一宽度和第一平均掺杂浓度;集电极区域,掺杂有第一导电类型,具有大于发射极区域的第一宽度的第二宽度和低于第一平均掺杂浓度的第二平均掺杂浓度;基极区域,掺杂有第二导电类型并且横向地定位在发射极区域和集电极区域之间;其中发射极区域、基极区域和集电极区域被布置在硅层中,硅层被布置在绝缘体层上,其中绝缘体层被布置在半导体衬底上;衬底区域,被去除硅层和绝缘体层并且横向地定位在集电极区域的一侧;以及偏置电路,耦合到衬底区域并且被配置为向衬底区域递送偏置电压,偏置电压调制集电极区域的静电掺杂,并且其中该多个晶体管中的一个晶体管具有被施加到其上的第一偏置电压,并且该多个晶体管中的另一晶体管具有被施加到其上的第二偏置电压。
根据实施例,晶体管还包括具有第三宽度的非本征基极,该非本征基极布置在具有第四宽度的基极区域上。
根据特定实施例,非本征基极的第三宽度小于基极区域的第四宽度,非本征基极例如基本上相对于基极区域居中。
根据实施例,晶体管还包括发射极区域的第一部分上的第一绝缘体部分和集电极区域的第一部分上的第二绝缘体部分,基极区域在发射极区域的第一部分和集电极区域的第一部分之间,并且非本征基极在第一绝缘体部分和第二绝缘体部分之间。
根据实施例,硅层具有在从几纳米到约十五纳米的范围内(例如,从5纳米到15纳米)的厚度。
根据实施例,绝缘体层具有在从几纳米到几十纳米(例如,从10纳米到50纳米)范围内的厚度。
根据实施例,发射极区域由第一导电类型的重掺杂区域形成。
根据实施例,集电极区域包括第一导电类型的轻掺杂的第一子区域和第一导电类型的重掺杂的第二子区域。
根据特定实施例,集电极区域的第一子区域被定位在基极区域和集电极区域的第二子区域之间。
根据特定实施例,集电极区域的第一子区域具有的第一导电类型的平均掺杂浓度低于(例如,低至少十分之一)第二导电类型的基极区域的平均掺杂浓度。
根据实施例,基极区域包括硅锗合金。
根据实施例,晶体管包括跨硅层、跨绝缘体层并且部分地跨半导体衬底的第一绝缘沟槽,第一绝缘沟槽被横向地定位在集电极区域和衬底区域之间。
根据实施例,该晶体管包括跨硅层、跨绝缘体层并且部分地跨半导体衬底的第二绝缘沟槽,发射极区域被横向地定位在第二绝缘沟槽和基极区域之间。
根据实施例,半导体衬底的至少位于被去除硅层和绝缘体层的衬底区域下方,并且优选地位于集电极区域下方的区掺杂有例如从衬底区域径向减少的逐渐掺杂。
根据实施例,晶体管包括发射极区域、集电极区域、衬底区域上的接触区以及在某些情况下,在非本征基极上的接触区,偏置电路通过接触区中的一个接触区耦合到衬底区域,例如,在每个接触区下方形成硅化物部分。
实施例提供了一种包括至少一个根据实施例的晶体管的电子电路。
实施例提供了一种包括根据实施例的多个晶体管的电子电路,至少两个晶体管具有施加到衬底区域的不同偏置电压。
本实用新型有利地提高横向双极晶体管的特性,例如以提高其开关速度和/或击穿电压,并且有助于实现目标应用的最佳折衷。
附图说明
前述特征和优点以及其他特征和优点将在特定实施例的公开内容的剩余部分中详细描述,这些特定实施例是参考附图以说明而非限制的方式给出的,在附图中:
图1是示出根据实施例的横向双极晶体管的横截面视图;
图2是示出根据图1的实施例的变型的横向双极晶体管的横截面视图;
图3是示出了根据图1的实施例的另一个变型的横向双极晶体管的横截面视图;
图4A至图4F是示出根据实施例的制造横向双极晶体管的方法的步骤的横截面视图;
图5是示出对称双极晶体管的横截面视图;
图6示出了根据集电极电流(IC)给出电流增益转换频率(fT)和最大振荡频率(fmax)的曲线,并且这是对于多个衬底偏置值(VSUB)以及对于横向双极晶体管的若干示例;
图7示出了根据集电极电压提供集电极电流的I(V)曲线,该曲线用于多个衬底偏置值(VSUB),并且用于横向双极晶体管的若干示例;
图8示出了根据相对于基极/发射极结的横向距离提供电子密度和空穴密度的曲线的对于多个衬底偏置值(VSUB)以及对称横向双极晶体管和非对称横向双极晶体管;
图9示出了根据实施例的包括多个横向双极晶体管的电子电路。
具体实施方式
在不同的附图中,相同的特征由相同的附图标记表示。特别地,在各种实施例中共同的结构和/或功能特征可以具有相同的附图标记并且可以设置相同的结构、尺寸和材料特性。
为了清楚起见,仅详细图示和描述了对于理解本文所描述的实施例有用的步骤和元件。特别地,没有详细描述横向双极晶体管的元件的所有制造步骤和细节,例如在半导体区域和/或接触区上形成硅化物部分(硅化),因为它们可以用本领域技术人员已知的常规方法形成。
除非另有说明,当提到连接在一起的两个元件时,这指示除了导体之外没有任何中间元件的直接耦合,而当提到耦合在一起的两个元件时,这指示这两个元件可以耦合或它们可以经由一个或多个其他元件耦合。
在下面的描述中,当提到限定绝对位置的术语时,诸如术语“前”、“后”、“顶”、“底”、“左”、“右”等,或相对位置,诸如术语“上方”、“下方”、“上”、“下”等,或限定取向的术语,诸如术语“水平”、“竖直”等,其是指附图的取向或在正常使用位置中的横向双极晶体管。
在以下描述中,宽度或距离对应于横向双极晶体管的横向方向上的尺寸,该横向方向对应于图中所示的水平方向X,并且厚度或深度对应于图中所示的竖直方向Z上的尺寸。
除非另有说明,表述“约”、“近似”、“基本上”和“约”表示在10%以内,并且优选地在5%以内。
附图中示出,并且在以下描述中描述的实施例包括NPN型横向双极晶体管,N掺杂对应于第一导电类型,并且P掺杂对应于第二导电类型。
然而,本领域技术人员将容易理解,本公开中描述的原理可以应用于PNP型横向双极晶体管,P掺杂对应于第一导电类型,而N掺杂对应于第二导电类型。
图1是示出根据实施例的双极晶体管100的横截面视图。
晶体管100以绝缘体上半导体(例如,硅)(SOI)衬底技术制造,并且包括半导体衬底102(SUB)、通过使用例如注入氧分离(SIMOX)方法或智能切割方法在衬底102中形成的绝缘体104、以及绝缘体104上的薄单晶硅层(Si)110。例如,衬底102基于硅(Si)。绝缘体104可以是例如基于二氧化硅(SiO2)的氧化物(BOX,用于掩埋氧化物)。
优选地,晶体管处于被称为“全耗尽SOI”(FD-SOI)的技术中,也就是说,使得能够在全耗尽模式下操作,参考CMOS FD-SOI晶体管的操作。
优选地,薄硅层110具有在从几纳米到约十五纳米(例如,从5nm到15nm)的范围内的厚度e10。
优选地,绝缘体层104具有从几纳米到几十纳米(例如,从10nm到50nm)范围内的厚度e4。
晶体管100包括N掺杂的发射极区域112、N掺杂的集电极区域116和形成在发射极区域112和集电极区域116之间的P掺杂的基极区域114。
发射极区域112、基极区域114和集电极区域116在硅层110中彼此横向相邻地形成,基极区域在发射极区域和集电极区域之间。
发射极区域112是重N掺杂(N+),基极区域114是重P掺杂(P+),集电极116包括第一轻N掺杂(N-)集电极子区域116a和第二重N掺杂(N+)集电极子区域116b,第一集电极子区域116a布置在基极区域114和第二集电极子区域116b之间。发射极和集电极之间的此掺杂差异形成了晶体管的掺杂非对称性。在本文中,“重”掺杂意味着平均掺杂浓度大于或等于1×1019at/cm3,而“轻”掺杂意味着平均掺杂浓度小于1×1019at/cm3。此外,集电极区域116的宽度L16大于发射极区域112的宽度L12,形成了晶体管的几何非对称性。因此,晶体管100在几何上和掺杂上两者都被称为非对称的。
对应于基极区域114的硅层部分可以被处理以在所述基极区域中形成硅锗(SiGe)合金。基极中的锗使得能够提高晶体管的性能,于是该晶体管是异质结双极晶体管(HBT)类型。例如,由于SiGe合金相对于硅的更小的带隙,因此在基极区域中添加锗可以降低发射极区域和基极区域之间的电压。根据备选模式,基极区域由硅制成,晶体管是双极结型(BJT)晶体管。
此基极区域114对应于称为“本征”(位于发射极区域和集电极区域之间的基极的有源部分)的基极区域。
此本征基极区域的顶部具有被称为“非本征”118的基极区域,该基极区域也可以用术语“非本征基极”来表示并且是电连接部分,经由该电连接部分本征基极区域114可以在晶体管操作期间被偏置。外部基极118例如是基于多晶硅或多晶硅(Poly)。
优选地,非本征基极118的宽度L18小于基极区域114的宽度L14,并且非本征基极相对于基极区域定位,使得基极区域114的两个横向端处的第一部分114a和第二部分114b不被非本征基极118覆盖。
例如,基极区域114的宽度L14在从约10nm到100nm的范围内,并且非本征基极118的宽度L18在从约5nm到90nm的范围内,其中非本征基极可以基本上相对于基极区域居中。
此外,发射极区域112的一部分112a(第一发射极子区域)和没有被非本征基极118覆盖的基极区域114的第一部分114a被第一绝缘体部分126a(或第一间隔件)(优选地是氧化物,例如SiO2)覆盖。类似地,没有被非本征基极118覆盖的集电极区域116的一部分和基极区域114的第二部分114b被第二绝缘体部分126b(或第二间隔件)(优选地是氧化物,例如SiO2)覆盖。这些间隔件能够电绝缘中的发射极区域112和集电极区域116中的每一者的非本征基极118。基极区域114的第一部分114a和第二部分114b没有被非本征基极118覆盖,而是相应地被第一隔离层126a和第二隔离层126b覆盖,这使能提高所述非本征基极相对于发射极区域112和集电极区域116中的每一者的绝缘。
绝缘沟槽122a、122b在薄硅层110、绝缘体104和衬底102中形成(蚀刻,然后用绝缘体填充)一定深度以将晶体管100与可以在硅层110中实现的相邻电子部件分离。更准确地,绝缘沟槽122a、122b部分地跨衬底102,所跨厚度远小于所述衬底的厚度并且可以用术语“浅沟槽隔离”(STI)表示。它们可以填充有氧化物绝缘体,例如SiO2。第一绝缘沟槽122a相对于集电极区域116横向地定位,并且所示出的模式中相对于第二集电极子区域116b定位,并且第二绝缘沟槽122b相对于发射极区域112横向地定位。
例如,集电极区域116的宽度L16在从约30nm到400nm或从约30nm到300nm的范围内,第一集电极子区域116a的宽度L16在从约15nm到200nm的范围内,第二集电极子区域116b的宽度L16b在从约15nm到200nm的范围内,并且发射极区域112的宽度L12在从约15nm到200nm的范围内。
应注意的是,在所描述的实施例中,集电极区域116的宽度L16基本上对应于基极区域114和第一绝缘沟槽122a之间的距离,并且发射极区域112的宽度L12基本上对应于第二绝缘沟槽122b和基极区域114之间的距离。
在图1中示出的晶体管100中,发射极区域112和集电极区域116的深度使得它们一直延伸到绝缘体104,将基极区域114限制在其间。
在图1中示出的晶体管100中,第二间隔件126b覆盖第一集电极子区域116a并且出现在第二集电极子区域116b上。这可以使得例如在形成间隔件时考虑可能的对准误差(如下面进一步描述的),并且特别确定第二间隔件126b总是比第一集电极子区域116a稍宽,使得后者不被硅化。
此外,晶体管100包括衬底区域106,其中在衬底102上,硅层110和绝缘体104已经被移除,例如被蚀刻。此类区域被本领域技术人员称为术语“没有SOI的区域”或“NO-SO”区域。该衬底区域106相对于集电极区域116并且在示出的模式中相对于第二集电极子区域116b横向地定位在第一绝缘沟槽122a的另一侧。换句话说,第一绝缘沟槽122a位于集电极区域116和NO-SO区域106之间,使得这两个区域能够彼此横向绝缘。NO-SO区域106使得能够接触衬底以便根据称为“反向偏置”的技术对其进行偏置,如下文所解释的。
在没有被第一间隔件126a覆盖的发射极区域112的另一部分112b(第二发射极子区域)上,在没有被第二间隔件126b覆盖的集电极区域116的部分上,在非本征基极118上,以及在NO-SO区域106的至少一部分上,可以在每个硅化物部分上形成金属硅化物部分130(称为“硅化物”)和电接触区140或“接触件”(接触件在图4F中可见)。此类硅化物部分使得能够显著降低接触件的电阻值,即半导体区域和接触件之间的电阻。
优选地,如图1中所示,没有被第二间隔件126b覆盖的集电极区域116的部分是第二集电极子区域116b的一部分,使得硅化物部分130形成在集电极区域116的最重掺杂的子区域上,并且这降低了通向集电极的电阻。
优选地覆盖有硅化物130的NO-SO区域106上的接触件40(见图4F)使得能够向集电极区域116施加偏置电压以通过集电极的最轻掺杂子区域(即第一集电极子区域116a)中的静电效应来调制负载,如下文所解释的。此类偏置可以借助于偏置电路150(例如包括一个方面耦合到电压发生器152并且另一个方面经由其接触件140耦合到NO-SO衬底区域的偏置线151)执行(图4F中示出的电路)。
图2是示出了根据图1的实施例的变型的横向双极晶体管200的横截面视图,其不同之处在于,至少位于NO-SO区域106下方,并且优选地位于集电极区域116下方的衬底区208是N掺杂的,掺杂可以是渐变的(即,呈现掺杂剂梯度),例如根据高斯分布在远离NO-SO区域的方向上径向减小。
图3是示出了根据图1的实施例的另一变型的横向双极晶体管300的横截面视图,其不同之处在于,至少位于NO-SO区域106下方,并且优选地位于集电极区域116下方的衬底区308是P掺杂的,掺杂可以是渐变的(即,呈现掺杂剂梯度),例如根据高斯分布在远离NO-SO区域的方向上径向减小。
因此,根据实施例的横向双极晶体管被非对称地配置并且包括横向靠近集电极区域定位的NO-SO区域,所述区域被绝缘沟槽横向分隔。通过经由NO-SO区域上的接触件40向衬底施加偏置,可以控制所述晶体管的某些特性。特别地,衬底的偏置使得能够通过“反向偏置”技术(即穿过衬底),通过集电极的轻掺杂子区域的静电效应(与晶体管区域的静电耦合)来调制电荷,或甚至在较小程度上调制基极区域的电荷,如图1中虚线箭头中所示。
施加到衬底的偏置电压可以是例如正或负几伏特,例如在约0.5和2伏特之间,并且这取决于绝缘体104的厚度。
用“全耗尽SOI”(FD-SOI)技术中的横向双极晶体管,并且例如在上面提供的SOI的Si层和绝缘层的厚度范围内,施加到衬底的偏置电压可以降低,即使当基极区域也期望由衬底的偏置调制时。因此,将FD-SOI技术与衬底偏置相结合是有利的。
此外,集电极相对于发射极区域的非对称特征,即掺杂非对称(集电极区域“平均”比发射极区域掺杂得轻)和几何非对称(集电极区域比发射极区域宽)两者,一个方面使得集电极区域能够具有足够轻的掺杂。实际上,发明人已经确定,如果所述集电极的初始掺杂比对称双极晶体管中的轻,或甚至轻得多,则集电极的静电掺杂更高效。典型地,对于根据实施例的横向双极晶体管,与对称双极晶体管的约从1×1019到1×1021at/cm3的值相比,集电极掺杂处于从1×1016到1×1018at/cm3的范围内。
衬底与晶体管区域的静电耦合的影响与每个区域中存在的电荷水平直接相关并且因此与每个区域的掺杂直接相关。因此,对应于第二发射极子区域112b和第二集电极子区域116b的晶体管的接入或非本征(重掺杂)区域以及对应于第一发射极子区域112a的重掺杂本征区域,仅非常轻微地受到衬底的静电耦合的影响。仅基极区域114(本征)和对应于第一集电极区域116a(轻掺杂)的本征集电极区域会受到衬底的静电耦合的影响。此外,如果本征集电极116a的掺杂比本征基极区域114的掺杂轻得多,则静电耦合将主要作用在本征集电极区域116a上。
此外,发明人已经确定,如果反向偏置主要、并且均匀地沿着本征集电极116a中的竖直方向Z产生影响,则反向偏置的影响也可以到达基极区域114与绝缘体104的接口。
与衬底102和绝缘体104的组件相关联的非常轻掺杂的本征集电极116a允许通过在衬底102的NO-SO区域106上施加电压,由静电效应调制所述本征集电极中的有效掺杂或电荷。此后将会看到,这例如使能将晶体管从非常快速的操作模式切换到高压操作模式。
另一方面,发明人已经确定,如果集电极区域的宽度更大,则集电极的静电掺杂更高效以比基极区域更有利于集电极静电掺杂的调制。其原理实际上是有效地调节集电极区域的静电掺杂并且在较小程度上调节基极区域的静电掺杂。
应注意的是,静电掺杂的效率也可能取决于衬底的掺杂,如下文所解释的。
从图6至图8的描述中可以看出,根据实施例的横向双极晶体管能够获得同一晶体管的开关速度(频率)和击穿(雪崩)电压之间的不同折衷,或甚至提高同一晶体管的速度和击穿电压之间的折衷。
根据示例,对应于具有小宽度的基极区域和/或具有重掺杂的集电极区域的配置,可以施加衬底的正偏置以增加晶体管的快速性,入将在图6和图8的描述中看到的。
根据另一示例,对应于具有更宽的基极区域和/或轻掺杂的集电极区域的配置,可以施加衬底的负偏置以增加击穿电压,减小集电极中的电场,从而将击穿向更高的电压推回,如将在图7的描述中看到的那样。
根据可以应用于晶体管100、200、300的实施例的示例,考虑以下尺寸,给出在10%以内,优选地在5%以内:发射极区域的总宽度(L12):60nm;硅化发射极区域的总宽度(L12’):30nm;集电极区域的总宽度(L16):60nm;第一集电极子区域的宽度(L16a):30nm;第二集电极子区域的宽度(L16b):30nm;硅化集电极区域的宽度(L16’):30nm;基极区域的宽度(L14):28nm;非本征基极的宽度(L18):20nm;绝缘沟槽(L22)的宽度:30nm;硅层的厚度(e10):7nm;绝缘体层的厚度(e4):25nm;非本征基极的厚度(e18):20nm;以及绝缘沟槽的深度(e22):32nm。
图4A至图4F是参考图1的晶体管100进行描述的示出制造横向双极晶体管的方法的示例步骤的横截面视图。
它始于SOI衬底(优选地FD-SOI),包括:由半导体材料制成的衬底102(SUB)、通过使用例如SIMOX方法或智能切割方法在衬底102中形成的绝缘体104、以及绝缘体104上的薄单晶硅层110(Si)。例如,衬底102基于硅。绝缘体104可以是被称为掩埋氧化物(BOX)的氧化物,例如基于二氧化硅(SiO2)。
优选地,薄硅层110具有在从几纳米到约十五纳米(例如从5nm到15nm)的范围内的厚度。
优选地,绝缘体层104具有从几纳米到几十纳米(例如从10nm到50nm)范围内的厚度。
图4A示出了在衬底层102中从薄硅层110向下到一定深度(例如约30nm和300nm之间)形成绝缘沟槽(STI)122a、122b的步骤结束时获得的结构。
可以通过蚀刻然后用电绝缘材料填充蚀刻部分来形成此类绝缘沟槽。绝缘材料例如是氧化物,诸如氧化硅。
然后,该方法包括形成没有SOI的衬底区域106或NO-SO的区域的步骤,其中硅层110和绝缘体层104已经根据本领域技术人员已知的技术被蚀刻以触及衬底层102。该NO-SO区域相对于集电极区域116横向形成在第一绝缘沟槽122a的另一侧。
根据实施例,可以在蚀刻之后执行选择性外延的步骤以在NO-SO区域上保持平坦的表面。
此外,该方法可以包括在薄硅层110中形成SiGe基极区域114的步骤。
存在本领域技术人员已知的在Si层中形成SiGe区域的多种技术。例如,可以提到一种冷凝技术,该技术包括在用于形成基极区域的薄Si层的一部分上沉积SiGe层。该SiGe层可以通过选择性外延沉积,借助于在沉积SiGe之前在薄Si层上形成的由介电材料例如SiO2制成的硬掩模。该硬掩模在薄Si层的用于形成基极区域的部分的水平面上包括孔。然后,在约700℃到900℃的温度下进行氧化步骤。在该步骤中,SiGe层的锗扩散到薄Si层中。然后,例如通过适当的化学处理移除硬掩模。
图4B示出了在形成NO-SO区域106和形成基于SiGe的区域114的这些步骤结束时获得的结构。
图4C示出了在薄层110中光刻和离子注入(例如用磷或砷)步骤结束时获得的结构以在基极区域114的任一侧形成:第一重N掺杂发射极子区域112a(N+/Si);以及第一轻N掺杂集电极子区域116a(N-/Si)。
然后,在薄硅层110(部分掺杂)和绝缘沟槽122a、122b上形成由电介质材料制成的硬掩模126,例如基于四乙氧基硅烷(TEOS)以形成SiO2。该硬掩模126包括与基极区域114竖直对齐的孔126c,所述孔的宽度基本上对应于要在此基极区域上形成的非本征基极118的期望宽度并且基本上小于基极区域的宽度。例如,通过沉积介电材料形成硬掩模126,之后通过光刻形成孔126c,随后进行蚀刻。
在孔126c中进行硼掺杂多晶硅(P+/Poly)的选择性外延步骤以形成非本征基极118。多晶硅的硼扩散到基极区域114的SiGe中以对所述基极区域进行重P型掺杂(P+/SiGe)。
图4D示出了在这些外延和掺杂步骤结束时获得的结构。
然后,部分移除硬掩模126,仅留下在非本征基极118两侧的第一绝缘体部分126a(第一间隔件)和第二绝缘体部分126b(第二间隔件),相应地与第一发射极子区域112a和第一集电极子区域116a竖直延伸,也就是说,基本上停止在薄硅层110尚未掺杂的部分的边缘。
图4E示出了在移除硬掩模的步骤和例如用磷或砷进行离子注入的步骤结束时获得的形成在薄硅层110的尚未掺杂的部分中以形成以下的结构:第二重N掺杂发射极子区域112b(N+/Si);以及第二重N掺杂集电极子区域116b(N+/Si)。
图4F示出了在第二发射极子区域112b、第二发射极子区域116b、非本征基极118和至少一部分NO-SO区域106上形成硅化物部分130的步骤以及在这些硅化物部分上形成电接触区140的步骤结束时获得的结构。在NO-SO区域106的硅化部分下方,可以有利地提供重N+或P+掺杂的区108。在本领域技术人员的能力范围内的所有这些步骤将不在本文详述。
为了形成根据图2或图3的实施例的横向双极晶体管,可以应用上述方法,然后掺杂至少在NO-SO区域下方的衬底区。对于根据图2的变型的横向双极晶体管200,区108可以是N+掺杂的。对于根据图3的变型的横向双极晶体管300,区108可以是P+掺杂的。
从此方法的示例可以看出,实施例的非对称横向双极晶体管可以容易地由标准CMOS方法制造,而不增加另外的方法复杂性。这特别使能形成低成本的双极晶体管,同时相对于其他已知的双极晶体管提高了性能。
图5是示出对称双极晶体管500的示例的横截面视图。发射极区域512和集电极区域516具有基本相同的宽度L12、L16和基本相同的掺杂。换句话说,集电极516和基极514之间的距离基本上等于发射极512和基极514之间的距离。
图6示出了根据集电极电流(IC)给出电流增益转换频率(FT)(曲线300、302、304、306)和最大振荡频率(fmax)(曲线301、303、305、307)的曲线,并且这对于多个衬底偏置值(VSUB)和横向双极晶体管的若干示例来说是此:曲线300和301对应于对称晶体管500,曲线302和303对应于非对称晶体管100,曲线304和305对应于具有N掺杂的非对称晶体管200,并且曲线306和307对应于具有P掺杂的非对称晶体管300;曲线300a、301a、302a、303a、304a、305a、306a、307a对应于2v偏置值(VSUB);曲线300b、301b、302b、303b、304b、305b、306b、307b对应于1v偏置值(VSUB);曲线300c、301c、302c、303c、304c、305c、306c、307c对应于0v偏置值(VSUB)(无偏置);并且曲线300d、301d、302d、303d、304d、305d、306d、307d对应于-1-V偏置值(VSUB)。
图7示出了根据集电极电压(V)提供集电极电流(I)的I(V)曲线,对于多个衬底偏置值(VSUB),与此对于横向双极晶体管的若干示例:曲线401对应于对称晶体管500,曲线403对应于非对称晶体管100,曲线405对应于具有N掺杂的非对称晶体管200,并且曲线407对应于具有P掺杂的非对称晶体管300;曲线401a、403a、405a、407a对应于2v偏置值(VSUB);曲线401b、403b、405b、407b对应于0v偏置值(VSUB)(无偏置);并且曲线401c、403c、405c、407c对应于-2v偏置值(VSUB)。
图8示出了根据相对于基极/发射极结(点0)的横向距离(单位为m)提供电子密度(/cm3)和空穴密度(/cm3)的曲线,与此对于多个衬底偏置值(VSUB)和横向双极晶体管的多个示例,曲线501对应于对称晶体管500,并且曲线503对应于非对称晶体管100;曲线501a、503a对应于2v偏置值(VSUB);曲线501b、503b对应于0v偏置值(VSUB)(无偏置);曲线501c、503c对应于-2v偏置值(VSUB)。
如上面指出的,图6和图7的曲线是通过比较非对称横向晶体管100、200、300和对称横向晶体管500绘制的,并且图8的曲线是通过比较非对称横向晶体管100和对称横向晶体管500绘制的。对于这些晶体管,基极区域的SiGe合金中的锗浓度约为20%并且对于晶体管100、200、300、500中的每个晶体管,不同区域的掺杂在下面的表1中示出。
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此外,用于绘制图6和图7的曲线的晶体管100、200、300的尺寸在上述实施例的示例中给出,晶体管500的厚度和深度与晶体管100、200、300的厚度和深度相同,并且晶体管500的宽度如下:发射极区域的总宽度(L12):60nm;硅化发射极区域的宽度(L12’):30nm;集电极区域的总宽度(L16):60nm;硅化集电极区域的宽度(L16’):30nm;基极区域的宽度(L14):28nm;以及非本征基极的宽度(L18):20nm。
从对图6的曲线的分析中可以看出:衬底的偏置使得能够调制(增加)非对称晶体管的电流增益晶体管频率(FT)和最大振荡频率(fmax)的特性,而对于对称晶体管,这是不允许的,或是非常轻微的;频率随着所施加的偏置电压而增加:特别地,必须施加正偏置电压来增加晶体管频率,从而增加晶体管的快速性和功率增益;集电极区域和NO-SO区域(晶体管200)下方的衬底的N型掺杂增加了频率,因此对衬底在频率上的偏置效率具有积极影响;并且集电极区域和NO-SO区域(晶体管300)下方的衬底的P型掺杂对衬底偏置的效率具有相当负面的影响。
因此,可以施加衬底的正偏置来增加晶体管的快速性。如图8所示,这对应于集电极中电子积累和基极中空穴减少的配置。正偏置(曲线503a)导致基极-集电极空间电荷区向基极移位,意味着更小的中性基极宽度和更重的静电掺杂集电极区域,从而将强注入效应推向更高的电流密度。此外,基极-发射极结容量由于基极中空穴的减少而降低。在图8中,通过比较曲线503和曲线501,还可以看出,偏置对非对称晶体管有非常明显的影响(曲线503),而对对称晶体管几乎没有影响(曲线501)。
从对图7的曲线的分析中可以看出:衬底的偏置使得能够调节(增加)非对称晶体管的击穿电压特性,而对于对称晶体管来说,它允许的击穿电压特性要小得多:例如,对于对称晶体管来说,它保持在2.5V以下,而对于对称晶体管来说,它可以超过3V;击穿电压随着所施加的偏置电压而增加:特别地,必须施加负偏置电压来增加晶体管击穿电压,从而减少雪崩现象;集电极区域和NO-SO区域(晶体管200)下方的衬底的N型掺杂对衬底在击穿电压上的偏置效率没有影响;集电极区域和NO-SO区域(晶体管300)下方的衬底的P型掺杂可以对衬底偏置的效率和击穿电压产生积极的影响。
因此,从图6至图8中可以看出,向衬底施加偏置电压结合晶体管的非对称特性能够控制所述晶体管的特性,特别是调节快速性和击穿电压之间的折衷。
如图9中图示的,根据实施例的一个晶体管或多个晶体管可以被集成在电子电路900中,图9示出了根据实施例的两个非对称横向双极晶体管100,每个晶体管在同一衬底SUB上具有NO-SO区域上(非常示意性地示出了晶体管)。它可以是多个基本上类似的晶体管,但是具有施加到其上的不同偏置电压。它也可以是具有相同的偏置电压或不同的偏置电压的多个不同的晶体管。电子电路可以包括其他电子元件。
尽管不是限制性的,但是根据实施例的晶体管的优选应用是在需要密集数字功能和RF(射频)功能两者的系统中,例如5G和6G基础设施或雷达,特别是远程机动车辆雷达以及更一般的通信系统,通过光纤或无线,包括便携式系统以及毫米范围成像系统。
根据实施例的晶体管的特别有利的应用涉及Bi-CMOS(双极互补金属氧化物半导体)设备,其在同一集成电路芯片上组合了双极晶体管和CMOS晶体管,从而受益于双极技术的高速特性和CMOS技术的低消耗特性。
已经描述了各种实施例和变型。本领域技术人员应理解这些不同实施例和变型的某些特征可以组合,并且本领域技术人员将想到其他变型。特别地,晶体管可以是另一横向异质结双极晶体管(HBT),或横向双极结晶体管(BJT)。
最后,基于以上给出的功能指示,所描述的实施例和变型的实际实现方式在本领域技术人员的能力内。
Claims (18)
1.一种横向双极晶体管,其特征在于,包括:
发射极区域,掺杂有第一导电类型,具有第一宽度和第一平均掺杂浓度;
集电极区域,掺杂有所述第一导电类型,具有大于所述发射极区域的所述第一宽度的第二宽度和低于所述第一平均掺杂浓度的第二平均掺杂浓度;
基极区域,掺杂有第二导电类型并且横向地定位在所述发射极区域和所述集电极区域之间;
其中所述发射极区域、所述基极区域和所述集电极区域被布置在硅层中,所述硅层被布置在绝缘体层上,其中所述绝缘体层被布置在半导体衬底上;
衬底区域,被去除所述硅层和所述绝缘体层并且横向地定位在所述集电极区域的一侧;以及
偏置电路,耦合到所述衬底区域并且被配置为向所述衬底区域递送偏置电压,所述偏置电压调制所述集电极区域的静电掺杂。
2.根据权利要求1所述的晶体管,其特征在于,还包括非本征基极区域,所述非本征基极区域具有第三宽度并且被布置在具有第四宽度的所述基极区域上。
3.根据权利要求2所述的晶体管,其特征在于,其中所述非本征基极区域的所述第三宽度小于所述基极区域的所述第四宽度。
4.根据权利要求3所述的晶体管,其特征在于,其中所述非本征基极区域相对于所述基极区域基本居中。
5.根据权利要求2所述的晶体管,其特征在于,还包括所述发射极区域的第一部分上的第一绝缘体部分和所述集电极区域的第一部分上的第二绝缘体部分,其中所述基极区域被定位在所述发射极区域的所述第一部分和所述集电极区域的所述第一部分之间,并且其中所述非本征基极区域被定位在所述第一绝缘体部分和所述第二绝缘体部分之间。
6.根据权利要求1所述的晶体管,其特征在于,其中所述硅层具有在5纳米到15纳米的范围内的厚度。
7.根据权利要求1所述的晶体管,其特征在于,其中所述绝缘体层具有在10纳米到50纳米的范围内的厚度。
8.根据权利要求1所述的晶体管,其特征在于,其中所述发射极区域包括具有大于或等于1×1019at/cm3的平均掺杂浓度的所述第一导电类型的重掺杂区域。
9.根据权利要求1所述的晶体管,其特征在于,其中所述集电极区域包括所述第一导电类型的轻掺杂的第一子区域和所述第一导电类型的重掺杂的第二子区域。
10.根据权利要求9所述的晶体管,其特征在于,其中所述集电极区域的所述第一子区域被定位在所述基极区域和所述集电极区域的所述第二子区域之间。
11.根据权利要求9所述的晶体管,其特征在于,其中所述集电极区域的所述第一子区域具有的所述第一导电类型的平均掺杂浓度低于所述第二导电类型的所述基极区域的平均掺杂浓度。
12.根据权利要求1所述的晶体管,其特征在于,其中所述基极区域包括硅锗合金。
13.根据权利要求1所述的晶体管,其特征在于,还包括跨所述硅层、跨所述绝缘体层并且部分地跨所述半导体衬底的第一绝缘沟槽,所述第一绝缘沟槽被横向地定位在所述集电极区域和所述衬底区域之间。
14.根据权利要求13所述的晶体管,其特征在于,还包括跨所述硅层、跨所述绝缘体层并且部分地跨所述半导体衬底的第二绝缘沟槽,所述发射极区域被横向地定位在所述第二绝缘沟槽和所述基极区域之间。
15.根据权利要求1所述的晶体管,其特征在于,其中至少位于被去除所述硅层、所述绝缘体层和所述集电极区域的所述衬底区域下方的所述衬底的区掺杂有在远离所述衬底的所述区域的方向上径向减少的逐渐掺杂。
16.根据权利要求1所述的晶体管,其特征在于,还包括到所述发射极区域、所述集电极区域、所述衬底区域的接触件,其中硅化物部分位于每个接触件下方。
17.一种电子电路,其特征在于,包括根据权利要求1所述的晶体管。
18.一种电子电路,其特征在于,包括多个晶体管,其中每个晶体管包括根据权利要求1所述的晶体管,并且其中所述多个晶体管中的一个晶体管具有被施加到其上的第一偏置电压,并且所述多个晶体管中的另一晶体管具有被施加到其上的第二偏置电压。
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