JP7398339B2 - 半導体装置 - Google Patents
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- JP7398339B2 JP7398339B2 JP2020094212A JP2020094212A JP7398339B2 JP 7398339 B2 JP7398339 B2 JP 7398339B2 JP 2020094212 A JP2020094212 A JP 2020094212A JP 2020094212 A JP2020094212 A JP 2020094212A JP 7398339 B2 JP7398339 B2 JP 7398339B2
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- 239000004065 semiconductor Substances 0.000 title claims description 217
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 93
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 93
- 239000000758 substrate Substances 0.000 claims description 56
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 52
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 52
- 239000012535 impurity Substances 0.000 claims description 26
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
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- 230000014759 maintenance of location Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
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- 150000002500 ions Chemical class 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
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- 238000009825 accumulation Methods 0.000 description 1
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Description
<半導体装置の構造について>
本発明の一実施の形態の半導体装置を図面を参照して説明する。図1は、本実施の形態の半導体装置の要部断面図であり、ゲート長方向に略平行な断面が示されている。
次に、本実施の形態の半導体装置の製造工程を図面を参照して説明する。図2~図16は、本実施の形態の半導体装置の製造工程中の要部断面図であり、上記図1に対応する断面が示されている。なお、ここでは、本実施の形態の半導体装置の製造工程の好適な一例について説明するが、これに限定されず、種々変更可能である。
図17は、本実施の形態の半導体装置の要部断面図であり、上記図1の一部を拡大して示してある。ゲート電極GEに閾値電圧以上の電圧(電位)が印加されると、ゲート電極GEの下に位置する部分のp型半導体領域PWの上部(上層部)にチャネル(n型反転層)CHが形成されるが、このチャネルCHを、図17ではドットのハッチングを付して示してある。チャネルCHが形成されると、n型ソース領域SRとn型ドレイン領域DRとが、チャネルCHおよびn型半導体領域NWを通じて導通する。
図18は、本実施の形態2の半導体装置の要部断面図であり、上記図1に対応するものである。
図19は、本実施の形態3の半導体装置の要部断面図であり、上記図1および図18に対応するものである。
CH チャネル
CP 接続部
CR キャリア
CT1,CT2 コンタクトホール
DR n型ドレイン領域
EP エピタキシャル層
GE ゲート電極
GF 絶縁膜
IL 絶縁膜
M1 配線
M1D ドレイン配線
M1S ソース配線
NT 窒化シリコン膜
NW n型半導体領域
OP 開口部
OX1,OX2 酸化シリコン膜
PG,PG1,PG2,PGB,PGD,PGS プラグ
PW p型半導体領域
SB 基板本体
SC 絶縁膜
SR n型ソース領域
SUB 半導体基板
SW,SW1,SW2 サイドウォールスペーサ
SZ 絶縁膜
TZ 絶縁膜
Claims (16)
- 半導体基板と、
前記半導体基板中に互いに離間して形成された、MISFET用の第1導電型のソース領域および前記第1導電型のドレイン領域と、
前記半導体基板中に、前記ソース領域を囲むように形成された、前記第1導電型とは反対の第2導電型の第1半導体領域と、
前記ソース領域と前記ドレイン領域との間の前記半導体基板上にゲート絶縁膜を介して形成された、前記MISFET用のゲート電極と、
を有し、
前記ゲート絶縁膜は、平面視において互いに隣り合う第1ゲート絶縁膜および第2ゲート絶縁膜を有し、
前記ゲート電極のゲート長方向において、前記第1ゲート絶縁膜は前記ソース領域側に位置し、かつ、前記第2ゲート絶縁膜は前記ドレイン領域側に位置し、
前記第1ゲート絶縁膜は、前記第2ゲート絶縁膜よりも薄く、
前記第2ゲート絶縁膜は、前記半導体基板上の第1絶縁膜と、前記第1絶縁膜上の第2絶縁膜と、前記第2絶縁膜上の第3絶縁膜と、を有する積層膜からなり、
前記第1絶縁膜および前記第3絶縁膜のそれぞれのバンドギャップは、前記第2絶縁膜のバンドギャップよりも大きく、
前記第2ゲート絶縁膜と接続する第1コンタクトプラグを更に有し、
前記第3絶縁膜は、前記第2絶縁膜の一部を露出するように形成された第1開口部を有し、
前記第1コンタクトプラグは、前記第1開口部を介して前記第2絶縁膜と接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート絶縁膜は、単層の絶縁膜からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記MISFETは、LDMOSFETである、半導体装置。 - 請求項1記載の半導体装置において、
前記MISFETのチャネル形成領域と前記ゲート電極との間には、前記第1ゲート絶縁膜が介在している、半導体装置。 - 請求項4記載の半導体装置において、
前記チャネル形成領域と前記ゲート電極との間には、前記第2ゲート絶縁膜は配置されていない、半導体装置。 - 請求項5記載の半導体装置において、
前記ソース領域と前記ドレイン領域との間の前記第1半導体領域の上部が、前記チャネル形成領域である、半導体装置。 - 請求項4記載の半導体装置において、
前記ゲート電極のゲート長方向において、前記第1ゲート絶縁膜と前記第2ゲート絶縁膜との接続部は、前記チャネル形成領域よりも前記ドレイン領域側に位置している、半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート電極のゲート長方向において、前記第1半導体領域と前記ドレイン領域との間に介在する前記第1導電型の第2半導体領域を更に有し、
前記第2半導体領域の不純物濃度は、前記ドレイン領域の不純物濃度よりも低い、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜および前記第3絶縁膜は、それぞれ酸化シリコン膜からなり、
前記第2絶縁膜は、窒化シリコン膜からなる、半導体装置。 - 請求項9記載の半導体装置において、
前記第1絶縁膜の厚さは、5nm以上かつ15nm以下であり、
前記第2絶縁膜の厚さは、5nm以上かつ15nm以下であり、
前記第3絶縁膜の厚さは、5nm以上かつ15nm以下である、半導体装置。 - 請求項9記載の半導体装置において、
前記第1ゲート絶縁膜は、酸化シリコン膜からなる、半導体装置。 - 請求項11記載の半導体装置において、
前記第1ゲート絶縁膜の厚さは、4nm以上かつ20nm以下である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート絶縁膜と前記第2ゲート絶縁膜との接続部は、段差を有する、半導体装置。 - 請求項13記載の半導体装置において、
前記段差は、前記ゲート電極で覆われている、半導体装置。 - 請求項1記載の半導体装置において、
前記ゲート電極の側面に形成されたサイドウォールスペーサを更に有し、
前記サイドウォールスペーサのうち、前記ソース領域側に形成された第1サイドウォールスペーサは、前記半導体基板上に位置し、前記ドレイン領域側に形成された第2サイドウォールスペーサは前記第2ゲート絶縁膜上に位置している、半導体装置。 - 半導体基板と、
前記半導体基板中に互いに離間して形成された、MISFET用の第1導電型のソース領域および前記第1導電型のドレイン領域と、
前記半導体基板中に、前記ソース領域を囲むように形成された、前記第1導電型とは反対の第2導電型の第1半導体領域と、
前記ソース領域と前記ドレイン領域との間の前記半導体基板上にゲート絶縁膜を介して形成された、前記MISFET用のゲート電極と、
を有し、
前記ゲート絶縁膜は、平面視において互いに隣り合う第1ゲート絶縁膜および第2ゲート絶縁膜を有し、
前記ゲート電極のゲート長方向において、前記第1ゲート絶縁膜は前記ソース領域側に位置し、かつ、前記第2ゲート絶縁膜は前記ドレイン領域側に位置し、
前記第1ゲート絶縁膜は、前記第2ゲート絶縁膜よりも薄く、
前記第2ゲート絶縁膜は、前記半導体基板上の第1絶縁膜と、前記第1絶縁膜上の第2絶縁膜と、前記第2絶縁膜上の第3絶縁膜と、を有する積層膜からなり、
前記第1絶縁膜および前記第3絶縁膜のそれぞれのバンドギャップは、前記第2絶縁膜のバンドギャップよりも大きく、
前記第2ゲート絶縁膜と接続する第2コンタクトプラグと、
前記ゲート電極から露出している前記第2ゲート絶縁膜を部分的に覆うように形成された第4絶縁膜と、
を更に有し、
前記第2コンタクトプラグの底部の一部は、前記第3絶縁膜と接続され、前記第2コンタクトプラグの底部の他の一部は、前記第4絶縁膜と接続されている、半導体装置。
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