JP7383554B2 - 基板処理方法及び基板処理装置 - Google Patents
基板処理方法及び基板処理装置 Download PDFInfo
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- 238000000034 method Methods 0.000 claims description 80
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- 238000012805 post-processing Methods 0.000 claims description 39
- 230000008859 change Effects 0.000 claims description 9
- 239000010408 film Substances 0.000 description 68
- 238000007781 pre-processing Methods 0.000 description 42
- 238000005530 etching Methods 0.000 description 37
- 238000012546 transfer Methods 0.000 description 14
- 238000012937 correction Methods 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000032258 transport Effects 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
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- 239000004065 semiconductor Substances 0.000 description 1
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- H01L21/67017—Apparatus for fluid treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
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Description
本実施形態に係る基板処理装置Sについて、図1を用いて説明する。図1は、本実施形態に係る基板処理装置Sの構成図の一例である。基板処理装置Sは、半導体ウェハ等の基板Wに前工程の処理及び後工程の処理を施す装置である。
次に、基板処理装置Sの動作の一例について、図2および図3を用いて説明する。図2は、本実施形態に係る基板処理装置Sの動作の一例を示すフローチャートである。図3は、第1例における基板Wの断面模式図の一例である。基板W(図3(a)参照)は、基体200上にエッチング対象膜210、ハードマスク膜220およびマスクパターン230が形成されている。ここでは、基板処理装置Sは、基体200上にエッチング対象膜210、ハードマスク膜220およびマスクパターン230が形成された基板W(図3(a)参照)に対して、前工程としてマスクパターン230を通してエッチング処理を施しハードマスク膜220に開口221を形成する(図3(b)参照)場合を例に説明する。マスクパターン230は、例えば、有機膜により形成され、ホールまたはライン状の開口を有する。また、基板処理装置Sは、後工程として開口221を有するハードマスク膜220をマスクとして、エッチング対象膜210にエッチング処理を施して開口211を形成する(図3(c)参照)場合を例に説明する。また、制御対象の特性値は、エッチング対象膜210のCD(Critical Dimension)値である場合を例に説明する。
W 基板
10 前工程処理装置
11 制御部
20 後工程処理装置
21 制御部
30 計測装置
40 全体制御装置
PM1~PM6 基板処理室
200 基体
210 エッチング対象膜
220 ハードマスク膜
230 マスクパターン
Claims (7)
- 前工程と後工程により基板に処理を施し、少なくとも前記後工程は、複数のチャンバにて並行して基板に処理を施す基板処理方法であって、
前記前工程で処理された基板を複数の前記チャンバにて並行して前記後工程の処理をする工程と、
前記チャンバごとに前記後工程の処理後の基板の特性値を取得する工程と、
前記特性値と目標値との差が小さくなるように前記後工程の処理条件を調整した際の特性値の推定値である実力値を算出する工程と、
前記チャンバごとに前記実力値と前記目標値との差である補正残差量を取得する工程と、
全チャンバの前記補正残差量の平均値を算出する工程と、
前記補正残差量の平均値に基づき、前記前工程の処理条件を補正する工程と、
前記補正残差量の平均値と前記チャンバごとの前記補正残差量とに基づき、前記チャンバごとの前記後工程の処理条件を補正する工程と、
補正された処理条件に基づいて、基板に前記前工程および前記後工程の処理を施す工程と、を有する、
基板処理方法。 - 前記特性値と前記目標値との差は、前記前工程の処理結果のばらつきを考慮して算出する、
請求項1に記載の基板処理方法。 - 前記特性値は、複数の基板の前記特性値の平均値である、
請求項1または請求項2に記載の基板処理方法。 - 前記実力値を算出する工程は、あらかじめ記憶されたプロセスパラメータに対する前記特性値の変化量を示すテーブルを参照して前記実力値を推定する、
請求項1乃至請求項3のいずれか1項に記載の基板処理方法。 - 前記前工程の処理条件を補正する工程は、あらかじめ記憶された前記補正残差量の平均値と前記前工程の処理条件とを対応付けしたテーブルを参照して行う、
請求項1乃至請求項4のいずれか1項に記載の基板処理方法。 - 前記後工程の処理条件を補正する工程は、あらかじめ記憶されたプロセスパラメータに対する前記特性値の変化量を示すテーブルを参照して行う、
請求項1乃至請求項5のいずれか1項に記載の基板処理方法。 - 前工程装置、後工程装置、制御部を備える基板処理装置であって、
前記制御部は、請求項1乃至請求項6のいずれか1項に記載の基板処理方法を実行する、
基板処理装置。
Priority Applications (4)
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JP2020066978A JP7383554B2 (ja) | 2020-04-02 | 2020-04-02 | 基板処理方法及び基板処理装置 |
TW110109911A TW202205482A (zh) | 2020-04-02 | 2021-03-19 | 基板處理方法及基板處理裝置 |
KR1020210041909A KR20210123227A (ko) | 2020-04-02 | 2021-03-31 | 기판 처리 방법 및 기판 처리 장치 |
US17/220,435 US11705374B2 (en) | 2020-04-02 | 2021-04-01 | Substrate processing method and substrate processing apparatus |
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JP (1) | JP7383554B2 (ja) |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006506812A (ja) | 2002-11-12 | 2006-02-23 | アプライド マテリアルズ インコーポレイテッド | 一体型計測を使用して誘電体エッチング効率を改善する方法及び装置 |
JP2007035777A (ja) | 2005-07-25 | 2007-02-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体製造装置 |
US20080248412A1 (en) | 2007-04-09 | 2008-10-09 | John Douglas Stuber | Supervisory etch cd control |
JP2009290150A (ja) | 2008-06-02 | 2009-12-10 | Renesas Technology Corp | 半導体装置の製造システムおよび製造方法 |
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US6891627B1 (en) * | 2000-09-20 | 2005-05-10 | Kla-Tencor Technologies Corp. | Methods and systems for determining a critical dimension and overlay of a specimen |
DE10314504B4 (de) * | 2003-03-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer nitridhaltigen Isolationsschicht durch Kompensieren von Stickstoffungleichförmigkeiten |
JP5242906B2 (ja) | 2006-10-17 | 2013-07-24 | 東京エレクトロン株式会社 | 基板処理装置の制御装置、制御方法および制御プログラムを記憶した記憶媒体 |
JP6441499B2 (ja) * | 2015-10-28 | 2018-12-19 | 東京エレクトロン株式会社 | 基板処理方法、基板処理装置、基板処理システム及び記憶媒体 |
DE102018101173B4 (de) * | 2018-01-19 | 2022-09-01 | VON ARDENNE Asset GmbH & Co. KG | Verfahren |
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- 2021-03-19 TW TW110109911A patent/TW202205482A/zh unknown
- 2021-03-31 KR KR1020210041909A patent/KR20210123227A/ko unknown
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006506812A (ja) | 2002-11-12 | 2006-02-23 | アプライド マテリアルズ インコーポレイテッド | 一体型計測を使用して誘電体エッチング効率を改善する方法及び装置 |
JP2007035777A (ja) | 2005-07-25 | 2007-02-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び半導体製造装置 |
US20080248412A1 (en) | 2007-04-09 | 2008-10-09 | John Douglas Stuber | Supervisory etch cd control |
JP2009290150A (ja) | 2008-06-02 | 2009-12-10 | Renesas Technology Corp | 半導体装置の製造システムおよび製造方法 |
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US11705374B2 (en) | 2023-07-18 |
JP2021163928A (ja) | 2021-10-11 |
KR20210123227A (ko) | 2021-10-13 |
TW202205482A (zh) | 2022-02-01 |
US20210313238A1 (en) | 2021-10-07 |
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