JP7364969B2 - 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法 - Google Patents

電磁場解析プログラム、電磁場解析装置及び電磁場解析方法 Download PDF

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JP7364969B2
JP7364969B2 JP2022553323A JP2022553323A JP7364969B2 JP 7364969 B2 JP7364969 B2 JP 7364969B2 JP 2022553323 A JP2022553323 A JP 2022553323A JP 2022553323 A JP2022553323 A JP 2022553323A JP 7364969 B2 JP7364969 B2 JP 7364969B2
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thickness
electromagnetic field
width
field analysis
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JPWO2022070329A5 (https=
JPWO2022070329A1 (https=
Inventor
崇史 山▲崎▼
昇平 山根
広明 山田
敏靖 大原
陽一 巨智部
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Fujitsu Ltd
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Fujitsu Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/10—Noise analysis or noise optimisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2022553323A 2020-09-30 2020-09-30 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法 Active JP7364969B2 (ja)

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Application Number Priority Date Filing Date Title
PCT/JP2020/037206 WO2022070329A1 (ja) 2020-09-30 2020-09-30 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法

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JPWO2022070329A1 JPWO2022070329A1 (https=) 2022-04-07
JPWO2022070329A5 JPWO2022070329A5 (https=) 2023-02-24
JP7364969B2 true JP7364969B2 (ja) 2023-10-19

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JP2022553323A Active JP7364969B2 (ja) 2020-09-30 2020-09-30 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法

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US (1) US20230204650A1 (https=)
EP (1) EP4224357A4 (https=)
JP (1) JP7364969B2 (https=)
WO (1) WO2022070329A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050086615A1 (en) 2003-10-21 2005-04-21 Anand Minakshisundaran B. Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
JP2005107870A (ja) 2003-09-30 2005-04-21 Fujitsu Ltd 解析モデル作成装置
JP2013171361A (ja) 2012-02-20 2013-09-02 Elpida Memory Inc 電気特性評価解析システム、等価回路モデル抽出方法、並びに、それらのプログラム及び記録媒体

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3776834B2 (ja) * 2001-06-20 2006-05-17 日本電気株式会社 プリント回路基板設計支援装置、方法およびプログラム
JP4086870B2 (ja) 2001-06-20 2008-05-14 日本電気株式会社 プリント回路基板設計支援装置、方法およびプログラム
EP1617309B1 (en) 2004-07-15 2011-01-12 Fujitsu Limited Simulation technique with local grid refinement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005107870A (ja) 2003-09-30 2005-04-21 Fujitsu Ltd 解析モデル作成装置
US20050086615A1 (en) 2003-10-21 2005-04-21 Anand Minakshisundaran B. Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
JP2013171361A (ja) 2012-02-20 2013-09-02 Elpida Memory Inc 電気特性評価解析システム、等価回路モデル抽出方法、並びに、それらのプログラム及び記録媒体

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Publication number Publication date
WO2022070329A1 (ja) 2022-04-07
US20230204650A1 (en) 2023-06-29
EP4224357A1 (en) 2023-08-09
EP4224357A4 (en) 2023-11-15
JPWO2022070329A1 (https=) 2022-04-07

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