JPWO2022070329A1 - - Google Patents

Info

Publication number
JPWO2022070329A1
JPWO2022070329A1 JP2022553323A JP2022553323A JPWO2022070329A1 JP WO2022070329 A1 JPWO2022070329 A1 JP WO2022070329A1 JP 2022553323 A JP2022553323 A JP 2022553323A JP 2022553323 A JP2022553323 A JP 2022553323A JP WO2022070329 A1 JPWO2022070329 A1 JP WO2022070329A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022553323A
Other languages
Japanese (ja)
Other versions
JP7364969B2 (ja
JPWO2022070329A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2022070329A1 publication Critical patent/JPWO2022070329A1/ja
Publication of JPWO2022070329A5 publication Critical patent/JPWO2022070329A5/ja
Application granted granted Critical
Publication of JP7364969B2 publication Critical patent/JP7364969B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • G06F30/27Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/36Circuit design at the analogue level
    • G06F30/367Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00Details relating to the type of the circuit
    • G06F2115/12Printed circuit boards [PCB] or multi-chip modules [MCM]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06Power analysis or power optimisation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/10Noise analysis or noise optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2022553323A 2020-09-30 2020-09-30 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法 Active JP7364969B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/037206 WO2022070329A1 (ja) 2020-09-30 2020-09-30 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法

Publications (3)

Publication Number Publication Date
JPWO2022070329A1 true JPWO2022070329A1 (https=) 2022-04-07
JPWO2022070329A5 JPWO2022070329A5 (https=) 2023-02-24
JP7364969B2 JP7364969B2 (ja) 2023-10-19

Family

ID=80949959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022553323A Active JP7364969B2 (ja) 2020-09-30 2020-09-30 電磁場解析プログラム、電磁場解析装置及び電磁場解析方法

Country Status (4)

Country Link
US (1) US20230204650A1 (https=)
EP (1) EP4224357A4 (https=)
JP (1) JP7364969B2 (https=)
WO (1) WO2022070329A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003076741A (ja) * 2001-06-20 2003-03-14 Nec Corp プリント回路基板設計支援装置、方法およびプログラム
US20050086615A1 (en) * 2003-10-21 2005-04-21 Anand Minakshisundaran B. Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
JP2005107870A (ja) * 2003-09-30 2005-04-21 Fujitsu Ltd 解析モデル作成装置
JP2006053908A (ja) * 2004-07-15 2006-02-23 Fujitsu Ltd シミュレーション手法
JP2013171361A (ja) * 2012-02-20 2013-09-02 Elpida Memory Inc 電気特性評価解析システム、等価回路モデル抽出方法、並びに、それらのプログラム及び記録媒体

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4086870B2 (ja) 2001-06-20 2008-05-14 日本電気株式会社 プリント回路基板設計支援装置、方法およびプログラム

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003076741A (ja) * 2001-06-20 2003-03-14 Nec Corp プリント回路基板設計支援装置、方法およびプログラム
JP2005107870A (ja) * 2003-09-30 2005-04-21 Fujitsu Ltd 解析モデル作成装置
US20050086615A1 (en) * 2003-10-21 2005-04-21 Anand Minakshisundaran B. Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures
JP2006053908A (ja) * 2004-07-15 2006-02-23 Fujitsu Ltd シミュレーション手法
JP2013171361A (ja) * 2012-02-20 2013-09-02 Elpida Memory Inc 電気特性評価解析システム、等価回路モデル抽出方法、並びに、それらのプログラム及び記録媒体

Also Published As

Publication number Publication date
WO2022070329A1 (ja) 2022-04-07
JP7364969B2 (ja) 2023-10-19
US20230204650A1 (en) 2023-06-29
EP4224357A1 (en) 2023-08-09
EP4224357A4 (en) 2023-11-15

Similar Documents

Publication Publication Date Title
BR112023005462A2 (https=)
BR112023012656A2 (https=)
BR112021014123A2 (https=)
BR112023009656A2 (https=)
BR112022009896A2 (https=)
BR112021017747A2 (https=)
BR112022024743A2 (https=)
BR112023011738A2 (https=)
BR112023004146A2 (https=)
BR112023006729A2 (https=)
BR102021018859A2 (https=)
BR102021015500A2 (https=)
BR102021007058A2 (https=)
BR102020022030A2 (https=)
BR112023016292A2 (https=)
BR112023011539A2 (https=)
BR112023008976A2 (https=)
BR102021020147A2 (https=)
BR102021018926A2 (https=)
BR102021018167A2 (https=)
BR102021017576A2 (https=)
BR102021016837A2 (https=)
BR102021016551A2 (https=)
BR102021016375A2 (https=)
BR102021016176A2 (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221208

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221208

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230905

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230918

R150 Certificate of patent or registration of utility model

Ref document number: 7364969

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150