JP7364376B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

Patent Document 1 discloses a semiconductor light emitting device. This semiconductor light emitting device has a structure in which a non-light emitting part and a light emitting part are joined by a first bonding metal layer and a second bonding metal layer.
The non-light-emitting portion includes a silicon substrate and a second bonding metal layer covering the silicon substrate. The light-emitting portion includes a semiconductor region that generates light, a light-transmitting layer covering the main surface of the semiconductor region, a light-reflecting layer covering the light-transmitting layer, and a first bonding metal layer covering the light-reflecting layer. include.

The light-emitting portion is arranged above the light-emitting portion with the main surface of the semiconductor region facing the main surface of the silicon substrate relating to the non-light emitting portion. In this state, the first bonding metal layer relating to the light-emitting portion is bonded to the second bonding metal layer relating to the non-light-emitting portion.

Japanese Patent Application Publication No. 2005-175462

In the semiconductor light emitting device according to Patent Document 1, light generated in the active layer passes through the first, second and third auxiliary layers and is emitted to the cathode electrode side. Therefore, it is preferable that the materials of the first, second and third auxiliary layers have a composition that does not absorb the light generated in the active layer.
However, the third auxiliary layer is an ohmic contact layer to the cathode electrode. Therefore, the material for the third auxiliary layer is limited to materials that have excellent ohmic characteristics with the cathode electrode. On the other hand, even when processing the third auxiliary layer to improve light extraction efficiency, it is desirable to avoid an increase in the forward voltage (VF) of the element as much as possible.

Accordingly, one embodiment of the present invention provides a semiconductor light emitting device and a method for manufacturing the same, which can improve light extraction efficiency while suppressing an increase in forward voltage (VF) for causing a light emitting layer to emit light.

A semiconductor light emitting device according to an embodiment of the present invention includes a substrate, a metal layer on the substrate, a light emitting layer formed on the metal layer, and a first layer disposed on the substrate side with respect to the light emitting layer. a semiconductor layer including a conductivity type layer and a second conductivity type layer disposed on the opposite side of the substrate with respect to the light emitting layer; a first electrode formed on the substrate; and a semiconductor layer on the second conductivity type layer. the second conductivity type layer includes a first layer in a connection portion with the second electrode, and the first layer is closer to the second electrode than the periphery of the second electrode. The electrode has an end in an inner region of the two electrodes, and a space is formed between the end of the first layer and the periphery of the second electrode.

Further, a method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention includes a substrate, a metal layer on the substrate, a light emitting layer formed on the metal layer, and a light emitting layer on the substrate side with respect to the light emitting layer. a semiconductor layer including a first conductivity type layer disposed, and a second conductivity type layer disposed on the opposite side of the substrate with respect to the light emitting layer, the second conductivity type layer being forming a semiconductor structure including a first layer forming a surface and a second layer disposed on the substrate side with respect to the first layer; selectively removing the first layer; a step of exposing the surface of the second layer, a step of forming an uneven portion on the surface of the second layer by frosting the exposed surface of the second layer, and after forming the uneven portion, forming a second electrode on the first layer so as to fit within an inner region of the first layer; and using a dilute nitric acid solution, move the first layer downward from the second electrode. The method includes a step of forming a space between an end of the first layer and a periphery of the second electrode by side etching, and a step of forming a first electrode on the substrate.

In this semiconductor light emitting device, light generated in the light emitting layer directly passes through the second conductivity type layer, is extracted to the second electrode side, is reflected by the metal layer, and is reflected by the first conductivity type layer and the second conductivity type layer. and is taken out to the second electrode side.
The first layer of the second conductivity type layer has an end in an area further inside the second electrode than the periphery of the second electrode, and a space is formed between the end of the first layer and the periphery of the second electrode. has been done. Thereby, all or part of the first layer does not protrude from the second electrode. Therefore, even if the first layer is composed of a composition that absorbs light generated in the light-emitting layer, the range in which light is inhibited (reflected, absorbed) on the second electrode side should be kept within the region where the second electrode is formed. I can do it. As a result, the light extraction efficiency of the semiconductor light emitting device can be improved.

On the other hand, compared to the case where the entire first layer is in contact with the second electrode, since the contact area with the second electrode is reduced, there is a concern that the forward voltage (VF) may increase. However, if the space below the second electrode is formed by side etching using a dilute nitric acid solution as in the method for manufacturing a semiconductor light emitting device, the amount of etching can be kept relatively small. An increase in the forward voltage (VF) of the semiconductor light emitting device can be suppressed.

In the semiconductor light emitting device according to an embodiment of the present invention, the second conductivity type layer includes a second layer disposed on the substrate side with respect to the first layer, and the surface of the second layer is The electrode may include a flat portion formed in a portion facing the second electrode with a space in between, and an uneven portion formed in an outer region of the second electrode.
In the semiconductor light emitting device according to an embodiment of the present invention, the flat portion may also be formed in a peripheral portion of the second electrode in the outer region of the second electrode.

In the semiconductor light emitting device according to an embodiment of the present invention, the second conductivity type layer includes a second layer disposed on the substrate side with respect to the first layer, and the surface of the second layer is The surface of the second layer includes a portion facing the second electrode with the space in between, and a portion of the surface of the second layer that is formed in an outer region of the second electrode and has a first roughness. It may further include a second uneven portion formed on the surface of each convex portion and having a second roughness smaller than the first roughness.

According to this configuration, the luminous intensity of the semiconductor light emitting device can be increased by forming the second uneven portion.
In the semiconductor light emitting device according to an embodiment of the present invention, the second uneven portion may also be formed in a peripheral portion of the second electrode in the outer region of the second electrode.
In the semiconductor light emitting device according to an embodiment of the present invention, the arithmetic mean roughness Ra of the uneven portion is 0.1 μm to 0.5 μm, and the arithmetic mean roughness Ra of the second uneven portion is 0.01 μm to 0. .1 μm may be sufficient.

In the semiconductor light emitting device according to an embodiment of the present invention, a width W ₁ of the peripheral portion of the second electrode from the peripheral edge may be 1 μm to 3 μm.
In the semiconductor light emitting device according to an embodiment of the present invention, the second electrode includes a pad electrode portion to which a bonding member is connected, and a branch electrode portion extending in a branch shape from the pad electrode portion, and the space is , the space may be formed below the branch electrode portion, and a width W ₂ of the space from the periphery of the branch electrode portion may be less than 1/2 of a width W ₃ of the branch electrode portion. .

In the semiconductor light emitting device according to an embodiment of the present invention, the width W ₃ of the branch electrode portion may be 6 μm to 8 μm, and the width W ₂ of the space may be 1 μm to 2 μm.
In the semiconductor light emitting device according to an embodiment of the present invention, the first layer of the second conductivity type layer may include an n-type GaAs contact layer.
The semiconductor light emitting device according to an embodiment of the present invention may further include a transparent conductive layer formed between the metal layer and the semiconductor layer.

In the semiconductor light emitting device according to one embodiment of the present invention, the transparent conductive layer may contain ITO (indium tin oxide), ZnO (zinc oxide), or IZO (indium zinc oxide).
The semiconductor light emitting device according to an embodiment of the present invention further includes an insulating layer formed between the metal layer and the semiconductor layer and selectively having a contact hole, and the metal layer is formed between the metal layer and the semiconductor layer through the contact hole. and may be electrically connected to the first conductivity type layer.

In the semiconductor light emitting device according to one embodiment of the present invention, the insulating layer may contain SiO ₂ , SiN, or MgF ₂ .
In the semiconductor light emitting device according to one embodiment of the present invention, the metal layer may contain Au.
In the semiconductor light emitting device according to one embodiment of the present invention, the substrate may include a Si substrate.

In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, after the space is formed, diluted hydrochloric acid is used to form a portion of the second layer facing the second electrode with the space interposed therebetween and the uneven portion. It may include a step of frosting.
In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the first layer of the second conductivity type layer includes an n-type GaAs contact layer, and the step of forming the second electrode includes Au and Ge. A first step of evaporating a first evaporation material containing Ni and depositing it on the n-type contact layer to form a layer containing Au and Ge, and after the first step, evaporating a second evaporation material containing Ni. , a second step of depositing on the layer containing Au and Ge to form a layer containing Ni.

With this method, the amount of side etching of the first layer can be suppressed. As a result, a decrease in the contact area between the second electrode and the first layer (n-type GaAs contact layer) is suppressed, and an increase in forward voltage (VF) can be suppressed.
In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the weight ratio of the Ni to the total amount of the Au, Ge, and Ni may be 20 wt% or more.

In the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, the step of forming the semiconductor structure includes forming the second conductivity type layer, the light emitting layer, the first conductivity type layer and the first conductivity type layer on the first substrate. forming one metal layer in this order; forming a second metal layer on a second substrate; and bonding the first metal layer and the second metal layer to each other to form the metal layer. The method may include a step of bonding the first substrate and the second substrate together, and a step of removing the first substrate after the bonding.

FIG. 1 is a plan view of a semiconductor light emitting device according to a first embodiment of the invention. FIG. 2 is a cross-sectional view of the semiconductor light emitting device according to the first embodiment of the present invention, and is a diagram showing the II-II cross section in FIG. FIG. 3A is an enlarged view of main parts of the semiconductor light emitting device shown in FIG. 2. FIG. FIG. 3B is a reference diagram for comparison with the structure of FIG. 3A. FIG. 4A is an enlarged view of essential parts of the semiconductor light emitting device shown in FIG. 1. FIG. FIG. 4B is an enlarged view of essential parts of the semiconductor light emitting device shown in FIG. 1. FIG. 5A is a diagram showing a part of the method for manufacturing the semiconductor light emitting device. FIG. 5B is a diagram showing the next step after FIG. 5A. FIG. 5C is a diagram showing the next step after FIG. 5B. FIG. 5D is a diagram showing the next step after FIG. 5C. FIG. 5E is a diagram showing the next step after FIG. 5D. FIG. 5F is a diagram showing the next step after FIG. 5E. FIG. 5G is a diagram showing the next step after FIG. 5F. FIG. 5H is a diagram showing the next step after FIG. 5G. FIG. 5I is a diagram showing the next step after FIG. 5H. FIG. 6A is a diagram illustrating a part of the process related to side etching of the n-type contact layer. FIG. 6B is a diagram showing the next step after FIG. 6A. FIG. 6C is a diagram showing the next step after FIG. 6B. FIG. 7 is a diagram showing the relationship between the etching solution used for side etching of the n-type contact layer, the rate of increase in forward voltage (VF), and the rate of increase in luminous flux. FIG. 8 is a plan view of a semiconductor light emitting device according to a second embodiment of the invention. FIG. 9 is a cross-sectional view of a semiconductor light emitting device according to a second embodiment of the present invention, and is a diagram showing a cross section taken along line IX-IX in FIG. FIG. 10A is a diagram showing a part of the method for manufacturing the semiconductor light emitting device. FIG. 10B is a diagram showing the next step after FIG. 10A. FIG. 10C is a diagram showing the next step after FIG. 10B. FIG. 10D is a diagram showing the next step after FIG. 10C. FIG. 10E is a diagram showing the next step after FIG. 10D. FIG. 10F is a diagram showing the next step after FIG. 10E. FIG. 10G is a diagram showing the next step after FIG. 10F. FIG. 10H is a diagram showing the next step after FIG. 10G. FIG. 10I is a diagram showing the next step after FIG. 10H. FIG. 10J is a diagram showing the next step from FIG. 10I. FIG. 11 is an enlarged view of essential parts of the semiconductor light emitting device shown in FIG. 2. FIG. 12 is an enlarged view of the main part of FIG. 11. FIG. 13A is a diagram showing steps related to forming the uneven structure shown in FIG. 12. FIG. 13B is a diagram showing the next step after FIG. 13A. FIG. 14A is a diagram showing the state of light transmission in the uneven structure of FIG. 12. FIG. 14B is a diagram for comparison with the light transmission situation in FIG. 14A. FIG. 15 is a diagram showing the Iv increase rate of the semiconductor light emitting device. FIG. 16 is a diagram showing the relationship between frost time and Iv increase rate. FIG. 17A is a diagram showing the first structure of the cathode electrode layer. FIG. 17B is a diagram showing a second structure of the cathode electrode layer. FIG. 18 is a diagram showing the relationship between the Ni film thickness and the VF increase rate. FIG. 19 is a diagram showing the relationship between the AuGe film thickness and the VF increase rate. FIG. 20 is a diagram showing the relationship between the content ratio of Ni to AuGe/Ni and the VF increase rate. FIG. 21 is a schematic diagram of a TEM image of the cathode electrode layer (Ni content: 43.5%). FIG. 22 is a schematic diagram of a TEM image of the cathode electrode layer (Ni content: 19.4%). FIG. 23 is a schematic diagram of a TEM image of the cathode electrode layer (Ni content: 3.9%). FIG. 24 is a diagram showing the element distribution obtained by AES analysis from the surface of the cathode electrode layer (Ni content: 43.5%) toward the depth direction. FIG. 25 is a diagram showing the element distribution obtained by AES analysis from the surface of the cathode electrode layer (Ni content: 19.4%) toward the depth direction. FIG. 26 is a diagram showing the element distribution obtained by AES analysis from the surface of the cathode electrode layer (Ni content: 3.9%) toward the depth direction. FIG. 27 is a diagram showing the VF increase rate of semiconductor light emitting devices by lot. FIG. 28 is a diagram showing a modification of the pattern of the cathode electrode layer.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a plan view of a semiconductor light emitting device 1 according to a first embodiment of the invention. FIG. 2 is a cross-sectional view of the semiconductor light emitting device 1 according to the first embodiment of the present invention, and is a diagram showing the II-II cross section in FIG.
A semiconductor light emitting device 1 includes a substrate 2 having a first surface 3 and a second surface 4, a metal layer 5 on the substrate 2, a light-transmitting conductive layer 6 on the metal layer 5, and a structure formed on the light-transmitting conductive layer 6. A compound semiconductor layer 7 as an example of a semiconductor layer of the present invention having a first surface 8 and a second surface 9, and a first electrode of the present invention formed so as to be in contact with the second surface 4 of the substrate 2. It includes an anode electrode layer 10 as an example, and a cathode electrode layer 11 as an example of the second electrode of the present invention formed so as to be in contact with the first surface 8 of the compound semiconductor layer 7.

The first surface 3 and second surface 4 of the substrate 2 and the first surface 8 and second surface 9 of the compound semiconductor layer 7 are respectively referred to as the front surface and the back surface of the substrate 2 and the front surface and the back surface of the compound semiconductor layer 7. It's okay.
The substrate 2 may include a conductor substrate made of a metal material. The conductive substrate may contain at least one of Al (aluminum), Cu (copper), Au (gold), and Ag (silver) as a metal material.

The substrate 2 may include a semiconductor substrate made of a semiconductor material instead of or in addition to the conductor substrate. The semiconductor substrate may contain at least one of Si (silicon), silicon carbide (SiC), germanium (Ge), a compound semiconductor, or a nitride semiconductor as a semiconductor material. An example in which the substrate 2 is a semiconductor substrate made of Si will be described below.

Further, in this embodiment, the substrate 2 is formed into a substantially square shape in plan view, but the planar shape of the substrate 2 is not particularly limited, and may be rectangular in plan view, for example. good. Further, the thickness of the substrate 2 may be, for example, 50 μm to 300 μm.
In this embodiment, the metal layer 5 is made of Au or an alloy containing Au. The metal layer 5 may be a single layer of each of the Au layer and the Au alloy layer, or may be a layer in which a plurality of these layers and other metal layers are laminated. When the metal layer 5 has a multilayer structure, it is preferable that at least the contact surface with the transparent conductive layer 6 is composed of an Au layer or an Au alloy layer (for example, AuBeNi, etc.). An example is a laminated structure shown by Au/Ti (on the side of the transparent conductive layer 6) and Au/Ti (on the side of the substrate 2). Furthermore, even if the metal layer 5 is configured such that clear boundaries are not formed between the plurality of metal materials constituting the metal layer 5, and the plurality of metal materials are distributed one after another from the substrate 2 side, for example, good. On the other hand, in this embodiment, the metal layer 5 is formed by bonding the growth substrate 35 (described later) and the substrate 2 to form a first metal layer 37 (described later) and a second metal layer 38 (described later). It is formed by joining. Therefore, a boundary (bonding surface) between the first metal layer 37 and the second metal layer 38 may exist midway in the thickness direction of the Au layer constituting the metal layer 5.

Further, the metal layer 5 is formed to cover the entire first surface 3 of the substrate 2. Further, the (total) thickness of the metal layer 5 may be, for example, 0.1 μm to 3.0 μm.
The light-transmitting conductive layer 6 may be made of any material that is transparent to the emission wavelength of the light-emitting layer 12, which will be described later, such as ITO (indium tin oxide), ZnO (zinc oxide) or IZO (indium oxide). Zinc).

Further, the light-transmitting conductive layer 6 is formed to cover the entire surface of the metal layer 5. Further, the (total) thickness of the transparent conductive layer 6 may be, for example, 0.05 μm to 0.5 μm.
In this form, the compound semiconductor layer 7 is composed of an epitaxial layer formed by an epitaxial growth method.
Specifically, the compound semiconductor layer 7 includes a light emitting layer 12, a p-type semiconductor layer 13, and an n-type semiconductor layer 14. The p-type semiconductor layer 13 is arranged on the substrate 2 side with respect to the light-emitting layer 12, and the n-type semiconductor layer 14 is arranged on the cathode electrode layer 11 side with respect to the light-emitting layer 12. In this way, the light emitting layer 12 is sandwiched between the p-type semiconductor layer 13 and the n-type semiconductor layer 14, forming a double heterojunction. Electrons are injected into the light emitting layer 12 from the n-type semiconductor layer 14 and holes are injected from the p-type semiconductor layer 13. By recombining these in the light emitting layer 12, light is generated.

The p-type semiconductor layer 13 includes, in order from the substrate 2 side, a p-type contact layer 15 (for example, 0.1 μm to 2.5 μm thick), a p-type window layer 16 (for example, 0.1 μm to 2.5 μm thick), and a p-type contact layer 15 (for example, 0.1 μm to 2.5 μm thick). It is constructed by laminating mold cladding layers 17 (for example, 0.1 μm to 2.5 μm thick). On the other hand, the n-type semiconductor layer 14 is formed, in order, on the light-emitting layer 12, including an n-type cladding layer 18 (for example, 0.1 μm to 2.5 μm thick) and an n-type window layer as an example of the second layer of the present invention. 19 (for example, 2.0 μm to 5.0 μm thick) and an n-type contact layer 20 (for example, 0.1 μm to 2.5 μm thick) as an example of the first layer of the present invention.

P-type contact layer 15 and n-type contact layer 20 are low resistance layers for establishing ohmic contact with transparent conductive layer 6 and cathode electrode layer 11, respectively. The p-type contact layer 15 may be made into a p-type semiconductor by doping GaP with, for example, C (carbon) as a p-type dopant at a high concentration. Further, the n-type contact layer 20 may be made into an n-type semiconductor layer by doping GaAs with, for example, Si as an n-type dopant at a high concentration.

The p-type window layer 16 may be made into a p-type semiconductor by doping GaP with, for example, Mg as a p-type dopant. On the other hand, the n-type window layer 19 may be made into an n-type semiconductor layer by doping AlInGaP with, for example, Si as an n-type dopant.
The p-type cladding layer 17 may be made into a p-type semiconductor by doping AlInP with, for example, Mg as a p-type dopant. On the other hand, the n-type cladding layer 18 may be made into an n-type semiconductor layer by doping AlInP with Si as an n-type dopant.

The light emitting layer 12 has an MQW (multiple-quantum well) structure containing, for example, InGaP, and light is generated by recombination of electrons and holes, and the generated light is This is a layer for amplification.
In this embodiment, the light emitting layer 12 is a multiple quantum well formed by alternately stacking a quantum well layer made of an InGaP layer (for example, 5 nm thick) and a barrier layer made of an AlInGaP layer (for example, 4 nm thick) in a plurality of cycles. (MQW: Multiple-Quantum Well) structure. In this case, the quantum well layer made of InGaP has a relatively small band gap due to the In composition ratio being 5% or more, and the barrier layer made of AlInGaP has a relatively large band gap. For example, quantum well layers (InGaP) and barrier layers (AlInGaP) are alternately stacked repeatedly for 10 to 40 cycles, thereby forming the light emitting layer 12 having a multiple quantum well structure. The emission wavelength corresponds to the bandgap of the quantum well layer, and the bandgap can be adjusted by adjusting the composition ratio of In. As the composition ratio of In increases, the band gap decreases and the emission wavelength increases. In this embodiment, the emission wavelength is set to 610 nm to 680 nm (for example, 625 nm) by adjusting the In composition in the quantum well layer (InGaP layer).

As shown in FIGS. 1 and 2, the compound semiconductor layer 7 forms a mesa portion 21 by partially removing it. More specifically, part of the n-type semiconductor layer 14, the light-emitting layer 12, and the p-type semiconductor layer 13 are etched away from the first surface 8 of the compound semiconductor layer 7 over the entire circumference of the compound semiconductor layer 7, A mesa portion 21 having a substantially rectangular shape in cross section is formed. The shape of the mesa portion 21 is not limited to a substantially rectangular shape in cross section, but may be trapezoidal, for example. As a result, the p-type window layer 16 of the p-type semiconductor layer 13 and the layer closer to the substrate 2 than this form a lead-out portion 22 drawn out from the mesa portion 21 in the lateral direction. As shown in FIG. 1, the mesa portion 21 is surrounded by the drawer portion 22 in plan view.

In this embodiment, an uneven portion 23 is formed on the surface of the mesa portion 21 . The uneven portions 23 can diffuse the light extracted from the compound semiconductor layer 7. In this embodiment, as described later, the n-type window layer 19 is exposed by selectively removing the n-type contact layer 20 according to the shape of the cathode electrode layer 11, and the uneven portion 23 is formed on this exposed surface. is formed. Note that in FIG. 1, the uneven portion 23 is omitted for clarity.

In this embodiment, the anode electrode layer 10 as a back electrode is made of Au or an alloy containing Au. Specifically, a laminated structure shown by Ti/Au (on the substrate 2 side) may be used. Further, the anode electrode layer 10 is formed to cover the entire second surface 4 of the substrate 2.
In this embodiment, the cathode electrode layer 11 as a surface electrode is made of Au or an alloy containing Au. Specifically, it may be a stacked structure of AuGeNi/Au (on the compound semiconductor layer 7 side).

The cathode electrode layer 11 also integrates a pad electrode part 24 and a branch-like electrode part 25 that selectively extends in a branch shape from the pad electrode part 24 so as to partition a certain area around the pad electrode part 24. including.
In this embodiment, the pad electrode section 24 is arranged approximately at the center of the mesa section 21 in plan view. A branch electrode portion 25 extends from the pad electrode portion 24 toward each peripheral edge of the mesa portion 21 in a cross shape, and a branch intersects with the cross-shaped branch electrode portion 25 and extends along each peripheral edge of the mesa portion 21. A shaped electrode portion 25 is formed. In this embodiment, since the n-type contact layer 20 has substantially the same shape as the cathode electrode layer 11, the n-type window layer 19 is exposed from the region other than the region where the cathode electrode layer 11 is formed. There is.

FIG. 3A is an enlarged view of main parts of the semiconductor light emitting device 1 shown in FIG. 2. FIG. FIG. 3B is a reference diagram for comparison with the structure of FIG. 3A. FIG. 4A is an enlarged view of essential parts of the semiconductor light emitting device 1 shown in FIG. 1. FIG. FIG. 4B is an enlarged view of main parts of the semiconductor light emitting device 1 shown in FIG. 1.
Next, more detailed structures of the n-type semiconductor layer 14 and the cathode electrode layer 11 will be described with reference to FIGS. 3A, 3B, 4A, and 4B.

As shown in FIGS. 1 and 2, the n-type contact layer 20 has approximately the same shape as the cathode electrode layer 11, but more specifically, the n-type contact layer 20 It has an end portion 27 in the inner region of the cathode electrode layer 11, and is formed to be slightly smaller than the cathode electrode layer 11 in plan view. As a result, between the end 27 of the n-type contact layer 20 and the periphery 26 of the cathode electrode layer 11, there are the lower surface 28 of the cathode electrode layer 11, the end 27 of the n-type contact layer 20, and the n-type window layer 19. A space 30 is defined by the upper surface 29.

Here, the periphery 26 of the cathode electrode layer 11 is, for example, as shown in FIG. It may also be the lower edge of the layer 11. Moreover, the cathode electrode layer 11 may have a laminated structure of the AuGeNi layer 31 and the Au layer 32, as described above. The thickness of the AuGeNi layer 31 may be 1000 Å to 5000 Å, and the thickness of the Au layer 32 may be 17000 Å.

The space 30 below the cathode electrode layer 11 is continuous along the entire periphery 26 of the cathode electrode layer 11 (pad electrode section 24 and branch electrode section 25), as shown in FIGS. 4A and 4B. It is formed. More specifically, in the pad electrode section 24, a circular space 30 may be formed along the entire circumference of the circumferential edge 26 of the pad electrode section 24, which is circular in plan view. Further, in the branch-like electrode section 25 , it may be formed below both ends in the width direction of the branch-like electrode section 25 along the longitudinal direction of the linear peripheral edge 26 of the branch-like electrode section 25 .

In this embodiment, the width W ₂ of the space 30 from the peripheral edge 26 of the branch electrode portion 25 (the total width of the two spaces 30 formed at both ends in the width direction), the width W of the branch electrode portion 25 Preferably, it is less than 1/2 of ₃ . More specifically, the width W ₃ of the branch electrode portion 25 may be 6 μm to 8 μm, and the width W ₂ of the space 30 may be 1 μm to 2 μm. In this way, a relatively large contact area between the cathode electrode layer 11 and the n-type contact layer 20 can be secured even in the branch-like electrode section 25 which is thinner than the pad electrode section 24 (for example, the diameter _D1 is 80 μm to 100 μm). Therefore, an increase in the forward voltage (VF) of the semiconductor light emitting device 1 can be suppressed.

Further, in addition to the above-mentioned uneven portions 23, the n-type window layer 19 has a flat portion 33 on its upper surface 29, which has no unevenness or is smoother than the uneven portions 23. The flat portion 33 is located in the space 30 below the cathode electrode layer 11 (that is, the upper surface 29 of the n-type window layer 19 facing the cathode electrode layer 11 with the space 30 in between) and in the outer region of the cathode electrode layer 11. It is formed in the peripheral portion 34 of the cathode electrode layer 11 .

The peripheral portion 34 of the cathode electrode layer 11 is covered with an n-type contact layer 20 around the cathode electrode layer 11 before the side etching process described below (see FIG. 6B), and the area exposed after the side etching process (see FIG. 6B). 6C). For example, the width W ₁ of the peripheral portion 34 from the peripheral edge 26 of the cathode electrode layer 11 may be 1 μm to 3 μm.
5A to 5I are diagrams illustrating the manufacturing process of the semiconductor light emitting device 1 of FIGS. 1 and 2 in order of process. Further, FIGS. 6A to 6C are diagrams showing steps related to side etching of the n-type contact layer 20.

To manufacture the semiconductor light emitting device 1, for example, as shown in FIG. 5A, a compound semiconductor layer 7 is formed by epitaxial growth on a growth substrate 35 made of GaAs or the like and serving as an example of the first substrate of the present invention. As the growth method, for example, a known growth method such as molecular beam epitaxial growth method or metal organic vapor phase epitaxy method can be applied. At this stage, the compound semiconductor layer 7 is formed in order from the side of the growth substrate 35: the n-type etching stop layer 36, the n-type contact layer 20, the n-type window layer 19, the n-type cladding layer 18, the light emitting layer 12, and the p-type cladding layer 36. layer 17 , p-type window layer 16 and p-type contact layer 15 . After the compound semiconductor layer 7 is formed, the light-transmitting conductive layer 6 is formed by, for example, a vapor deposition method.

Next, as shown in FIG. 5B, a first metal layer 37 (eg, 2.0 μm thick) is formed on the transparent conductive layer 6 by, for example, a vapor deposition method. The first metal layer 37 is made of Au or an alloy containing Au, and at least the outermost surface thereof is made of an Au layer.
The next step is a step of bonding the growth substrate 35 and the substrate 2, which is an example of the second substrate of the present invention. In the bonding process, the first metal layer 37 on the growth substrate 35 and the second metal layer 38 on the substrate 2 are bonded. The second metal layer 38 is made of Au or an alloy containing Au, and at least the outermost surface thereof is made of an Au layer. This second metal layer 38 is formed on the first surface 3 of the substrate 2 by, for example, a vapor deposition method before bonding.

More specifically, as shown in FIG. 5C, the growth substrate 35 and the substrate 2 are stacked on top of each other with the first and second metal layers 37 and 38 facing each other, and the first and second metal layers 37, 38 is joined. The first and second metal layers 37 and 38 may be joined by thermocompression bonding, for example. The conditions for thermocompression bonding may be, for example, a temperature of 250° C. to 350° C. and a pressure of 30 kN to 45 kN. Through this bonding, the first and second metal layers 37 and 38 are combined to form the metal layer 5, as shown in FIG. 5D.

Next, as shown in FIG. 5D, the growth substrate 35 is removed, for example by wet etching. Here, since the n-type etching stop layer 36 is formed on the outermost surface of the compound semiconductor layer 7, during the wet etching, the n-type contact layer 20 and the n-type window that contribute to the characteristics of the semiconductor light emitting device 1 are removed. There is no need to affect layer 19 and the like. Thereafter, the n-type etching stop layer 36 is also removed.

The next steps are a step of making the n-type window layer 19 uneven, a step of forming the cathode electrode layer 11, and a step of side etching the n-type contact layer 20.
First, as shown in FIG. 5E, a resist 39 having openings having substantially the same pattern as the electrode pattern of the cathode electrode layer 11 is formed on the n-type contact layer 20. Thereafter, the n-type contact layer 20 exposed from the resist 39 is removed by etching. As a result, the n-type window layer 19 is exposed in a portion other than the resist 39.

Next, as shown in FIG. 5F, an uneven portion 23 is formed on the surface of the n-type window layer 19 exposed from the resist 39 by, for example, frosting (wet etching) or the like. Note that the frost treatment may be performed by dry etching. Examples of the etching solution used include dilute hydrochloric acid. As a more specific product name, "Pure Etch150" manufactured by Hayashi Pure Chemical Industries, Ltd. can be used. Further, the etching time may be, for example, 10 seconds to 100 seconds, preferably 50 seconds to 100 seconds. By continuing the etching for 50 seconds or more, the uneven portion 23 can be formed in good quality. Further, the etching temperature may be, for example, 30°C to 60°C.

After that, the resist 39 is removed. FIG. 6A is an enlarged view of the main part after the resist 39 is removed.
Next, as shown in FIG. 6B, the cathode electrode layer 11 is formed by stacking the AuGeNi layer 31 and the Au layer 32 on the n-type contact layer 20. Cathode electrode layer 11 may be formed, for example, by a lift-off method.

In the lift-off method, although not shown, a resist having an opening with approximately the same pattern as the n-type contact layer 20 (more specifically, taking into account some misalignment of the resist, a resist that is slightly smaller than the n-type contact layer 20) is used. A resist having an opening is formed on the compound semiconductor layer 7. Next, an electrode material film for the cathode electrode layer 11 is laminated on the compound semiconductor layer 7 by, for example, a vapor deposition method. Then, the electrode material film on the resist is removed together with the resist. As a result, as shown in FIGS. 5G and 6B, the cathode electrode layer 11 made of the electrode material film remaining on the n-type contact layer 20 is formed. At this time, the end portion 27 of the n-type contact layer 20 is arranged in the peripheral portion 34 outside the peripheral edge 26 of the cathode electrode layer 11 . In other words, as a result of using a resist that takes the above-mentioned misalignment into account, the n-type contact layer 20 has a portion 40 that protrudes outward from the cathode electrode layer 11.

Next, as shown in FIG. 6C, a space 30 is formed by side etching the n-type contact layer 20 toward the bottom of the cathode electrode layer 11 by wet etching using a dilute nitric acid solution. Further, the upper surface 29 of the n-type window layer 19, which was covered with the n-type contact layer 20 before side etching, is exposed as a flat portion 33 because it was protected by the n-type contact layer 20 during the uneven processing.

The dilute nitric acid solution may be, for example, an etching solution containing less than 10% nitric acid. Further, the etching time may be, for example, 10 seconds to 60 seconds, and the temperature may be, for example, 15° C. to 25° C.
Next, as shown in FIG. 5H, the peripheral portion of the compound semiconductor layer 7 is selectively removed, thereby forming the mesa portion 21 and the extended portion 22. The mesa portion 21 and the lead-out portion 22 may be formed by, for example, wet etching.

Next, as shown in FIG. 5I, an anode electrode layer 10 is formed on the second surface 4 of the substrate 2 by, for example, a vapor deposition method. Through the above steps, the semiconductor light emitting device 1 is obtained.
As described above, in this semiconductor light emitting device 1, the light generated in the light emitting layer 12 directly passes through the n-type semiconductor layer 14, is extracted to the cathode electrode layer 11 side, is reflected by the metal layer 5, and is reflected by the p-type semiconductor layer 13. And it passes through the n-type semiconductor layer 14 and is taken out to the cathode electrode layer 11 side.

In this embodiment, as shown in FIG. 3A, the n-type contact layer 20 of the n-type semiconductor layer 14 has an end portion 27 in the inner region of the cathode electrode layer 11 than the periphery 26 of the cathode electrode layer 11; A space 30 is formed between the end 27 of the mold contact layer 20 and the peripheral edge 26 of the cathode electrode layer 11 . As a result, all or part of the n-type contact layer 20 does not protrude from the cathode electrode layer 11.

Therefore, even if the n-type contact layer 20 is made of a composition such as GaAs that absorbs the light generated in the light emitting layer 12 (for example, the wavelength range is 610 nm to 680 nm), the light is inhibited on the cathode electrode layer 11 side. (Reflection, absorption) can be kept within the region where the cathode electrode layer 11 is formed. As a result, the light extraction efficiency of the semiconductor light emitting device 1 can be improved.

On the other hand, in the reference example shown in FIG. 3B in which the side etching shown in FIG. 6C is not performed, the n-type contact layer 20 has a portion 40 that protrudes outside the cathode electrode layer 11. In this configuration, in addition to the cathode electrode layer 11 which is a metal layer and thus originally inhibits light emission, light emission is also restricted in the peripheral portion 34 of the cathode electrode layer 11 due to absorption by the n-type contact layer 20. There are cases.

Furthermore, compared to the case where the entire n-type contact layer 20 is in contact with the cathode electrode layer 11, since the contact area with the cathode electrode layer 11 is reduced, there is a concern that the forward voltage (VF) may increase. However, if the space 30 below the cathode electrode layer 11 is formed by side etching using a dilute nitric acid solution as in the manufacturing method of the semiconductor light emitting device 1 of this embodiment, the amount of etching can be made relatively small. Therefore, an increase in the forward voltage (VF) of the semiconductor light emitting device 1 can be suppressed.

The effect of suppressing the increase in forward voltage (VF) can be explained with reference to FIG. 7, for example.
FIG. 7 shows the forward voltage (VF) after performing the side etching process shown in FIG. 6C using a dilute nitric acid solution (etching time: 10 seconds, 30 seconds, 60 seconds) and other chemical solutions (sulfuric acid peroxide). The rate of increase in luminous flux and the rate of increase in luminous flux are shown.
According to FIG. 7, when side etching was performed using other chemical solutions, the luminous flux could be increased by approximately 15% compared to before performing side etching, but on the other hand, the forward voltage (VF) was approximately 3 It also rose by .8. On the other hand, when side etching is performed using a dilute nitric acid solution, the luminous flux can be increased by about 15% regardless of the etching time, and the rate of increase in forward voltage (VF) can be kept to about 1%. Ta.

A large increase in forward voltage (VF) when using other chemical solutions results in an excessively high etching rate and an excessive increase in the amount of side etching. This is thought to be due to a significant decrease in the contact area with the
FIG. 8 is a plan view of a semiconductor light emitting device 41 according to a second embodiment of the invention. FIG. 9 is a cross-sectional view of a semiconductor light emitting device 41 according to a second embodiment of the present invention, and is a view taken along the line IX-IX in FIG. In FIGS. 8 and 9, the same elements as those shown in FIGS. 1 and 2 described above are denoted by the same reference numerals, and the explanation thereof will be omitted.

In the semiconductor light emitting device 41, an insulating layer 42 is disposed between the transparent conductive layer 6 and the compound semiconductor layer 7.
Insulating layer 42 may consist of SiO ₂ , SiN or MgF ₂ in this embodiment. Further, the insulating layer 42 is formed to cover the entire surface of the transparent conductive layer 6. Further, the (total) thickness of the insulating layer 42 may be, for example, 0.1 μm to 0.5 μm.

On the other hand, since the transparent conductive layer 6 and the compound semiconductor layer 7 are separated by the insulating layer 42, the transparent conductive layer 6 is connected to the p-type contact layer 15 through the contact hole 43 penetrating the insulating layer 42. It has a connected contact portion 44. As a result, the semiconductor light emitting device 41 has an ODR (Omni-Directional-Reflector) structure.
The contact portions 44 are arranged discretely within the plane of the substrate 2, as shown in FIG. For example, they may be arranged in a matrix within the mesa portion 21 which has a rectangular shape in plan view.

Further, as shown in FIG. 9, each contact portion 44 may have a tapered shape in a cross-sectional view that tapers toward the compound semiconductor layer 7.
Although not shown, the space 30 shown in FIG. 3A is also formed below the cathode electrode layer 11 of the semiconductor light emitting device 41 according to the second embodiment.
10A to 10J are diagrams illustrating the manufacturing process of the semiconductor light emitting device 41 of FIGS. 8 and 9 in order of process.

To manufacture the semiconductor light emitting device 41, for example, as shown in FIG. 10A, a compound semiconductor layer 7 is formed by epitaxial growth on a growth substrate 35, which is an example of the first substrate of the present invention and is made of GaAs or the like. As the growth method, for example, a known growth method such as molecular beam epitaxial growth method or metal organic vapor phase epitaxy method can be applied. At this stage, the compound semiconductor layer 7 is formed in order from the side of the growth substrate 35: the n-type etching stop layer 36, the n-type contact layer 20, the n-type window layer 19, the n-type cladding layer 18, the light emitting layer 12, and the p-type cladding layer 36. layer 17 , p-type window layer 16 and p-type contact layer 15 . After the compound semiconductor layer 7 is formed, the insulating layer 42 is formed by, for example, a CVD method. Thereafter, the contact hole 43 is formed by selectively etching the insulating layer 42.

Next, as shown in FIG. 10B, a light-transmitting conductive layer 6 is formed on the insulating layer 42 by, for example, a vapor deposition method. Transparent conductive layer 6 enters contact hole 43 and is connected to p-type contact layer 15 .
Next, as shown in FIG. 10C, a first metal layer 37 (eg, 2.0 μm thick) is formed on the transparent conductive layer 6 by, for example, a vapor deposition method. The first metal layer 37 is made of Au or an alloy containing Au, and at least the outermost surface thereof is made of an Au layer.

The next step is a step of bonding the growth substrate 35 and the substrate 2 together. In the bonding process, the first metal layer 37 on the growth substrate 35 and the second metal layer 38 on the substrate 2 are bonded. The second metal layer 38 is made of Au or an alloy containing Au, and at least the outermost surface thereof is made of an Au layer. This second metal layer 38 is formed on the first surface 3 of the substrate 2 by, for example, a vapor deposition method before bonding.

More specifically, as shown in FIG. 10D, the growth substrate 35 and the substrate 2 are stacked with the first and second metal layers 37 and 38 facing each other, and the first and second metal layers 37 and 38 are stacked on top of each other. 38 is joined. The first and second metal layers 37 and 38 may be joined by thermocompression bonding, for example. The conditions for thermocompression bonding may be, for example, a temperature of 250° C. to 350° C. and a pressure of 30 kN to 45 kN. By this bonding, the first and second metal layers 37 and 38 are combined to form the metal layer 5, as shown in FIG. 10E.

Next, as shown in FIG. 10E, growth substrate 35 is removed, for example, by wet etching. Here, since the n-type etching stop layer 36 is formed on the outermost surface of the compound semiconductor layer 7, during the wet etching, the n-type contact layer 20 and the n-type window that contribute to the characteristics of the semiconductor light emitting device 41 are removed. There is no need to affect layer 19 and the like. Thereafter, the n-type etching stop layer 36 is also removed.

The next steps are a step of making the n-type window layer 19 uneven, a step of forming the cathode electrode layer 11, and a step of side etching the n-type contact layer 20.
First, as shown in FIG. 10F, a resist 39 having openings having substantially the same pattern as the electrode pattern of the cathode electrode layer 11 is formed on the n-type contact layer 20. Thereafter, the n-type contact layer 20 exposed from the resist 39 is removed by etching. As a result, the n-type window layer 19 is exposed in a portion other than the resist 39.

Next, as shown in FIG. 10G, an uneven portion 23 is formed on the surface of the n-type window layer 19 exposed from the resist 39 by, for example, frosting (wet etching) or the like. Note that the frost treatment may be performed by dry etching. After that, the resist 39 is removed.
After that, the cathode electrode layer 11 is formed according to the steps shown in FIGS. 6A to 6C (see also FIG. 10H), and side etching of the n-type contact layer 20 is performed.

Next, as shown in FIG. 10I, a peripheral portion of the compound semiconductor layer 7 is selectively removed, thereby forming a mesa portion 21 and a lead-out portion 22. The mesa portion 21 and the lead-out portion 22 may be formed by, for example, wet etching.
Next, as shown in FIG. 10J, an anode electrode layer 10 is formed on the second surface 4 of the substrate 2 by, for example, a vapor deposition method. Through the above steps, a semiconductor light emitting device 41 is obtained.

As described above, also in this semiconductor light emitting device 41, since the space 30 is formed between the end portion 27 of the n-type contact layer 20 and the peripheral edge 26 of the cathode electrode layer 11, the same effect as in the semiconductor light emitting device 1 described above is achieved. effect can be achieved.
Next, preferred structures of the semiconductor light emitting devices 1 and 41 will be described. More specifically, the compound semiconductor layer 7 is frosted in two stages (double frosting), and the AuGeNi layer 31 of the cathode electrode layer 11 is vapor-deposited with AuGe and Ni separated. The form (divisional deposition of AuGe/Ni) will be explained.
<Double frost treatment>
FIG. 11 is an enlarged view of essential parts of the semiconductor light emitting device 1 shown in FIG. 2. As shown in FIG. FIG. 12 is an enlarged view of the main part of FIG. 11.

First, in the above-described embodiment, as shown in FIG. 5F, the frosting process is performed only once, so that the uneven portion 23 is formed in the n-type window layer 19. On the other hand, in this embodiment, in addition to the uneven portion 23, a second uneven portion 50 (see FIG. 12) is formed in the processing region 49 shown by a thick solid line in FIG. The processing region 49 includes the entire n-type window layer 19 exposed from the n-type contact layer 20 and includes both the uneven portion 23 and the flat portion 33. In addition, the flat part 33 in this embodiment means a part in which unevenness comparable to the roughness of the uneven part 23 is not formed, and even if unevenness having fine roughness like the second uneven part 50 is formed. good.

More specifically, as shown in FIG. 12, the second uneven portion 50 is formed on the surface of the flat portion 33 and the surface of the uneven portion 23 of the n-type window layer 19.
The flat portion 33 includes a first flat portion 51 within the space 30 covered with the cathode electrode layer 11 and a second flat portion 52 outside the cathode electrode layer 11 . The second uneven portion 50 is formed on both the first flat portion 51 and the second flat portion 52.

In the uneven portion 23, a second uneven portion 50 is formed on the outer surface of each convex portion 53 of the uneven portion 23 (or may be referred to as the inner surface of each concave portion). That is, a relatively rough uneven portion 23 is formed over the entire upper surface 29 of the n-type window layer 19, and a second uneven portion 50 which is even finer is formed over the entire surface of each convex portion 53 of the uneven portion 23. has been done.
The second uneven portion 50 has a smaller uneven structure than the uneven portion 23. For example, the arithmetic mean roughness Ra (second roughness Ra) of the second uneven portion 50 is smaller than the arithmetic mean roughness Ra (first roughness Ra) of the uneven portion 23. For example, the second roughness Ra may be 0.01 μm to 0.1 μm, and the first roughness Ra may be 0.1 μm to 0.5 μm.

Further, although the second uneven portion 50 is formed on both the uneven portion 23 and the flat portion 33 of the n-type window layer 19 in FIG. 12, it may be formed only on one of the uneven portion 23 and the flat portion 33. good.
FIG. 13A is a diagram showing steps related to forming the uneven structure shown in FIG. 12. FIG. 13B is a diagram showing the next step after FIG. 13A.

To form the second uneven portion 50, first, as shown in FIG. 5F, the uneven portion 23 is formed on the surface of the n-type window layer 19 by, for example, frost treatment (wet etching).
Next, after the cathode electrode layer 11 is formed as shown in FIG. 6B, the n-type contact layer 20 exposed from the cathode electrode layer 11 is selectively removed using a dilute nitric acid solution, as shown in FIG. 6C. Ru. Thereby, a space 30 is formed below the cathode electrode layer 11. The state after the space 30 is formed is the state shown in FIG. 13A. At this time, an oxide film (not shown) may be formed on the surface of the n-type window layer 19 due to the oxidizing action of the dilute nitric acid solution used as the etching solution.

Next, as shown in FIG. 13B, wet etching is performed using an etching solution different from the frosting (first frosting) shown in FIG. Two uneven portions 50 are formed (second frosting).
The etching solution used is, for example, diluted hydrochloric acid. By using diluted hydrochloric acid as an etching solution, even if the surface of the n-type window layer 19 is covered with an oxide film, the oxide film can be dissolved with diluted hydrochloric acid and the second uneven portion 50 can be formed well. . Furthermore, since the diluted hydrochloric acid also enters the space 30, the n-type contact layer 20 is further side-etched. As a result, the end portion 27 of the n-type contact layer 20 may be further retreated.

The diluted hydrochloric acid may have a volume ratio of water to 1 part hydrochloric acid of 0.5 to 5 (for example, HCl:H ₂ O=1:3). Further, the etching time may be, for example, 10 seconds to 100 seconds, and the temperature may be, for example, 30° C. to 40° C.
As described above, the second uneven portion 50 is formed on the surface of each convex portion 53 of the uneven portion 23. Thereby, as shown by the arrow in FIG. 14A, total reflection of light on the surface of each convex portion 53 can be suppressed, and light can be efficiently extracted from the upper surface 29 of the n-type window layer 19. On the other hand, if the second uneven portion 50 is not formed, total reflection may occur on the surface of each convex portion 53, as shown by the arrow in FIG. 14B, and the structure in which the second uneven portion 50 is formed In comparison, the light extraction efficiency may be lower.

FIG. 15 is a diagram showing the Iv increase rate of the semiconductor light emitting device 1. FIG. 16 is a diagram showing the relationship between frost time and Iv increase rate.
Next, with reference to FIGS. 15 and 16, the effects of double frosting will be described based on experimental data. In FIGS. 15 and 16, "no frost" indicates the state before frosting the top surface of the n-type window layer 19 (for example, the state shown in FIG. 5E), and "after n-GaAs removal" indicates the 13A is shown after side etching of the mold contact layer 20 and before performing the second frost treatment (for example, the state in FIG. 13A).

The processing conditions for the first frost treatment were: Chemical solution: "Pure Etch150" manufactured by Hayashi Pure Chemical Industries, Ltd., Processing temperature: 40±2°C, Processing time: 50, 60, 70, 80 seconds (no rocking). It is. On the other hand, the treatment conditions for the second frost treatment are: chemical solution: diluted hydrochloric acid (hydrochloric acid: water = 1:3), treatment temperature: 32±2° C., and treatment time: 50 seconds (no shaking).
As a result of the experiment, as shown in Fig. 15, if double frost treatment is performed in which both the first frost treatment and the second frost treatment are performed, the rate of increase in luminous intensity Iv is approximately 160% compared to the case without frost treatment. I was able to raise it to. Furthermore, by forming the second uneven portion 50 also in the peripheral portion 34 of the cathode electrode layer 11, it was possible to increase the Iv increase rate to about 180%.

Furthermore, as shown in FIG. 16, up to the step of removing n-GaAs (n-type contact layer 20), the longer the frosting time, the higher the Iv increase rate. On the other hand, it was found that when the second frost treatment was performed, the Iv increase rate eventually became the same regardless of the frost time.
<About Ni split deposition>
FIG. 17A is a diagram showing the first structure of the cathode electrode layer 11. FIG. 17B is a diagram showing the second structure of the cathode electrode layer 11.

First, in the embodiment described above, as shown in FIG. 17A, the AuGeNi layer 31 of the cathode electrode layer 11 is formed by simultaneously evaporating Au, Ge, and Ni and adhering and depositing them on the n-type contact layer 20. There is. On the other hand, in this embodiment, the AuGeNi layer 31 of the cathode electrode layer 11 is formed by simultaneously evaporating Au and Ge and first adhering and depositing the AuGe layer 54 on the n-type contact layer 20. The Ni layer 55 is attached and deposited on the AuGe layer 54 by evaporation. That is, AuGe and Ni are separately deposited. Note that both the AuGe layer 54 and the Ni layer 55 may contain a small amount of impurity as long as the following effects can be achieved.

As described above, in the semiconductor light emitting device 1 including the cathode electrode layer 11 formed by partial vapor deposition of Ni, it is possible to suppress the increase in forward voltage (VF) compared to the case where AuGeNi is simultaneously vapor deposited. can.
As described above, in this semiconductor light emitting device 1, compared to the case where the entire n-type contact layer 20 is in contact with the cathode electrode layer 11, the contact area with the cathode electrode layer 11 is reduced, so that the forward voltage (VF ) is a concern. As shown in FIG. 7, by forming the space 30 with a dilute nitric acid solution, it is possible to suppress the increase in forward voltage (VF), but by employing the split deposition of Ni according to this embodiment, , the increase in forward voltage (VF) can be further suppressed.

Note that in FIG. 17B, the state of the cathode electrode layer 11 immediately after vapor deposition of the Ni layer 55 clearly shows the boundary between the AuGe layer 54 and the Ni layer 55, but the state of the cathode electrode layer 11 of the completed semiconductor light emitting device 1 In layer 11, there may not be a clear boundary between AuGe layer 54 and Ni layer 55. Therefore, the structure of the cathode electrode layer 11 may be referred to as AuGe/Ni for convenience.

Next, the rate of increase in the forward voltage (VF) of the semiconductor light emitting device 1 depends on the thickness of the Ni layer 55, the thickness of the AuGe layer 54, and the content ratio of Ni to the entire cathode electrode layer 11 (AuGe/Ni). I verified how it changes.
FIG. 18 is a diagram showing the relationship between the thickness of the Ni layer 55 and the VF increase rate. FIG. 19 is a diagram showing the relationship between the thickness 54 of the AuGe layer 54 and the VF increase rate. FIG. 20 is a diagram showing the relationship between the content ratio of Ni to AuGe/Ni and the VF increase rate.

More specifically, FIG. 18 shows an experiment in which the deposition thickness of the AuGe layer 54 was fixed at 1600 Å, and the deposition thicknesses of the Ni layer 55 were assigned to 100 Å, 250 Å, 400 Å, 600 Å (twice), and 800 Å, respectively. This is the result of doing this. FIG. 19 shows the results of an experiment in which the deposition thickness of the Ni layer 55 was fixed at 600 Å, and the deposition thicknesses of the AuGe layer 54 were assigned to 100 Å, 500 Å, 1000 Å, 1600 Å, and 2600 Å, respectively. FIG. 20 shows the results of calculating the relationship between the content ratio of Ni to AuGe/Ni and the VF increase rate based on the results obtained from FIGS. 18 and 19.

From the results shown in FIGS. 18 to 20, it was found that when the content ratio (weight ratio) of Ni to AuGe/Ni is 20 wt% or more, the VF increase rate can be stabilized at 1% or less. On the other hand, it was found that the lower the Ni content ratio, the higher the VF increase rate.
Next, we verified what kind of difference could be observed in the cross-sectional structure of the cathode electrode layer 11 depending on the Ni content ratio. More specifically, the cathode electrode layer 11 was deposited with the thickness and content shown in Table 1 below.

FIG. 21 is a schematic diagram of a TEM image of the cathode electrode layer 11 (Ni content: 43.5%). FIG. 22 is a schematic diagram of a TEM image of the cathode electrode layer 11 (Ni content: 19.4%). FIG. 23 is a schematic diagram of a TEM image of the cathode electrode layer 11 (Ni content: 3.9%). 21 and 22 also show a Ni distribution image 56 obtained by TEM-EDX elemental analysis of the cathode electrode layer 11.

First, by comparing the side etching amounts W ₄ , W ₅ , and W ₆ in FIGS. 21, 22, and 24, it was found that the higher the Ni content ratio, the smaller the side etching amount. In other words, it is considered that the higher the Ni content ratio, the more suppressed is the decrease in the contact area between cathode electrode layer 11 and n-type contact layer 20, and the more suppressed is the increase in forward voltage (VF). Further, as shown in FIG. 21, it was observed that when the Ni content ratio was high, a eutectic portion 57 with Ni was formed in the n-type contact layer 20 (GaAs layer).

Further, when TEM-EDX elemental analysis was performed, as shown in FIG. 21, when the Ni content ratio is high, Ni is present in the contact portion (near the boundary) of the AuGe/Ni layer 31 with the n-type contact layer 20. A distribution image 56 was observed, and it was observed that the distribution of AuGe was uniform. On the other hand, in FIG. 22 where the Ni content ratio is 19.4%, a Ni distribution image 56 was observed, but compared to FIG. The distribution intensity was also small. Further, in the case of FIG. 23, no distribution image of Ni could be observed.

Next, we verified what kind of difference could be observed in the composition in the depth direction of the cathode electrode layer 11 depending on the Ni content ratio.
FIG. 24 is a diagram showing the element distribution obtained by AES analysis from the surface of the cathode electrode layer 11 (Ni content: 43.5%) toward the depth direction. FIG. 25 is a diagram showing the element distribution obtained by AES analysis from the surface of the cathode electrode layer 11 (Ni content: 19.4%) toward the depth direction. FIG. 26 is a diagram showing the element distribution obtained by AES analysis from the surface of the cathode electrode layer 11 (Ni content: 3.9%) toward the depth direction.

First, as shown in FIG. 24 (especially with reference to the part surrounded by the broken line), if the Ni content ratio is high, Ni and Ge are diffused into the n-type contact layer 20 (GaAs layer). I understand. On the other hand, as shown in FIGS. 25 and 26 (especially with reference to the part surrounded by the broken line), when the Ni content ratio is not high, Ni and Almost no Ge diffusion was observed. That is, the higher the Ni content ratio, the larger the Ni peak, and more Ni and Ge diffusion was observed up to the n-type contact layer 20 (GaAs layer).

Generally, when forming an ohmic contact with GaAs or AlGaAs, the reaction at the contact interface is difficult to proceed, so the reaction can be accelerated by introducing Ni. However, if Ni reacts too much, the contact surface becomes rough and easily peels off, so in order to control Ni, Ni is vapor-deposited on AuGe while separating it from the interface. However, if the amount of Ni is too small, eutectic formation with the GaAs layer or AlGaAs layer will be insufficient, so an optimal amount of Ni is required to obtain a uniform eutectic portion.

From the above TEM-EDX elemental analysis results, it can be said that a Ni content of 43.5% is a good condition for uniform AuGe precipitation. It is considered that by depositing an appropriate amount of Ni in this manner, the reaction at the etaxial layer/metal interface was promoted, and Au, Ge, and Ni were diffused into the GaAs layer.
Next, it was examined how the VF increase rate of the semiconductor light emitting device 1 changes from lot to lot. FIG. 27 is a diagram showing the VF increase rate of the semiconductor light emitting device 1 by lot.

First, in the AuGeNi co-evaporation lot (number of samples n=432), AuGeNi/Au=2000 Å/17000 Å was adopted as the evaporation recipe for the cathode electrode layer 11. On the other hand, in the Ni split evaporation lot (number of samples n=49), the evaporation recipe for the cathode electrode layer 11 was AuGe/Ni/Au=500 Å/600 Å/18000 Å.
As calculated from the results in FIG. 27, in the AuGeNi co-deposition lot, the average VF increase rate was 101.3%, the maximum was 107.3%, and the minimum was 99.9%. On the other hand, in the Ni split evaporation lot, the average VF increase rate was 100.3%, the maximum was 100.8%, and the minimum was 100.1%. In other words, in the lots that adopted the Ni co-evaporation recipe, the VF increase rate could be stabilized at 1% or less.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other forms.
For example, as shown in FIG. 28, the cathode electrode layer 11 may integrally include a substantially circular pad electrode portion 45 and a branch electrode portion 46 extending radially around the pad electrode portion 45. good. More specifically, in plan view, the pad electrode section 45 is arranged approximately at the center of the substrate 2, and the plurality of branch electrode sections 46 extend from the pad electrode section 45 to four sides and four corners of the substrate 2. It extends in eight directions toward the center. In FIG. 28, the branch-like electrode portions 46 (first portions 47) extending toward the four corners of the substrate 2 are longer than the branch-like electrode portions 46 (second portions 48) extending toward the four sides of the substrate 2. ing.

Further, in the second embodiment, the light-transmitting conductive layer 6 was interposed between the insulating layer 42 and the metal layer 5, but the light-transmitting conductive layer 6 may be omitted. In this case, a metal layer may be provided as the contact portion 44.
Further, in the embodiments described above, when manufacturing the semiconductor light emitting devices 1 and 41, a step of bonding the growth substrate 35 and the substrate 2 was performed, but this bonding step is not essential. For example, a step may be performed in which the metal layer 5, the transparent conductive layer 6, the insulating layer 42, and the compound semiconductor layer 7 are laminated in this order on the substrate 2.

In addition, various design changes can be made within the scope of the claims.

1 Semiconductor light emitting device 2 Substrate 5 Metal layer 6 Transparent conductive layer 7 Compound semiconductor layer 10 Anode electrode layer 11 Cathode electrode layer 12 Light emitting layer 13 P type semiconductor layer 14 N type semiconductor layer 19 N side window layer 20 N type contact layer 23 Uneven portion 24 Pad electrode portion 25 Branch electrode portion 26 Periphery (of the cathode electrode layer) 27 End portion (of the n-type contact layer) 28 Lower surface (of the cathode electrode layer) 29 Upper surface (of the n-type window layer) 30 Space 33 Flatness Part 34 Peripheral part (of the cathode electrode layer) 35 Growth substrate 37 First metal layer 38 Second metal layer 41 Semiconductor light emitting device 42 Insulating layer 43 Contact hole 44 Contact part 45 Pad electrode part 46 Branch-shaped electrode part 50 Second uneven part 53 Convex portion 54 AuGe layer 55 Ni layer

Claims (16)

A substrate and
a metal layer on the substrate;
A light emitting layer formed on the metal layer, a first conductivity type layer disposed on the substrate side with respect to the light emitting layer, and a second conductivity type layer disposed on the opposite side of the substrate with respect to the light emitting layer. a semiconductor layer including a layer;
a first electrode formed on the substrate on the opposite side of the metal layer in the thickness direction of the substrate;
a second electrode formed on the second conductivity type layer,
The second conductivity type layer is formed at a connection portion with the second electrode, and includes a first layer having an end portion in an inner region of the second electrode inside the periphery of the second electrode; a second layer disposed on the substrate side with respect to the first layer;
A space is formed between the end of the first layer and the peripheral edge of the second electrode,
The surface of the second layer is located at a portion facing the second electrode across the space and at a peripheral portion of the second electrode in an outer region of the second electrode outside the peripheral edge of the second electrode. a flat portion formed, and an uneven portion formed outside the peripheral portion in the outer region of the second electrode and having a first roughness,
The surface of the second layer further includes a second uneven portion formed on the surface of each convex portion of the flat portion and the uneven portion, and having a second roughness smaller than the first roughness,
The second electrode includes a pad electrode portion to which a bonding member is connected, and a branch-like electrode portion extending branch-like from the pad electrode portion,
The space is formed below the branch electrode part,
The width W2 of the space from the periphery of the branch electrode part is less than 1/2 of the width W3 of the branch electrode part,
A semiconductor light emitting device, wherein the width W3 of the branch electrode portion is 6 μm to 8 μm, and the width W2 of the space is 1 μm to 2 μm. 2. The semiconductor light emitting device according to claim 1, wherein the second electrode includes a laminated structure in which an AuGe layer and a Ni layer are formed in this order from the substrate side. The arithmetic mean roughness Ra of the uneven portion is 0.1 μm to 0.5 μm, and the arithmetic mean roughness Ra of the second uneven portion is 0.01 μm to 0.1 μm, according to claim 1 or 2. Semiconductor light emitting device. The semiconductor light emitting device according to any one of claims 1 to 3, wherein a width _W1 of the peripheral portion of the second electrode from the peripheral edge is 1 μm to 3 μm. 5. The semiconductor light emitting device according to claim 1, wherein the first layer of the second conductivity type layer includes an n-type GaAs contact layer. The semiconductor light emitting device according to claim 1, further comprising a transparent conductive layer formed between the metal layer and the semiconductor layer. 7. The semiconductor light emitting device according to claim 6, wherein the light-transmitting conductive layer contains ITO (indium tin oxide), ZnO (zinc oxide), or IZO (indium zinc oxide). further comprising an insulating layer formed between the metal layer and the semiconductor layer and selectively having a contact hole;
6. The semiconductor light emitting device according to claim 1, wherein the metal layer is electrically connected to the first conductivity type layer via the contact hole. The semiconductor light emitting device according to claim 8, wherein the insulating layer contains _SiO2 , SiN, or _MgF2 . The semiconductor light emitting device according to claim 1, wherein the metal layer contains Au. The semiconductor light emitting device according to claim 1, wherein the substrate includes a Si substrate. a substrate, a metal layer on the substrate, a light emitting layer formed on the metal layer, a first conductivity type layer disposed on the substrate side with respect to the light emitting layer, and a first conductivity type layer disposed on the substrate side with respect to the light emitting layer; a semiconductor layer including a second conductivity type layer disposed on the opposite side of the semiconductor layer, the second conductivity type layer forming a surface of the semiconductor layer, and the substrate with respect to the first layer. forming a semiconductor structure including a second layer disposed on the side;
selectively removing the first layer to expose the surface of the second layer;
forming an uneven portion on the surface of the second layer by frosting the exposed surface of the second layer;
After forming the uneven portion, forming a second electrode on the first layer so as to fit within an inner region of the first layer;
Forming a space between an end of the first layer and a periphery of the second electrode by side-etching the first layer downward of the second electrode using a dilute nitric acid solution. process and
forming a first electrode on the substrate opposite to the metal layer in the thickness direction of the substrate. 13. The semiconductor light emitting device according to claim 12, further comprising the step of frosting a portion of the second layer facing the second electrode across the space and the uneven portion using diluted hydrochloric acid after forming the space. Method of manufacturing the device. the first layer of the second conductivity type layer includes an n-type GaAs contact layer;
The step of forming the second electrode includes a first step of evaporating a first vapor deposition material containing Au and Ge and depositing it on the n-type contact layer to form a layer containing Au and Ge, and the first step. 14. The semiconductor light emitting device according to claim 12, further comprising a second step of evaporating a second vapor deposition material containing Ni and depositing it on the layer containing Au and Ge to form a layer containing Ni. manufacturing method. 15. The method for manufacturing a semiconductor light emitting device according to claim 14, wherein the weight ratio of the Ni to the total amount of Au, Ge, and Ni is 20 wt% or more. The step of forming the semiconductor structure includes:
forming the second conductivity type layer, the light emitting layer, the first conductivity type layer, and the first metal layer in this order on the connection substrate;
forming a second metal layer on the substrate;
bonding the connection substrate and the substrate as the metal layer by bonding the first metal layer and the second metal layer to each other;
16. The method for manufacturing a semiconductor light emitting device according to claim 12, further comprising the step of removing the connection substrate after the bonding.

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