JP2009510730A - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Abstract

An embodiment of the present invention includes an upper cladding layer, a lower cladding layer, an active layer between the upper and lower cladding layers, an upper ohmic contact layer that forms a conductive line path to the upper cladding layer, and a conductive line path to the lower cladding layer A semiconductor light emitting device is provided comprising a lower ohmic contact layer that forms a substrate. The lower ohmic contact layer has a shape that is substantially different from the shape of the upper ohmic contact layer so that it is substantially below the upper ohmic contact layer when a voltage is applied to the upper and lower cladding layers. The carrier flow is changed from a part of the active layer.

Description

  The present invention relates to the design of semiconductor light emitting devices. More particularly, the present invention relates to a novel device structure that promotes more efficient light emission.

(Related technology)
Solid-state lighting is expected to become a trend in future lighting. High-intensity light-emitting diodes (HB-LEDs) are beginning to be used in an increasing number of applications, particularly as light sources for display devices and light bulbs that replace conventional lighting. High luminous efficiency, such as conventional incandescent or fluorescent lamps, remains a challenge for LED designers.

  An LED typically generates light from an active region located between a positively doped cladding layer (p-type cladding layer) and a negatively doped cladding layer (n-type cladding layer). When the LED is forward biased, the carriers including the holes in the p-type cladding layer and the electrons in the n-type cladding layer recombine in the active region. In the case of direct transition materials, this recombination process releases energy in the form of photons or light, the wavelength of which corresponds to the band gap energy of the material in the active region.

  In order to improve the luminous efficiency, it is very important that the emitted light is rapidly emitted from the device so that the light is not absorbed by the inert material in the device. Unlike laser devices where the emitted light is guided and propagated in a common specific direction, the light emitted from the LED propagates in all directions. As a result, some of the light is reflected from certain inner surfaces and is absorbed or blocked by the impermeable material in the device.

  The problem of light blocking is particularly noticeable in LEDs having a vertical electrode structure, that is, LEDs in which the entire device is located between the upper and lower electrodes. The electrode is typically made of metal and does not transmit visible light. If there is significant overlap between the upper and lower electrodes, the electrodes can block a significant amount of light emitted vertically. In the active region coinciding with the overlapping region, carriers are further recombined because typically this region is part of the low resistance path. Such concentration of carriers in undesirable locations further exacerbates the problem of blocking vertical light.

  Accordingly, there is a need for LED structures and methods for processing such structures that alleviate the vertical light blocking problem.

(Overview)
An embodiment of the present invention includes an upper cladding layer, a lower cladding layer, an active layer between the upper and lower cladding layers, an upper ohmic contact layer that forms a conductive line path to the upper cladding layer, and a conductive line path to the lower cladding layer A semiconductor light emitting device is provided comprising a lower ohmic contact layer that forms a substrate. The lower ohmic contact layer has a shape that is substantially different from that of the upper ohmic contact layer, so that it is substantially below the upper ohmic contact layer when a voltage is applied to the upper and lower cladding layers. The carrier flow is changed from a part of the active layer.

  In one variation of this embodiment, the shape of the lower ohmic contact layer is substantially complementary to the shape of the upper ohmic contact layer, so that light emitted upward is substantially transmitted by the upper ohmic contact layer. The carrier flow is concentrated on a part of the active region that is not blocked.

  In yet another variation, a portion of the lower ohmic contact layer is substantially absent in the region below the upper ohmic contact layer. The region without the lower ohmic contact layer includes a high resistance material or a material capable of forming a high resistance contact with the Schottky or lower cladding layer.

In yet another variation, the material included in the region where the lower ohmic contact layer is not present includes one of S _i O ₂ , Au, Al, and Ag.

  In yet another embodiment, the material contained in the region where there is no lower ohmic contact layer is reflective to the wavelength of light emitted by the active layer.

  In one variation of this embodiment, the device further includes a layer of high resistance material located between the lower cladding layer and the lower ohmic contact layer. The high resistance material is substantially confined to the region below the upper ohmic contact layer, thereby reducing carrier recombination that occurs under the upper ohmic contact layer that can block light emitted upward.

  In a variation of this embodiment, the device further comprises a bonding material layer below the lower ohmic contact layer and a low resistance substrate under the bonding material layer, the low resistance substrate comprising Si, and the upper and lower cladding layers being Each includes n-type GaN and p-type GaN. The active layer includes an InGaN / GaN multiple quantum well structure, and the bonding material layer includes Au.

  Yet another embodiment of the present invention includes an upper cladding layer, a lower cladding layer, an active layer between the upper and lower cladding layers, an upper ohmic contact layer that forms a conductive line path to the upper cladding layer, and a conductivity to the lower cladding layer. A semiconductor light emitting device is provided that includes a lower ohmic contact layer that forms a line path. In addition, part of the lower cladding layer, or part of the active layer, or both are substantially absent in the region below the upper ohmic contact layer, thereby allowing the upwardly emitted light to be in upper ohmic contact. Reduces carrier recombination below the upper ohmic contact layer, which causes the layer to block.

  In a modification of the present embodiment, the region where no part of the lower cladding layer or part of the active layer is present contains a high resistance material.

  In one variation of this embodiment, the shape of the lower cladding layer or active layer is substantially complementary to the shape of the upper ohmic contact layer.

  One embodiment of the present invention provides a method for processing a semiconductor light emitting device. The method includes forming a layered semiconductor structure on a substrate, the layered semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The method includes forming a first ohmic contact layer having a conductive path to a first surface of the layered structure, removing a portion of the first ohmic contact layer, the first ohmic Forming a bonding material layer on the contact layer; bonding a low resistance substrate on the bonding material layer; removing a growth substrate to expose a second surface of the layered structure; and the layered structure. Forming a second ohmic contact layer having a conductive path to the second surface of the substrate. The second ohmic contact layer is limited to a region substantially corresponding to the region from which a portion of the first ohmic contact layer is removed, whereby vertically emitted light is transmitted to the second ohmic contact layer. The carrier flow is diverted from a portion of the active layer that can be substantially blocked by the.

  In some variations of this embodiment, the shape of the second ohmic contact layer is substantially complementary to the shape of the first ohmic contact layer.

  In one variation of this embodiment, the method uses a high resistance material or a Schottky or material that can form a high resistance contact with the layered structure to remove a portion of the first ohmic contact layer. The method further includes a step of filling.

In yet another variation, the material used to fill the region from which a portion of the first ohmic contact layer is removed includes one of S _i O ₂ , Au, Al, and Ag. .

  In one variation of this embodiment, the first ohmic contact layer includes a material that is reflective to the wavelength of light emitted by the active layer.

  One embodiment of the present invention provides a method for processing a semiconductor light emitting device. The method includes forming a layered semiconductor structure on a growth substrate, the layered semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The method forms a high resistance material region confined to a region on the first surface of the layered structure and forms a first ohmic contact layer having a conductive path to the first surface of the layered structure. A step of covering the high resistance material region with a first ohmic contact layer, a step of forming a bonding material layer on the first ohmic contact layer, a step of bonding a low resistance substrate on the bonding material layer, and a layered structure Removing the growth substrate to expose the second side of the substrate and forming a second ohmic contact layer having a conductive path to the second side of the layered structure. The second ohmic contact layer is confined to a region substantially corresponding to the high resistance material region, whereby one of the active layers in which the emitted light can be substantially blocked by the second ohmic contact layer. Change the career flow from the department.

  In a variation of this embodiment, the shape of the second ohmic contact layer is substantially the same as the shape of the high resistance material region.

  One embodiment of the present invention provides a method for processing a semiconductor light emitting device. The method includes forming a layered semiconductor structure on a growth substrate, the layered semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The method includes removing a portion of the p-type layer, filling a region from which the p-type layer is removed with a high resistance material, and having a conductive path to the first surface of the layered structure. Forming an ohmic contact layer, the first ohmic contact layer covering the high resistance material region, forming a bonding material layer on the first ohmic contact layer, and forming a low resistance substrate on the bonding material layer. Bonding, removing the growth substrate to expose the second side of the layered structure, and forming a second ohmic contact layer having a conductive path to the second side of the layered structure. In addition. The second ohmic contact layer is confined to a region substantially corresponding to the high resistance material region, whereby the vertically emitted light can be substantially blocked by the second ohmic contact layer. To change the career flow from a part of.

  In one variation of this embodiment, the shape of the second ohmic contact layer is substantially complementary to the shape of the high resistance material region.

  In a variation of this embodiment, the high resistance material region penetrates the p-type layer.

  In one variation of this embodiment, the method further includes removing a portion of the active layer and filling a region from which the active layer is removed with a high resistance material.

(Detailed explanation)
The following description is presented to enable any person skilled in the art to make and use the invention and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the scope of the invention. Accordingly, the invention is not limited to the disclosed embodiments, but is to be accorded the widest scope consistent with the claims.

(Blocking light emitted vertically)
In general, the two electrodes of an LED can be arranged on the same side (side electrode) as the substrate or on a different side (vertical electrode) from the substrate. The configuration of the vertical electrode is a suitable design for its easy mounting and excellent reliability. FIG. 1 shows a typical LED structure with vertical electrodes.

  The active layer 106 is “sandwiched” between the upper layer 104 and the lower layer 108. It should be noted that the upper layer 102 or the lower layer 108 may include additional layers such as an n-type or p-type cladding layer, a substrate layer, a buffer layer, and the like. Further, although the cladding layer can include one or more layers, the “cladding layer” used in some literature refers only to the doped layer immediately adjacent to the active layer.

  The upper layer 104 described above is the upper electrode 102 and is a conductive layer or a low-resistance material. Below the lower layer 108 is a lower electrode 110, which is also a conductive layer or a low resistance material. In one embodiment, both the upper electrode 102 and the lower electrode 110 are ohmic contact layers. Note that the ohmic contact layer can form an ohmic contact with an adjacent layer and typically exhibits low resistance. The ohmic contact layer can be based on one or more metals, alloys or compounds such as Pt, Ni, NiO, ITO (Indium Tin Oxide). In yet another embodiment, the upper layer 104 can include a negatively doped layer (n-type doped layer) and the lower layer 108 can include a positively doped layer (p-type doped layer).

  As shown in FIG. 1, when the LED is forward biased above the turn-on voltage threshold, the p-type layer vacancies recombine with the n-type layer electrons in the active layer 106. As a result, the current shown by the dotted line between the electrodes 102 and 110 is generated by the carrier flow. Since current tends to concentrate in places with low resistance, the distribution of this current through the active layer 106 depends on the resistance distribution between the electrodes. Since the low resistance path between the electrodes is directly under the upper electrode 102, the region of the active layer 106 immediately under the upper electrode 102 has the highest current density. Accordingly, the most carrier recombination occurs in this region. This “current crowding” phenomenon is more pronounced when the LED's layered structure is relatively thin, since the horizontal resistance in the layered structure can be much greater than the vertical resistance. As a result of this “current congestion”, most of the light emitted vertically is blocked by the upper electrode 102.

  Note that the lower electrode 110 also blocks downward propagating light. However, it is possible to use a reflective material for the lower electrode 110 so that the lower electrode 110 can reflect most of the light.

(Operation of carrier flow by modifying the resistance distribution)
Embodiments of the present invention reduce vertical light blocking problems by manipulating the carrier flow in the device, and the majority of carrier recombination is the active layer where vertically emitted light is not blocked by the upper electrode. To occur in the region. Such manipulation is accomplished by modifying the resistance distribution that extends to the metal, cladding, and / or active layer.

  One embodiment of the present invention uses a specially shaped electrode to modify the effective resistance distribution that spans the layered structure of the LED. For example, the upper and lower electrodes have substantially complementary shapes, so that the overlapping area between vertical projections on the horizontal projection plane is greatly reduced. Thus, the majority of carrier recombination can occur in the active layer region where the upward propagating light is not blocked by the upper electrode.

FIG. 2 illustrates an LED structure having substantially complementary vertical electrodes, according to one embodiment of the present invention. In this example, the upper electrode 202 has a ring shape, and the lower electrode 210 is an ohmic contact layer having a removed portion, and the removed portion corresponds to the shape of the upper electrode 202. FIG. 5 shows a top view of these electrodes. The removed portion in the ohmic contact layer 210 is then filled with a high resistance material. As used herein, “high resistance material” includes an insulator, a material having a substantially higher resistivity than the metal or its cladding layer, or a material capable of forming a high resistance contact with the metal or cladding layer. Note that you can. In one embodiment, the high resistance material can be an insulator material such as SiO ₂ , SiN, or Al ₂ O ₃ . In yet another embodiment, the high resistance material can be a conductive metal such as Au or Cr that can form a Schottky contact with the cladding layer.

  When the LED is forward biased, carrier recombination occurs in regions in the active layer 206 that correspond to the “inner” and “outer” of the ring shape. As a result, most of the light propagating upward can be freely moved to the upper surface of the layered structure without being blocked by the upper electrode 202.

  Note that the exact and complementary electrode shapes are optional in the present invention to alleviate the light blocking problem. In general, similar results can be achieved with different electrode shapes. As used herein, having a “substantially complementary shape” means having vertical upper and lower electrode regions that do not overlap. In one embodiment, the overlap region is less than 100% of the upper electrode region, preferably less than 50%. In addition, the upper and lower electrodes can have a shape in which the vertical projections do not overlap at all as long as the electrodes can maintain sufficient connection with the wires, or unless the luminous efficiency of the LED is impaired. In one embodiment, the non-overlapping region between the upper and lower electrodes does not exceed five times the upper electrode region.

  In addition to the use of specially shaped electrodes, other modifications, additions, or reduction of materials in the layered LED structure can also change the resistance distribution. In one embodiment, as shown in FIG. 3, a layer of high resistance material 310 is initially disposed between the lower cladding layer and the lower electrode. A portion of the high resistance material 310 is subsequently removed, and its shape is substantially complementary to the shape of the upper electrode 302.

  In one embodiment, after the lower electrode 312, which is a metal layer, is deposited or epitaxially grown, only a portion of this ohmic contact layer is made conductive to the lower layer 308 because of the high resistance material layer 310. Is possible. As a result, the carrier flow through the active layer 306 region in the “shadow” portion, or the vertical projection of the upper electrode, is reduced and the carrier flow through the other regions of the active layer 306 is increased. Therefore, most of the light emitted upward can be propagated to and emitted from the upper surface of the device without being blocked by the upper electrode 302. Note that in this example, the upper electrode 302 has a circular shape, and the high resistance layer 310 has a similar circular shape with a slightly larger area. It should further be noted that the shape of the high resistance layer 310 need not exactly match the shape of the upper electrode 302. Smaller or larger high resistance layers are also possible.

  In yet another embodiment, a portion of the cladding and / or active layer is removed and replaced with a high resistance material to divert carrier flow to the non-blocking region. As shown in FIG. 4, the lower layer 408 and a part of the active layer 406 are removed and replaced with the high resistance material 412. The vertical projection of the high resistance material 412 substantially overlaps the vertical projection of the upper electrode 402. Note that in one embodiment, only a portion of lower layer 408 is removed and replaced with a high resistance material, while active layer 406 remains intact. In yet another embodiment, the high resistance material 412 can penetrate both the lower layer 408 and the active layer 406. However, in yet another embodiment, only a portion of the active layer 406, but not the lower layer 408, is removed and replaced with a high resistance material. Other configurations are possible as long as the replacement of the high resistance material 412 can reduce the carrier flow under the upper electrode 402.

  When a forward bias voltage is applied between the upper electrode 402 and the lower electrode 410, carriers flow around the high resistance material 412 as shown by the dotted line. As a result, the upper electrode 402 cannot block upward propagation light.

  5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. Also note that these shapes can also reflect the shape of the effective low resistance conductive regions on the upper and lower electrodes of a device having buried high resistance layers as illustrated in FIGS. I want to be.

  FIG. 5 shows an upper electrode 502 having a ring shape and a lower electrode 504 having a removed portion. The removed portion of the lower electrode 504 substantially corresponds to the upper electrode 502 and is replaced with a high resistance material. The region defined by the dotted line indicates the upper surface of the upper layer below the upper electrode or the lower layer above the lower electrode.

  FIG. 6 shows an upper electrode 602 having a circular shape and a lower electrode 604 having a removed portion. The removed portion of the lower electrode 604 substantially corresponds to the upper electrode 602 and is replaced with a high resistance material.

  FIG. 7 shows an upper electrode 702 having a star shape and a lower electrode 704 having a removed portion. The removed portion of the lower electrode 704 substantially corresponds to the upper electrode 702 and is replaced with a high resistance material.

  FIG. 8 shows an upper electrode 804 having an irregular shape and a lower electrode 804 having a removed portion. The removed portion of the lower electrode 804 substantially corresponds to the upper electrode 804 and is replaced with a high resistance material.

  Note that substantially complementary electrodes need not have exactly matching shapes. FIG. 9 shows an upper electrode 902 having a triangular shape and a lower electrode 904 having a substantially different shape. The peripheral region of the lower electrode 904 is filled with a high resistance material.

  FIG. 10 shows an upper electrode 1002 having a strip shape and a lower electrode 1004 having a quadrangular shape. Note that the vertical projections of the upper electrode 1002 and the lower electrode 1004 do not overlap at all. A region around the lower electrode 1004 is filled with a high resistance material.

  FIG. 11 shows an upper electrode 1104 having two strip-shaped metal portions and a lower electrode 1104 having a rectangular shape. The vertical projection of the lower electrode 1104 is located between the two strip-shaped vertical projections of the upper electrode 1102. As a result, the upper electrode 1102 does not overlap with the lower electrode 1104. A region around the lower electrode 1104 is filled with a high resistance material.

  FIG. 12 shows an upper electrode 1202 having an elliptical shape and a lower electrode 1204 having a removed portion. The removed portion of the lower electrode 1204 substantially corresponds to the upper electrode 1202 and is replaced with a high resistance material.

(Processing process)
The exemplary processing process described below uses a GaN light emitting device as in the examples. However, the general device structures described herein are applicable to a wide range of semiconductor light emitting devices. In the examples described later, a layered structure based on GaN is processed on a Si substrate. Typically, a buffer layer is present between the GaN based device and the Si substrate to eliminate lattice and thermal mismatch. The compounds generally used for the buffer layer are In _x Ga _y Al _1-xy N (0 ≦ x ≦ 1; 0 ≦ y ≦ 1), In _x Ga _y Al _1-xy P (0 ≦ x ≦ 1; 0 ≦ y ≦ 1), and In _x Ga _y Al _1-xy As (0 ≦ x ≦ l; 0 ≦ y ≦ l). Furthermore, the device structure described herein can be applied to a wide range of semiconductor layers or metal substrates such as Si, GaAs, GaP, Cu, and Cr.

FIG. 13 shows a process for processing an LED with a complementary electrode where the top electrode is ring-shaped. Based on the well-known InGaAlN device processing process, in step A, a GaN light emitting layered structure is first processed on a grown Si substrate 1302. A buffer layer 1304 is typically grown on the substrate 1302. Thereafter, an n-type GaN layer 1306 is grown on the buffer layer 1304. In one embodiment, the InGaN / GaN multiple quantum well active layer 1307 and the p-type GaN layer 1308 are formed on the n-type GaN layer 1306. These layers can be processed using chemical vapor deposition (CVD). In yet another embodiment, the layered structure is placed in a N ₂ environment at 760 ° C. for about 20 minutes for annealing purposes.

  In Step B, an ohmic contact layer 1310 is formed on the p-type GaN layer. In one embodiment, this processing step uses physical vapor deposition methods such as electron beam vapor deposition, filament vapor deposition, or sputter vapor deposition. Also, the ohmic contact layer 1310 can be a reflective material. Preferably, the ohmic contact layer 1310 has a reflectivity of 30% or more. In one embodiment, the ohmic contact layer 1310 includes Pt.

  In step C of the fabrication process, a portion of the ohmic contact layer is removed using photolithography to produce a patterned ohmic contact layer 1311. The removed portion corresponds to a ring shape. Note that the ohmic contact layer 1311 becomes the lower electrode after the structure is inverted upside down in the next step.

  In Step D, the bonding metal material 1312 is deposited on the ohmic contact layer 134. The bonding metal material 1312 is a conductive material, but can form a high resistance contact with the p-type layer. In one embodiment, Au can form a Schottky barrier with p-type GaN, so the bonding metal material 1312 includes Au.

  In Step E, the entire layered structure 1314 obtained in Step D is inverted upside down and bonded to the second Si substrate 1318 having low resistance. Further, the bonding surface of the substrate 1318 is covered with the same bonding metal material 1316 as the bonding material 1312. The other side of the substrate 1318 is a layer of protective material 1320 that protects the substrate 1318 from subsequent etching steps. In one embodiment, the protective layer 1320 also includes Au. Note that since the protective layer 1320 is generally a conductive material, a conductive path can be formed from the p-type GaN layer to the bonding layer 1316, the substrate 1318, and the protective layer 1320.

  In step F, a layered structure 1322 including two substrates is formed after bonding. In Step G, the grown Si substrate 1302 is removed using a wet etch based on, for example, KOH or HNA. Note that the generated structure 1324 includes the substrate 1318 because the protective layer 1320 protects the substrate 1318 from the etchant.

  In step H, another ohmic contact layer 1326 is deposited on the top surface of the substrate 1324. Thereafter, a portion of the ohmic contact layer 1326 is removed in step I using photolithography to produce a shaped upper ohmic contact layer 1328. The ohmic contact layer 1328 has a ring shape and substantially corresponds to the removed portion of the lower ohmic contact layer 1311. In general, the processing process shown in FIG. 13 can produce any substantially complementary electrode shape as shown in FIGS. For example, the same process can be used to produce a star-shaped upper electrode and a corresponding lower electrode as shown in FIG. Further, the region of the part where the lower electrode is removed can be made larger than the region of the upper electrode. In one embodiment, the area of the removed portion of the lower electrode is 1.5 times the area of the upper electrode.

In yet another embodiment, the high resistance material can be filled into the area where the lower ohmic contact layer has been removed. For example, referring to FIG. 13, after part of the ohmic contact layer 1311 is removed in step C, the SiO ₂ layer can fill the cavity from which the ohmic contact layer 1311 has been removed. Thereafter, the SiO ₂ layer can be patterned and etched to expose the ohmic contact layer 1311 that has not been removed. Thereafter, in Step D, a junction ohmic contact layer 1312 is formed on the ohmic contact layer 1311 and the SiO ₂ layer. In addition to SiO ₂ , other conductive metals such as Au, Al, and Ag can also be used to fill the cavity as long as the material can form a Schottky contact with the p-type GaN layer 1308. .

  FIG. 14 illustrates a process for processing an LED having a buried high resistance layer between an electrode and a p-type cladding layer and the upper electrode in a ring shape, according to one embodiment. In step A, the GaN device is processed on the grown Si substrate 1402. Typically, an InGaAlN buffer layer 1404 is grown on the substrate 1402. Thereafter, an n-type GaN layer 1406, which may be Si-doped GaN in one embodiment, is grown on the buffer layer 1404. Next, an InGaN / GaN multiple quantum well active layer 1407 and a p-type GaN layer 1408 are grown on the n-type GaN layer 1406.

In step B, a layer of a high resistance material such as SiO ₂ is deposited using, for example, plasma enhanced chemical vapor deposition (PECVD). Thereafter, the SiO ₂ layer is patterned and etched to form a ring-shaped insulator layer 1409. Insulator layer 1409 is then used to prevent the p-side electrode from forming a conductive path with p-type GaN layer 1408 in certain areas.

  In Step C, a reflective ohmic contact layer 1411 is deposited on the insulator layer 1409 and the p-type GaN layer 1408. The region of the ohmic contact layer 1411 that is in ohmic contact with the p-type GaN layer 1408 has a shape that is substantially complementary to the shape of the insulator 1409.

  In step D, a bonded ohmic contact layer 1412 is further deposited on the ohmic contact layer 1411. Thereafter, the generated layered structure 1414 is inverted upside down and bonded to the low resistance Si wafer 1418. As seen in step E, the bonding surface of the Si wafer 1418 is covered with a bonding metal layer 1416. The other surface of the Si wafer 1418 is covered with a protective layer 1420. In one embodiment, the joining process occurs under high temperature and pressure. After bonding, in step F, a layered structure 1422 is formed, but will include two substrates.

  In step G, the growth substrate 1402 is removed using wet etching, resulting in a structure 1424. Since the protective layer 1420 protects the wafer 1418 from damage by the etchant, the low resistance Si wafer 1418 remains intact.

  In Step H, the InGaAlN buffer layer 1404 is separated by etching to expose the n-type GaN layer 1406. Next, an ohmic contact layer 1426 is deposited on the n-type GaN layer 1406. In Step I, the ohmic contact layer 1426 is etched into the ring-shaped upper electrode 1428 using photolithography.

  FIG. 15 illustrates a process for fabricating an LED having a buried insulator penetrating a p-type cladding layer and an active layer according to one embodiment of the present invention. In this example, the upper electrode has a circular shape, and the shape of the embedded insulator substantially matches the shape of the upper electrode.

  In Step A, a GaN-based light emitting device including a buffer layer 1504, an n-type GaN layer 1506, a multiple quantum well active layer 1507, and a p-type GaN layer 1508 is grown on a growth Si substrate 1502. Next, in step B, the p-type GaN layer 1508 and a part of the active layer 1507 are separated by etching in order to generate the cavity 1509.

Thereafter, in Step C, an insulating material such as SiO ₂ is deposited to fill the cavity 1509. In step D, further patterning and etching are applied to remove excess insulating material.

  In Step E, an ohmic contact layer is formed on the p-type GaN layer 1508 and the insulator 1511. Next, a bonding layer 1513 is formed on the ohmic contact layer 1512. Thereafter, the generated layered structure 1514 is inverted upside down and bonded to the low resistance substrate 1518. On the bonding surface of the low-resistance substrate 1518 is a bonding layer 1516, and in one embodiment, includes the same metal as the bonding layer 1513. Another surface of the low resistance substrate 1518 is a conductive protection layer 1520.

  Thereafter, in step G, the growth substrate 1502 is removed by wet etching, resulting in a structure 1524. The buffer layer 1504 is further removed in step H, exposing the n-type GaN layer 1506. Thereafter, an ohmic contact layer 1526 is formed to form an ohmic contact with the n-type GaN layer 1506.

  In Step I, the ohmic contact layer 1526 is patterned and etched to form a circular upper electrode 1526. Note that the shape of the insulator 1511 substantially matches the shape of the upper electrode 1526.

  The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. It is not intended to be exhaustive or limited to the invention in the form disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in this art. Also, the above disclosure is not intended to limit the present invention. The scope of the invention is defined by the appended claims.

FIG. 1 shows an LED structure having vertical electrodes that block vertically emitted light. FIG. 2 illustrates an LED structure having substantially complementary verticals in accordance with one embodiment of the present invention. FIG. 3 illustrates an LED structure having a high resistance layer positioned between a lower cladding layer and a lower ohmic contact layer, in accordance with one embodiment of the present invention. FIG. 4 illustrates an LED structure in which a portion of the lower cladding layer and the active layer are removed and replaced with a high resistance layer according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. 5-12 illustrate examples of complementary upper and lower electrodes according to one embodiment of the present invention. FIG. 13 illustrates a process for fabricating an LED having complementary electrodes, according to one embodiment of the present invention. FIG. 14 illustrates a process for processing an LED having a buried high resistance layer between an electrode and a p-type cladding layer, in accordance with one embodiment of the present invention. FIG. 15 illustrates a process for processing an LED having a p-type cladding layer and a buried high resistance layer penetrating the active layer, in accordance with one embodiment of the present invention.

Claims (21)

A semiconductor light emitting device,
An upper cladding layer;
A lower cladding layer;
An active layer between the upper and lower cladding layers;
An upper ohmic contact layer that forms a conductive path to the upper cladding layer;
A lower ohmic contact layer that forms a conductive path to the lower cladding layer, the lower ohmic contact layer having a shape substantially different from the shape of the upper ohmic contact layer, thereby A semiconductor light emitting device that, when a voltage is applied to an ohmic contact layer, diverts carrier flow from a portion of the active layer that is substantially below the upper ohmic contact layer.   The shape of the lower ohmic contact layer is substantially complementary to the shape of the upper ohmic contact layer, thereby concentrating the carrier flow on a portion of the active layer and radiating upward. The semiconductor layer light emitting device of claim 1, wherein light is not substantially blocked by the upper ohmic contact layer. A portion of the lower ohmic contact layer is not substantially present in a region below the upper ohmic contact layer;
3. The semiconductor light emitting device of claim 2, wherein the region without the lower ohmic contact layer includes either a high resistance material or a material capable of forming a high resistance contact with a Schottky or the lower cladding layer. . The semiconductor light emitting device according to claim 3, wherein the material included in the region where the lower ohmic contact layer is not present is one of SiO ₂ , Au, Al, and Ag.   The semiconductor light emitting device according to claim 4, wherein the material contained in the region where the lower ohmic contact layer is not present is reflective to the wavelength of light emitted by the active layer. A high resistance material layer located between the lower cladding layer and the lower ohmic contact layer;
The high resistance material layer is substantially confined to the region below the upper ohmic contact layer, thereby reducing carrier recombination that occurs under the upper ohmic contact layer that may block light emitted upward. The semiconductor light-emitting device according to claim 1. A bonding material layer under the lower ohmic contact layer, and a low-resistance substrate under the bonding material layer;
The low resistance substrate includes Si,
The upper and lower cladding layers each include n-type GaN and p-type GaN,
The active layer includes an InGaN / GaN multiple quantum well structure,
The semiconductor light emitting device according to claim 1, wherein the bonding material layer includes Au. A semiconductor light emitting device,
An upper cladding layer;
A lower cladding layer;
An active layer between the upper and lower cladding layers;
An upper ohmic contact layer that forms a conductive path to the upper cladding layer;
A lower ohmic contact layer that forms a conductive path to the lower cladding layer, wherein a portion of the lower cladding layer, or a portion of the active layer, or both are substantially below the upper ohmic contact layer A semiconductor light emitting device that reduces recombination of carriers under the upper ohmic contact layer that is not present in the region, thereby blocking light emitted upward by the upper ohmic contact layer.   9. The semiconductor light emitting device according to claim 8, wherein a region in which a part of the lower cladding layer or a part of the active layer does not exist contains a high resistance material.   9. The semiconductor light emitting device of claim 8, wherein the shape of the lower cladding layer or the active layer is substantially complementary to the shape of the upper ohmic contact layer. A method of processing a semiconductor light emitting device, the method comprising:
Forming a layered semiconductor structure on a growth substrate, the layered semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;
Forming a first ohmic contact layer having a conductive path to the first surface of the layered structure;
Removing a portion of the first ohmic contact layer;
Forming a bonding material layer on the first ohmic contact layer;
Bonding a low resistance substrate on the bonding material layer;
Removing the growth substrate to expose the second side of the layered structure;
Forming a second ohmic contact layer having a conductive path to the second surface of the layered structure, wherein the second ohmic contact layer is a portion of the first ohmic contact layer. Carriers from a portion in the active layer that is confined to a region substantially corresponding to the region to be removed, whereby vertically emitted light can be substantially blocked by the second ohmic contact layer To change the flow of   The method of claim 11, wherein a shape of the second ohmic contact layer is substantially complementary to a shape of the first ohmic contact layer.   The region from which a portion of the first ohmic contact layer is removed further comprises filling with either a high resistance material or a material capable of forming a high resistance contact with the layered structure. Item 12. The method according to Item 11. The method of claim 13, wherein the material used to fill a region from which a portion of the first ohmic contact layer is removed comprises one of SiO ₂ , Au, Al, and Ag.   The method of claim 11, wherein the first ohmic contact layer comprises a material that is reflective to the wavelength of light emitted by the active layer. A method for processing a semiconductor light emitting device, comprising:
Forming a layered semiconductor structure on a growth substrate, the layered semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;
Forming a high resistance material region confined to a location on the first surface of the layered structure;
Forming a first ohmic contact layer having a conductive path to the first surface of the layered structure, the first ohmic contact layer covering the high resistance material;
Forming a bonding material layer on the first ohmic contact layer;
Bonding a low resistance substrate on the bonding material layer;
Removing the growth substrate to expose the second side of the layered structure;
Forming a second ohmic contact layer having a conductive path to the second surface of the layered structure;
The second ohmic contact layer is confined to a region substantially corresponding to the high resistance material region, whereby emitted light is substantially blocked by the second ohmic contact layer. A method of diverting carrier flow from a portion of the active layer that can be obtained.   The method of claim 16, wherein a shape of the second ohmic contact layer is substantially the same as a shape of the high resistance material region. A method for processing a semiconductor light emitting device, comprising:
Forming a layered semiconductor structure on a growth substrate, the layered semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;
Removing a portion of the p-type layer;
Filling the region from which the p-type layer is removed with a high resistance material;
Forming a first ohmic contact layer having a conductive path to a first surface of the layered structure, the first ohmic contact layer covering the high resistance material;
Forming a bonding material layer on the first ohmic contact layer;
Bonding a low resistance substrate on the bonding material layer;
Removing the growth substrate to expose the second side of the layered structure;
Forming a second ohmic contact layer having a conductive path to the second surface of the layered structure, the second ohmic contact layer substantially corresponding to the high resistance material region A method wherein the flow of carriers is diverted from a portion in the active layer that is confined within the region, whereby vertically emitted light can be substantially blocked by the second ohmic contact layer.   The method of claim 18, wherein a shape of the second ohmic contact layer is substantially complementary to a shape of the high resistance material region.   The method of claim 18, wherein the high resistance material region penetrates the p-type layer.   19. The method of claim 18, further comprising removing a portion of the active layer and filling a region where the active layer has been removed with a high resistance material.

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