JP2014041999A - Semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element with high luminous efficiency.SOLUTION: A semiconductor light-emitting element includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light-emitting layer, a dielectric layer, a first electrode, and a second electrode. The first semiconductor layer has a first surface and a second surface at the opposite side of the first surface. The second semiconductor layer is provided on the second surface side of the first semiconductor layer. The light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The dielectric layer is in contact with the second surface and has a refractive index lower than that of the first semiconductor layer. The first electrode is in contact with the second surface and has a first portion that is provided adjacent to the dielectric layer and a second portion that is in contact with the opposite side of the dielectric layer from the first semiconductor layer. The first electrode is not overlapped with the second semiconductor layer when projected on a plane parallel to the second surface. The second electrode is in contact with the opposite side of the second semiconductor layer from the light-emitting surface. A supporting substrate is provided on the opposite side of the second electrode from the second semiconductor layer and is electrically connected to the second electrode.

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  As a structure of a semiconductor light emitting element such as an LED (Light Emitting Diode), for example, there is a structure in which a crystal layer formed on a substrate is bonded to a conductive substrate and then the substrate is removed. In this structure, the light extraction efficiency can be increased by performing uneven processing on the surface of the crystal layer exposed by removing the substrate. In addition, there is a structure in which electrodes are not formed on the surface of the crystal layer serving as a light extraction surface, and a p-side electrode and an n-side electrode are formed on the crystal surface opposite to the surface from which the substrate is removed. In such a semiconductor light emitting device, further improvement in light extraction efficiency is required.

JP 2006-210824 A

  Embodiments of the present invention provide a semiconductor light emitting device with high luminous efficiency.

  The semiconductor light emitting device according to the embodiment includes a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer, a light emitting layer, a dielectric layer, a first electrode, a second electrode, Is provided. The first semiconductor layer has a first surface and a second surface opposite to the first surface. The second semiconductor layer is provided on the second surface side of the first semiconductor layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer. The dielectric layer is in contact with the second surface and has a refractive index lower than that of the first semiconductor layer. The first electrode is in contact with the second surface and has a first portion provided adjacent to the dielectric layer, and a second portion in contact with the opposite side of the dielectric layer from the first semiconductor layer. Have. The first electrode does not overlap the second semiconductor layer when projected onto a plane parallel to the second surface. The second electrode is in contact with the side of the second semiconductor layer opposite to the light emitting layer. The support substrate is provided on the opposite side of the second electrode from the second semiconductor layer and is electrically connected to the second electrode.

FIG. 1A and FIG. 1B are schematic views showing the semiconductor light emitting device of the first embodiment. It is a typical sectional view showing the semiconductor light emitting element of a 1st embodiment. FIG. 3A and FIG. 3B are schematic cross-sectional views showing a semiconductor light emitting device according to a reference example. 4A and 4B are schematic cross-sectional views of the two-dimensional model used for the estimation. FIG. 5A and FIG. 5B are graphs showing characteristics derived from the approximation of the semiconductor light emitting device according to the two-dimensional model of FIG. FIG. 6A to FIG. 6C are schematic cross-sectional views showing the semiconductor light emitting device of the second embodiment. It is a typical sectional view of a 3rd embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and length of each part, the ratio coefficient of the size between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(First embodiment)
FIGS. 1A and 1B are schematic views showing the semiconductor light emitting device of the first embodiment.
FIG. 2 is a schematic cross-sectional view showing the semiconductor light emitting device of the first embodiment.
1A is a schematic cross-sectional view taken along line A1-A2 in FIG. 1B, and FIG. 1B is a schematic plan view.
In addition, FIG.1 (b) is the top view seen from the surface along the laminated structure mentioned later.
FIG. 2 is a schematic cross-sectional view taken along line B1-B2 in FIG.

  As shown in FIG. 1A, the semiconductor light emitting device 110 according to the first embodiment includes a first semiconductor 10, a second semiconductor 20, a light emitting layer 30, a dielectric layer 81, and a first electrode. 41, a second electrode 50, and a support substrate 54.

  The laminated structure 100 includes a first conductivity type first semiconductor layer 10, a second conductivity type second semiconductor layer 20, and a light emitting layer 30. The laminated structure 100 is formed in the order of the first semiconductor layer 10, the light emitting layer 30, and the second semiconductor layer 20, for example, on a growth substrate (not shown). The growth substrate is removed after the stacked structure 100 is formed. The first semiconductor layer 10 has a first surface 10a and a second surface 10b opposite to the first surface 10a. The second semiconductor layer 20 is provided on the second surface 10 b side of the first semiconductor layer 10. The light emitting layer 30 is provided between the first semiconductor layer 10 and the second semiconductor layer 20.

  In the present embodiment, a direction from the second semiconductor layer 20 toward the first semiconductor layer 10 is a Z direction. One of the directions orthogonal to the Z direction is defined as the X direction, and the direction orthogonal to the Z direction and the X direction is defined as the Y direction.

  For example, the first conductivity type is n-type and the second conductivity type is p-type. The first conductivity type may be p-type, and the second conductivity type may be n-type. In the present embodiment, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

The first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 each include a nitride semiconductor. The first semiconductor layer 10, the second semiconductor layer 20, and the light emitting layer 30 include, for example, Al _x Ga _1-xy In _y N (x ≧ 0, y ≧ 0, x + y ≦ 1).

  The first semiconductor layer 10 includes, for example, a Si-doped n-type GaN contact layer and a Si-doped n-type AlGaN cladding layer in order from the first surface 10a side. The first semiconductor layer 10 may further include a GaN buffer layer on the first surface 10a side of the Si-doped n-type GaN contact layer. The first surface 10a is a surface on which light emitted from the light emitting layer 30 is mainly emitted to the outside.

The light emitting layer 30 has, for example, a multiple quantum well structure (MQW) in which Si-doped n-type AlGaN barrier layers and InGaN well layers are alternately stacked in N cycles. N is an integer of 2 or more. For example, the light emitting layer 30 has MQW in which Si-doped n-type Al _0.11 Ga _0.89 N barrier layers and InGaN well layers are alternately stacked for six periods. In the Si-doped n-type Al _0.11 Ga _0.89 N barrier layer, for example, the Si concentration is 1.1 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ¹⁹ cm ⁻³ or less. For example, the MQW thickness of the light emitting layer 30 is 0.075 μm.

A final Al _0.11 Ga _0.89 N barrier layer is provided on the second semiconductor layer 20 side of the MQW. In the final Al _0.11 Ga _0.89 N barrier layer, for example, the Si concentration is 1.1 × 10 ¹⁹ cm ⁻³ or more and 1.5 × 10 ¹⁹ cm ⁻³ or less, and the thickness is 0.01 μm, for example. Meter (μm).

The final _Al 0.11 _{Ga 0.89} N second well layer 20 side of the barrier layer of the MQW, may further _Al 0.11 _{Ga 0.89} N barrier layer is provided. The wavelength of the emitted light in the light emitting layer 30 is, for example, 370 nanometers (nm) or more and 480 nm or less, or 370 nm or 400 nm or less.

The second semiconductor layer 20 includes a non-doped AlGaN spacer layer, an Mg-doped p-type AlGaN cladding layer, an Mg-doped p-type GaN contact layer, and a high-concentration Mg-doped p-type GaN contact layer in order from the side in contact with the light emitting layer 30. . Specifically, the second semiconductor layer 20 includes a non-doped Al _0.11 Ga _0.89 N spacer layer (for example, a thickness of 0.02 μm), a Mg-doped p-type Al _0.28 Ga _0.72 N cladding layer ( For example, the Mg concentration is 1 × 10 ¹⁹ cm ⁻³ , for example, the thickness is 0.02 μm, and the Mg-doped p-type GaN contact layer (for example, the Mg concentration is 1 × 10 ¹⁹ cm ⁻³ and the thickness is 0). .4 μm) and a highly-concentrated Mg-doped p-type GaN contact layer (for example, the Mg concentration is 5 × 10 ¹⁹ cm ⁻³ and the thickness is, for example, 0.02 μm).
Note that the above composition, composition ratio, impurity type, impurity concentration, and thickness are merely examples, and various modifications are possible.

  The dielectric layer 81 is in contact with a part of the second surface 10 b of the first semiconductor layer 10. The laminated structure 100 is provided with a recess 100t. The light emitting layer 30 and the second semiconductor layer 20 are divided by the recess 100t. The dielectric layer 81 is in contact with the first semiconductor layer 10 in the recess 100t.

  The refractive index of the dielectric layer 81 is lower than the refractive index of the first semiconductor layer 10. Due to the refractive index difference between the dielectric layer 81 and the first semiconductor layer 10, the reflectance in the direction from the first semiconductor layer 10 toward the dielectric layer 81 is improved.

  Here, a part of the light emitted from the light emitting layer 30 is reflected by the first surface 10 a of the first semiconductor layer 10. Of the light reflected by the first surface 10a, the light directed to the portion in contact with the second portion 41b of the dielectric layer 81 is totally reflected outside the escape cone and reflected or absorbed by the second portion 41b inside. Is done. The larger the refractive index difference between the dielectric layer 81 and the first semiconductor layer 10, the smaller the angle of the escape cone. When the angle of the escape cone is small, most of the light is totally reflected at the interface between the first semiconductor layer 10 and the dielectric layer 81. Therefore, it is preferable that the refractive index difference between the dielectric layer 81 and the first semiconductor layer 10 is large.

Since the first semiconductor layer 10 includes a nitride semiconductor, the refractive index of the first semiconductor layer 10 with respect to a wavelength of 450 nm is higher than about 2.2. Specifically, the refractive index of AlN is 2.2, the refractive index of GaN is 2.4, and the refractive index of InN is higher than 2.6. Accordingly, the dielectric layer 81 includes, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or silicon nitride oxide (SiON). The refractive indexes of these materials are all lower than the refractive index of the nitride semiconductor. For example, the refractive index of SiO ₂ is 1.4 to 1.5. When the dielectric layer 81 includes these materials, the refractive index difference between the dielectric layer 81 and the first semiconductor layer 10 increases. Thereby, the reflectance in the direction from the first semiconductor layer 10 toward the dielectric layer 81 is improved. In addition, these materials are particularly effective because they can be easily processed such as patterning.

  The dielectric layer 81 may have a first layer and a second layer having a refractive index different from that of the first layer and in contact with the first layer. The dielectric layer 81 has a refractive index equal to the refractive index of the first layer and a second k + 1 layer in contact with the second k layer, and a second k + 2 layer in contact with the second k + 1 layer having a refractive index equal to the refractive index of the second layer. And may have. However, k is an integer of 1 or more. At this time, the thickness of each layer is desirably 1/4 times the wavelength of light emitted from the light emitting layer 30. As a result, the dielectric layer 81 having a high reflectance is formed. Furthermore, the light extraction efficiency is improved.

  The dielectric layer 81 may be provided not only in contact with the first semiconductor layer 20 but also on a side surface of the multilayer structure 100 and a part of the second semiconductor layer 20 opposite to the first semiconductor layer 20. .

  The first electrode 41 has a first portion 41a and a second portion 41b. The first portion 41 a is in contact with a region of the second surface 10 b of the first semiconductor layer 10 that is not in contact with the dielectric layer 81. The first portion 41 a is provided adjacent to the dielectric layer 81. “A region of the second surface 10 b that is not in contact with the dielectric layer 81” is a first region A, which will be described later, and is an opening of the dielectric layer 81. The first electrode 41 is in contact with the first semiconductor layer 10 through this opening. For example, electrons are injected from the interface in contact with the first portion 41 a of the first electrode 41 toward the first semiconductor layer 10.

  The second portion 41 b of the first electrode 41 is in contact with a part of the dielectric layer 81 on the opposite side to the first semiconductor layer 10. In other words, the second portion 41 b is provided on the dielectric substrate 81 on the support substrate 54 side. The second portion 41b of the first electrode 41 does not contribute to carrier injection but functions as an auxiliary wiring for reducing the resistance of the first electrode 41.

  Here, a region where the first portion 41a of the first electrode 41 is in contact with the second surface 10b is referred to as a “first region A”. A region where the second portion 41 b overlaps with the dielectric layer 81 when viewed from the Z direction is referred to as a “second region B”. A region from the end of the dielectric layer 81 to the end of the first electrode 41 as viewed from the Z direction is referred to as a “third region C”. A region where the second electrode 50 is in contact with the second semiconductor layer 20 as viewed from the Z direction is referred to as a “fourth region D”.

  The first portion 41a of the first electrode 41 is provided on the opposite side of the second portion 41b from the second electrode 50 when projected onto a plane parallel to the second surface 10b. The second portion 41 b is provided at least between the first portion 41 a and the contact portion 51 of the second electrode 50 when viewed from the Z direction. Further, the second region B is provided between the first region A and the fourth region D when viewed from the Z direction. The third region C is located between the second region B and the fourth region D. For example, the first portion 41a is provided at the center of the recess 100t, and the second portion 41b is provided on both sides of the first portion 41a.

  In this way, the first portion 41a (first region A) with which the first electrode 41 is in contact is separated from the fourth region D by at least the length of the second region B. Thereby, the current spreads in a certain range from the first electrode 41 toward the second electrode 50 through the second region B overlapping the second portion 41b when viewed from the Z direction. Thereby, light emission can be obtained in a wide range.

  The first electrode 41 is preferably in ohmic contact with the first semiconductor layer 10. When the first electrode 41 is in contact with the n-type GaN contact layer, the material of the first electrode 41 on the side in contact with at least the second surface 10b is titanium (Ti), an alloy of Ti and aluminum (Al), or conductive Transparent oxide (for example, ITO). While these materials have good ohmic characteristics with respect to the n-type first semiconductor layer 10, the light reflectance of these materials is low. For example, when such a material is used, the first electrode 41 and the dielectric layer 81 are arranged as described above, so that the light extraction efficiency is improved and the spreading of the current is compatible.

  The first electrode 41 is not limited to these materials, and may be aluminum (Al), silver (Ag), gold (Au), or an alloy containing at least one of these having high reflectivity. . The light extraction efficiency is improved by increasing the reflectance of the first electrode 41. Further, as described later in the second embodiment, the first electrode 41 may have a structure of two or more layers.

  The dielectric layer 81 further has a portion that covers the first electrode 41 on the opposite side of the first electrode 41 from the first semiconductor layer 10. As a result, the first electrode 41 is electrically disconnected from the second electrode 50.

  Here, the dielectric layer 81 includes a first dielectric part 81a in contact with the first semiconductor layer 10, a second dielectric part 81b provided on the opposite side of the first electrode 41 from the first semiconductor layer 10, and Have For example, the first dielectric part 81a to the second dielectric part 81b are formed of the same material. In this case, no interface may be formed between the first dielectric part 81a and the second dielectric part 81b. The second dielectric part 81b may contain a material different from that of the first dielectric part 81a. In this case, an interface may be formed between the first dielectric part 81a and the second dielectric part 81b.

  The thickness of the first dielectric part 81a is, for example, 400 nm. The thickness of the second dielectric part b is, for example, 600 nm.

The second electrode 50 is in contact with a part of the second semiconductor layer 20 on the side opposite to the light emitting layer 30.
Further, the second electrode 50 includes a contact part 51 and a joining metal part 52. The contact part 51 is in contact with the second semiconductor layer 20. The bonding metal part 52 is provided on the opposite side of the contact part 51 from the first semiconductor layer 10 and is in contact with the support substrate 54. The joining metal portion 52 overlaps the first electrode 41 when viewed from the Z direction.

  The material on the side in contact with at least the second semiconductor layer 20 in the second electrode 50 contains Ag. Thereby, the reflectance at the interface between the second electrode 50 and the second semiconductor layer 20 is improved. The light extraction efficiency of the semiconductor light emitting device 110 is improved.

  Specifically, the contact part 51 contains Ag, for example. The thickness of the contact portion 51 is, for example, 200 nanometers (nm). The bonding metal part 52 is a layer in which, for example, Ti / Pt / Au is stacked from the second semiconductor layer 20 side.

  The support substrate 54 is provided on the opposite side of the second electrode 50 from the second semiconductor layer 20 and is electrically connected to the second electrode 50. A bonding layer 53 is provided between the support substrate 54 and the second electrode 50. Specifically, the bonding layer 53 is made of a material different from that of the bonding metal portion 52 of the second electrode 50. The bonding layer 53 includes AuSn alloy solder.

  The support substrate 54 overlaps the first semiconductor layer 10 when viewed from the Z direction. The area of the support substrate 54 is at least the area of the first semiconductor layer 10.

  The support substrate 54 has conductivity. Specifically, the support substrate 54 is, for example, a semiconductor substrate such as Si, or a metal substrate such as Cu or CuW. The support substrate 54 may be formed by plating. This eliminates the need for the bonding layer 53 and reduces the manufacturing cost. Further, there is no thermal history in the joining process, and thermal degradation is suppressed.

  A back electrode 55 is provided on the opposite side of the support substrate 54 from the second electrode 50. The back electrode 55 is a layer in which, for example, Ti / Pt / Au is laminated from the support substrate 54 side. The thickness of the back electrode 55 is, for example, 800 nm.

As shown in FIG. 1B, the first portion 41a extends in the first direction (for example, the Y direction) along the second surface 10a. The length l _na of the first portion 41a in the first direction (Y direction) is longer than the length w _na of the second direction (X direction) perpendicular to the first direction. The length w _na is the thin line width of the first portion 41a. For example, the first electrode 41 is a thin wire electrode having a shape that is long in the first direction.

For example, the length w _{na in} the second direction (X direction) of the first portion 41 a is greater than the length w _p in the second direction (X direction) of the second electrode 50 in the portion in contact with the second semiconductor layer 20. Also short.

  Further, the area of the second electrode 50 in contact with the second semiconductor layer 20 is larger than the area of the first electrode 41. “The area of the portion of the second electrode 50 in contact with the second semiconductor layer 20” roughly corresponds to the area of the contact portion 51. For example, the second electrode 50 is provided over the entire surface of the support substrate 54. The area of the second electrode 50 (including the bonding metal portion 53) is substantially equal to the area of the support substrate 54. On the other hand, the first electrode 41 is a thin wire electrode as described above. The first electrode 41 is not provided over the entire surface of the element.

  Here, the resistivity of the p-type second semiconductor layer 20 is higher than the resistivity of the n-type first semiconductor layer 10. Specifically, the resistivity of the p-type second semiconductor layer 20 is, for example, 100 times or more and 1000 times or less than the resistivity of the n-type first semiconductor layer 10. The carrier spread in the first semiconductor layer 10 is longer than the carrier spread in the second semiconductor layer 20. While the current spreads in a certain range in the first semiconductor layer 10, it tends to hardly spread in the second semiconductor layer 20.

  Since the first electrode 41 has a thin line shape, a portion where the second electrode 50 is in contact with the second semiconductor layer 20 can be expanded. With such an arrangement, the light emitting region is expanded by current spreading within a limited element area.

  Further, as described above, the second electrode 50 is electrically connected to the support substrate 54. The support substrate 54 overlaps the first electrode 41 when viewed from the Z direction. Therefore, the first electrode 41 does not hinder the conduction between the second electrode 50 and the support substrate 54 by guiding the first electrode 41 in a thin shape from a pad described later.

The second portion 41b is provided on both sides of the first portion 41a when viewed from the Z direction. For example, the area of the second portion 41b is larger than the area of the first portion 41a. For example, the length l _nb in the Y direction of the second portion 41b is longer than the length l _na in the Y direction of the first portion 41a. For example, the length w _nb in the X direction of the first electrode 41 is longer than the length w _na in the X direction of the first portion 41a.

The first portion 41a of the first electrode 41 is a region that easily absorbs light. For this reason, it is preferable that the first portion 41a is limited to a range necessary for carrier injection. Specifically, the length _{w na} of the first portion 41a of the first electrode 41 is, for example, 5μm or more 15μm or less. As the length _{w na} of the first portion 41a is long, the contact resistance decreases. As a result, the operating voltage of the semiconductor light emitting device 110 decreases. However, normally, the contact resistance of the first portion 41a is lower than the contact resistance of the second electrode 50, and the first semiconductor layer 10 has a lower resistivity than the second semiconductor layer 20, so that the current flows through the first portion 41a. It is biased toward the second electrode 50 side. Therefore, when the length in the X-direction length w _na of the first portion 41a is equal to or greater than a predetermined value, the lowering of the operating voltage is saturated. The length w _na in the X direction of the first portion 41a is determined in consideration of the current spread in the X direction.

On the other hand, the length w _nb in the X direction of the first electrode 41 is, for example, 20 μm. Thereby, the resistance of the first electrode 41 decreases. Furthermore, when it is desired to reduce the resistance of the first electrode 41, the length _Wnb may be increased, for example, 50 μm. However, since the area of the second electrode 50 is reduced as the second portion 41b is lengthened, the light emission region and the reflection region may be reduced, and the light output may be reduced. Considering these, the length W _nb can be determined.

  In addition, as illustrated in FIG. 1B, the first electrode 41 includes an extending portion 43 provided to the outside of the first semiconductor layer 10. The extending portion 43 is provided in the opening of the first semiconductor layer 10. The pad 42 is provided in the extending portion 43 when viewed from the Z direction. The pad 42 is in contact with the extending portion 43. As a result, a current is supplied from the pad 42 to the first electrode 41. For example, a plurality of pads 42 may be provided. The pad 42 has a rectangular shape when viewed from the Z direction, for example.

  The first portion 41a is separated from the pad 42 by a predetermined distance. Thereby, it is suppressed that the injection | pouring area | region of the electron from the 1st part 41a of a 1st electrode concentrates on the pad 42 side of the 1st part 41a.

The length w _{pad in} the second direction (X direction) of the pad 42 is longer than the length w _na of the first portion 41a. For example, one side of the outer periphery of the pad 42 is greater than the length _{w na} of the first portion 41a. Thereby, a bonding wire (not shown) is stably connected to the pad 42. Specifically, the length w _pad of the pad 42 is, for example, 130 μm.

  As illustrated in FIG. 2, the extended portion 43 is exposed from the first semiconductor layer 10 by removing a part of the multilayer structure 100. A pad 42 is provided on the opposite side of the extending portion 43 from the support substrate 54. The second dielectric portion 81 b of the dielectric layer 81 is in contact with the extending portion 43 on the support substrate 54 side. The extending portion 43 overlaps the support substrate 54 when viewed from the Z direction through at least the second dielectric portion 81 b of the dielectric layer 81.

The growth substrate (not shown) is removed from the first surface 10 a of the first semiconductor layer 10.
The first surface 10 a of the first semiconductor layer 10 has a plurality of uneven portions 12. It is preferable that the length between adjacent convex portions in the concavo-convex portion 12 is equal to or greater than the peak wavelength in the first semiconductor layer 10 of the emitted light emitted from the light emitting layer 30. When the length of the adjacent convex portion of the concavo-convex portion 12 is smaller than the wavelength of the emitted light, the emitted light incident on the concavo-convex portion 12 is explained by wave optics such as scattering and diffraction at the interface of the concavo-convex portion 12. Shows the behavior. For this reason, the uneven portion 12 prevents a part of the emitted light from being extracted. Moreover, when the length of the adjacent convex part among the uneven | corrugated | grooved parts 12 is sufficiently smaller than the wavelength of emitted light, the part in which the uneven | corrugated | grooved part 12 was provided is regarded as a layer from which a refractive index changes continuously. For this reason, the 1st surface 10a becomes the same as the flat surface in which the unevenness | corrugation is not provided. The effect of improving the light extraction efficiency by the uneven portion 12 is reduced.

The planar shape of the uneven portion 12 of the first surface 10a is, for example, a hexagon. In this case, the length between adjacent convex parts is the length of the diagonal vertex among hexagons. For example, the uneven portion 12 is formed by anisotropically etching the first semiconductor layer 10 with a KOH solution. Thereby, the light emitted from the light emitting layer 30 is Lambert-reflected at the interface (first surface 10a) between the first semiconductor layer 10 and the outside world.
Further, the uneven portion 12 may be formed by dry etching using a mask. In this method, the uneven portion 12 is formed as designed. For this reason, the light extraction efficiency is easily improved.

The semiconductor light emitting device 110 may further include a dielectric layer 83 that covers the side surface of the first semiconductor layer 10, the side surface of the light emitting layer 30, and the side surface of the second semiconductor layer 20. The dielectric layer 83 includes the same material as that of the dielectric layer 81, for example. Specifically, the dielectric layer 83 includes SiO _2. The dielectric layer 83 functions as a protective layer for the laminated structure 100. Thereby, deterioration and leakage of the semiconductor light emitting element 110 are suppressed.

  The semiconductor light emitting device 110 may cover the stacked structure 100 and further include a sealing portion (not shown). For example, a resin is used for the sealing portion. The sealing portion may include a phosphor that is excited by light emitted from the light emitting layer 30 and emits light.

Next, characteristics of the semiconductor light emitting device 110 according to the first embodiment will be described in comparison with the reference example.
3A and 3B are schematic cross-sectional views showing a semiconductor light emitting device according to a reference example. FIG. 3A illustrates the semiconductor light emitting device 191 of the first reference example. FIG. 3B illustrates the semiconductor light emitting device 192 of the second reference example.

As shown in FIG. 3A, the first electrode 41 of the semiconductor light emitting device 191 according to the first reference example has only the first portion 41a in the first embodiment. The second portion 41b is not provided on the dielectric substrate 81 on the support substrate 54 side. That is, only the dielectric layer 81 is provided in the second region B, and the first electrode 42 is not provided. Note that the length in the X direction of the first electrode 41 in the first reference example is equal to the length (w _na ) of the first portion 41a in the first embodiment.

  As shown in FIG. 3B, the first electrode 41 of the semiconductor light emitting device 192 according to the second reference example also includes only the first portion 41a in the first embodiment. In the second reference example, the first electrode 41 is provided to the vicinity of the side surface of the light emitting layer 30. The length in the X direction of the first electrode 41 in the second reference example is longer than the length in the X direction of the first portion 41a in the first reference example. The second region B in the second reference example is shorter than the second region B in the first embodiment.

  The configurations of the other parts of the semiconductor light emitting device 191 of the first reference example and the semiconductor light emitting device 192 of the second reference example are the same as those of the semiconductor light emitting device 110 of the first embodiment.

  Here, with reference to FIG. 4, the light extraction efficiency and the resistance of the first electrode 41 will be described in the first embodiment, the first reference example, and the second reference example. In each case, the estimation was performed under the following conditions.

4A and 4B are schematic cross-sectional views of the two-dimensional model used for the estimation.
Each of FIG. 4A and FIG. 4B shows a cross-sectional view in the XZ plane.
FIG. 4A is a schematic cross-sectional view of the semiconductor light emitting device 110 according to the first embodiment.
FIG. 4B is a schematic cross-sectional view of the semiconductor light emitting device 191 of the first reference example and the semiconductor light emitting device 192 of the second reference example.
Consider a simplified two-dimensional model of a semiconductor light emitting device as shown in FIGS. For simplification of the drawing, the light emitting layer 30 and the second semiconductor layer 20 are omitted. Further, consider the case where the first electrode 41 is provided on a straight line in the Y direction. The “resistance of the first electrode 41” is a resistance when a current is passed in the Y direction with respect to the first electrode 41 extending in the Y direction in FIG.

The following conditions are assumed in all of the first embodiment, the first reference example, and the second reference example.
The light emitted from the light emitting layer 30 is extracted from the first surface 10 a while being multiple-reflected between the first surface 10 a and the contact portion 51 of the second electrode 50. The light emitted from the light emitting layer 30 is Lambert-reflected by the first surface 10a. The first semiconductor layer 10 is covered with a silicone resin. In this case, the light extraction efficiency from the first surface 10a of the first semiconductor layer 10 is 28%. That is, the reflectance of light in the first surface 10a is 72%. Further, it is assumed that the absorption rate of emitted light inside the laminated structure 100 is 2% per round trip.

  As described above, the first region A is a region where the first portion 41a of the first electrode 41 is in contact with the second surface 10b. The second region B is a region where the second portion 41 b overlaps with the dielectric layer 81 when viewed from the Z direction. The third region C is a region from the end of the dielectric layer 81 to the end of the first electrode 41 as viewed from the Z direction. The fourth region D is a region where the second electrode 50 is in contact with the second semiconductor layer 20 as viewed from the Z direction.

In the X direction, the length of the semiconductor light emitting element is W, and the length of one region of the second regions B provided on both sides of the first region A is _wd1 . The length in the X direction of one of the third regions C provided on both sides of the first electrode 41 is defined as w _d2 . In the case of the first embodiment, the length of the first portion 41a (the length of the first region A in the X direction) is w _na , and the length of the first electrode 41 in the X direction is w _nb. . That is, w _nb = w _na + 2w _d1 . It is assumed that the thickness of the first portion 41a and the thickness of the second portion 41b are the same.

On the other hand, as shown in FIG. 4B, in the case of the first reference example and the second reference example, since the first electrode 41 does not have the second portion 41b, the length of the first electrode 41 is w _na. Suppose that

The reflectance of the first portion 41a of the first electrode 41 (the reflectance of the first region A) is R _n , the reflectance of the second region B is R _d1 , the reflectance of the third region C is R _d2 , the second electrode The reflectance of 50 contact portions 51 (the reflectance of the fourth region D) is R _p . For simplification, the reflectance of the entire semiconductor light emitting element is R _total , and the reflectance R _total is an average value obtained by weighting the length in the X direction with respect to the reflectance of each region. Assume that it is given in (1).

_{R total = w na R p /} W + 2w d1 R d1 / W + 2W d2 R d2 / W + (W-2w d1 -2W d2 -w na) R p / W ··· (1)

Further, when the resistance of the first electrode 41 is r, the length of the first electrode 41 in the Y direction is l _na , the electrical resistivity of the first electrode 41 is ρ, and the thickness of the first electrode 41 is t, Is given by the following equation (2).

r = ρl _na / (w _nb t) (2)

Here, the reflectance R _total and the resistance r of the first electrode 41 were estimated under the following conditions.
The laminated structure 100 is GaN, and the dielectric layer 81 is SiO ₂ . The material of the first electrode 41 is Ti / Au. The material of the portion of the first electrode 41 in contact with the laminated structure 100 is Ti. The material of the contact portion 51 of the second electrode 50 is Ag.
In this case, the reflectance R _p of the contact portion 51 (fourth region D) of the second electrode 50 is 95.1%.
The reflectance R _n of the first portion 41a (first region A) of the first electrode 41 is 46.5%.
The reflectance at the interface between the laminated structure 100 and the dielectric layer 81 is obtained as follows. The light that enters the escape cone determined by the refractive index difference between the laminated structure 100 and the dielectric layer 81 is reflected by Ti having a low reflectance. Other light is totally reflected at the interface between the laminated structure 100 and the dielectric layer 81. Therefore, the reflectance Rd1 in the second region B and the reflectance Rd2 in the third region C are 91.6%, respectively.

In any semiconductor light emitting element, the thickness (t) of the first electrode 41 is 0.7 μm, and Ti and Au are laminated films of 0.1 μm and 0.6 μm, respectively. The length (l _na ) in the Y direction of the first electrode 41 is 300 μm.

Other conditions in the semiconductor light emitting device 110 of the first embodiment are as follows.
The length W in the X direction of the semiconductor light emitting device 110 is 200 μm.
The length w _na in the X direction of the first region A is 10 μm.
The length w _d1 in the X direction of one of the second regions B provided on both sides of the first region A is 5 μm. That is, the total length (2w _d1 ) in the X direction of the second region B is 10 μm.
The length _wd2 in the X direction of one of the third regions C provided on both sides of the first electrode 41 is 5 μm. That is, the total length (2w _d2 ) in the X direction of the third region C is 10 μm.
The length of the fourth region D in the X direction (W−2w _d1 −2W _d2 −w _na ) is 170 μm.

Other conditions in the semiconductor light emitting device 191 of the first reference example are as follows.
The length W in the X direction of the semiconductor light emitting element 191 is equal to that of the semiconductor light emitting element 110 and is 200 μm.
The length w _na in the X direction of the first region A is equal to that of the semiconductor light emitting device 110 and is 10 μm.
Since the second region B is not provided, the total length (2w _d1 ) in the X direction of the second region B is 0 μm.
The total length (2w _d2 ) of the third region C in the X direction is 20 μm.
The length of the fourth region D in the X direction (W−2w _d1 −2W _d2 −w _na ) is 170 μm.

Other conditions in the semiconductor light emitting device 192 of the second reference example are as follows.
The length W in the X direction of the semiconductor light emitting device 192 is equal to that of the semiconductor light emitting device 110 and is 200 μm.
The length w _na in the X direction of the first region A is 20 μm.
Since the second region B is not provided, the total length (2w _d1 ) in the X direction of the second region B is 0 μm.
The total length (2w _d2 ) in the X direction of the third region C is 10 μm.
The length of the fourth region D in the X direction (W−2w _d1 −2W _d2 −w _na ) is 170 μm.

Under the above conditions, the light extraction efficiency and the resistance of the first electrode 41 are as follows.
The light extraction efficiency in the first reference example is 77.2%.
The resistance of the first electrode 41 in the first reference example is 1.24Ω.

The light extraction efficiency in the second reference example is 73.0%.
The resistance of the first electrode 41 in the second reference example is 0.62Ω.

The light extraction efficiency in the first embodiment is 77.2%.
The resistance of the first electrode 41 in the first embodiment is 0.62Ω.

  Thus, the light extraction efficiency in the first embodiment is 4.2 points (5.8%) higher than the light extraction efficiency in the second reference example. Further, the resistance of the first electrode 41 in the first embodiment is ½ times the resistance of the first electrode 41 in the first reference example.

The above approximate result is considered to be due to the following effects.
In the first reference example in FIG. 3A, the length w _na of the first electrode 41 is equal to the length w _na of the first electrode 41 in the first embodiment. The first electrode 41 does not have the second portion 41 b and is not provided on the support substrate 54 side of the dielectric layer 81. As described above, the reflectance of the first electrode 41 is lower than the reflectance at the interface between the first semiconductor layer 10 and the dielectric layer 81. In the first reference example, the area of the first electrode 41 which is a light absorption region is small. Thereby, the light extraction efficiency of the first reference example is higher than the light extraction efficiency of the second reference example.
However, the cross-sectional area of the first electrode 41 of the first reference example is smaller than that of the second reference example. For this reason, the resistance of the first electrode 41 is high. In the first reference example, there is a possibility that the current is difficult to spread over the entire semiconductor light emitting element 191.

In the second reference example in FIG. 3B, the length w _na of the first electrode 41 is equal to the entire length (w _nb ) of the first electrode 41 in the first embodiment. The length w _na of the first electrode 41 of the second reference example is longer than the length w _na of the first electrode of the first reference example. The cross-sectional area of the first electrode 41 of the second reference example is larger than the cross-sectional area of the first reference example. Thereby, the resistance of the first electrode 41 of the second reference example is lower than the resistance of the first electrode 41 of the first reference example.
However, in the second reference example, the area of the first electrode 41 which is a light absorption region is large. For this reason, in the second reference example, the light extraction efficiency is low.

  On the other hand, as shown in FIG. 1A, in the first embodiment, the first electrode 41 is in contact with a region of the first semiconductor layer 10 that is not in contact with the dielectric layer 81. 41a and a second portion 41b in contact with a part of the dielectric layer 81 opposite to the first semiconductor layer 10. In the first embodiment, the first portion 41a is provided in a minimum range necessary as a carrier injection region. The second portion 41b is provided on the support substrate 54 side of the dielectric layer 81 and functions as an auxiliary wiring. Thereby, the resistance of the first electrode 41 in the first embodiment is lower than the resistance of the first reference example. In the first embodiment, since the resistance of the first electrode 41 is low, the current spreads over the entire semiconductor light emitting device 110.

  In the first embodiment, the dielectric layer 81 is provided between the second portion 41 b of the first electrode 41 and the first semiconductor layer 10. The dielectric layer 81 has a refractive index lower than that of the first semiconductor layer 10 as described above. Due to the refractive index difference between the dielectric layer 81 and the first semiconductor layer 10, the reflectance in the direction from the first semiconductor layer 10 toward the dielectric layer 81 is improved. In the second reference example, the area of the first electrode 41 is large and the area of the dielectric layer 81 is small. For this reason, the light extraction efficiency in the first embodiment is higher than the light extraction efficiency of the second reference example.

FIG. 5A and FIG. 5B are graphs showing characteristics derived from the approximation of the semiconductor light emitting device according to the two-dimensional model of FIG.
The horizontal axis of FIG. 5A represents the ratio (w _na / w _nb ) of the length w _na of the first portion 41 a in the X direction to the length w _nb of the first electrode 41 in the X direction.
5A, the vertical axis represents the resistance r (Ω) of the first electrode 41 and the area of the contact portion 51 of the second electrode 50 at the operating current of 100 mA (area of the fourth region D). 110 is the current density J (A / cm ² ) injected into the light emitting layer 30, or the light extraction efficiency LE (%) of the semiconductor light emitting device 110.
The horizontal axis of FIG. 5B is the ratio (l _na / w _nb ) of the length l _na of the first electrode 41 in the Y direction to the length w _nb of the first electrode 41 in the X direction.
The vertical axis in FIG. 5B is equal to the vertical axis in FIG.

The conditions in FIGS. 5A and 5B are as follows.
The length (l _na ) in the Y direction of the first electrode 41 is 300 μm.
The thickness (t) of the first electrode 41 is 0.7 μm, and Ti and Au are laminated films of 0.1 μm and 0.6 μm, respectively.
The length W in the X direction of the semiconductor light emitting device 110 is 200 μm.
The length w _na in the X direction of the first region A is 10 μm.
The length w _d1 in the X direction of one of the second regions B provided on both sides of the first region A is 5 μm. That is, the total length (2w _d1 ) in the X direction of the second region B is 10 μm.
The length w _{nb of} the first electrode 41 in the X direction and the length of the fourth region D in the X direction (W−2w _d1 −2W _d2 −w _na ) are variables.

As shown in FIG. 5A, the smaller the ratio w _na / w _nb (that is, the longer the length w _d2 of one of the second regions B), the greater the resistance r of the first electrode 41. Significantly decreases, the light extraction efficiency LE decreases, and the current density J increases. This is because as the length w _d2 is longer, the area of the fourth region D having a higher reflectance decreases.

In particular, the current density J at w _na / w _nb <0.1 is larger than twice the current density J when w _na / w _nb = 1. When the current density J injected into the light emitting layer 30 of the semiconductor light emitting device 110 is high, the amount of heat generated per unit area in the contact portion 51 becomes large, and thermal degradation is likely to occur. Further, the optical output is reduced due to a decrease in internal quantum efficiency due to the efficiency drop phenomenon.
Therefore, the ratio w _na / w _nb is preferably 0.1 or more and 1 or less.

As shown in FIG. 5B, the smaller the ratio l _na / w _nb (that is, the longer the length w _nb of the second portion 41b), the same tendency as in FIG.

In particular, the current density J at l _na / w _nb <3 is larger than twice the current density J when l _na / w _nb = 30.
Therefore, the ratio l _na / w _nb is preferably 3 or more and 30 or less.

  As described above, in the first embodiment, a semiconductor light-emitting element having both light extraction efficiency and current spreading is provided.

Next, an example of a method for manufacturing the semiconductor light emitting device according to the first embodiment will be described.
First, the first semiconductor layer 10 including the nitride semiconductor, the light emitting layer 30, and the second semiconductor layer 20 are grown on the growth substrate in order. Thereby, the laminated structure 100 is formed on the growth substrate. A buffer layer may be formed between the growth substrate and the first semiconductor layer 10. For example, Si is used for the growth substrate. For example, any of Si, SiO ₂ , quartz, sapphire, GaN, SiC, and GaAs is used for the growth substrate. At this time, the plane orientation of the growth substrate is arbitrary. Hereinafter, an example in which a sapphire substrate is used as the growth substrate will be described.

  Next, the recessed part 100t is formed in a part of the laminated structure 100 by, for example, dry etching. The recess 100 t reaches the first semiconductor layer 10 from the second surface 10 b of the laminated structure 100. As a result, the first semiconductor layer 10 is exposed at the bottom of the recess 100t. This bottom is the second surface 10 b of the first semiconductor layer 10.

  The recess 100 t is a region for forming the second portion 41 b and the extending portion 43 connected to the pad 42.

Next, a dielectric layer 81 having a refractive index lower than that of the first semiconductor layer 10 is formed in the recess 100t. Specifically, SiO ₂ is formed as the dielectric layer 81 with a thickness of 400 nm. A part of the dielectric layer 81 in the recess 100t is selectively removed by wet etching, for example. For example, an opening having a length of 10 μm is formed in the bottom of the recess 100 t in the dielectric layer 81. As a result, a dielectric layer 81 (first dielectric portion 81a) in contact with a part of the second surface 10b is formed.

  Next, the first electrode 41 is formed on the first semiconductor layer 10 and the dielectric layer 81 by, for example, lift-off. Accordingly, the first portion 41a that is in contact with the region of the second surface 10b that is not in contact with the dielectric layer 81, and the second portion 41b that is in contact with a portion of the dielectric layer 81 opposite to the first semiconductor layer 10 Are formed. Specifically, Ti / Pt / Au / Ti is formed with a thickness of 700 nm from the first semiconductor layer 10 side. In order to improve ohmic properties, sintering may be performed at 650 ° C. in a nitrogen atmosphere for 1 minute. The length in the X direction of the second portion 41b of the first electrode 41 is, for example, 20 μm.

Next, a dielectric layer 81 (second dielectric portion 81b) is further formed on the first electrode 41. Specifically, SiO ₂ is formed with a thickness of 600 μm as the second dielectric portion 81b. As a result, the second dielectric portion 81b of the dielectric layer 81 covering the opposite side of the first electrode 41 from the first semiconductor layer 10 is formed.

  Next, a part of the dielectric layer 81 remaining on the second semiconductor layer 20 is selectively removed by wet etching, for example. Next, the contact portion 51 of the second electrode 50 is formed on the second semiconductor layer 20. Specifically, Ag is formed with a thickness of 200 nm as the second electrode 50. Sintering is performed at 400 ° C. in an oxygen atmosphere for 1 minute. Thereby, the contact part 51 of the 2nd electrode 50 which contacts a part on the opposite side to the light emitting layer 30 among the 2nd semiconductor layers 20 is formed.

  Next, for example, a Ti / Pt / Au laminated film having a thickness of 800 nm is formed as the bonding metal portion 52 on the opposite side of the contact portion 51 from the second semiconductor layer 20.

  In parallel with these steps, for example, a Si support substrate 54 is prepared. For example, the bonding layer 53 is provided on the upper surface of the support substrate 54. For the bonding layer 53, for example, solder having a thickness of 3 μm is used. The solder includes an AuSn alloy.

  Next, the bonding metal portion 52 of the second electrode 50 and the bonding layer 53 are opposed to each other and heated and bonded at a temperature equal to or higher than the eutectic point of the solder, for example. Specifically, the temperature is 300 ° C. Thereby, the support substrate 54 is joined to the laminated structure 100 and is electrically connected to the second electrode 50.

  Next, a laser beam of, for example, the third harmonic (355 nm) or the fourth harmonic (266 nm) of a solid laser of YVO4 is irradiated from the surface opposite to the stacked structure 100 of the growth substrate. For example, GaN at the interface between the growth substrate and the laminated structure 100 is decomposed into Ga and N. Then, the decomposed Ga is removed by hydrochloric acid treatment or the like, and the growth substrate is peeled off from the laminated structure. Thereby, the growth substrate and the laminated structure are separated.

  Next, for example, dry etching is performed from the opposite side of the laminated structure 100 to the support substrate 54. Thereby, the first surface 10a of the first semiconductor layer 10 is exposed. At this time, the etching amount is adjusted so that the thickness of the first semiconductor layer 10 is 4 μm.

  Next, a part of the laminated structure 100 is selectively removed by dry etching. A part of the dielectric layer 81 and a part of the first electrode 41 are exposed. As a result, the extended portion 43 of the first electrode 41 exposed outside the first semiconductor layer 10 is formed.

Next, on the side surface of the laminated structure 100, a part of the first surface 10a of the first semiconductor layer 10, a part of the dielectric layer 81 exposed as described above, and the extension part 43 of the first electrode 41 Then, the dielectric layer 83 is selectively formed. Specifically, as the dielectric layer 83, SiO ₂ is formed with a thickness of 600 nm. Note that the first surface 10 a of the first semiconductor layer 10 is exposed from the opening of the dielectric layer 83.

  Next, using the dielectric layer 83 as a mask, the first surface 10a of the first semiconductor layer 10 is etched by, for example, a KOH solution. Thereby, the uneven | corrugated | grooved part 12 is formed in the 1st surface 10a. For example, a 1 mol / L KOH solution is heated to 80 ° C. and etched for 20 minutes.

  Next, the dielectric layer 83 on the extending portion 43 of the first electrode 41 is removed by wet etching, for example. Next, Ti / Pt / Au, for example, is selectively formed on the extending portion 43 of the first electrode 41 with a thickness of 500 nm. Thereby, the pad 42 is formed.

  Next, the surface of the support substrate 54 opposite to the laminated structure 100 is ground to a thickness of about 100 μm. For example, Ti / Pt / Au is formed with a thickness of 800 nm on the surface of the support substrate 54 opposite to the laminated structure 100. Thereby, the back surface electrode 55 is formed.

  Next, the support substrate 54 is cut by, for example, cleavage or a diamond blade. Thereby, the semiconductor light emitting device 110 is obtained. Note that the semiconductor light emitting element 110 may be mounted on a mounting substrate or the like.

(Second Embodiment)
6A to 6C are schematic cross-sectional views showing the semiconductor light emitting device of the second embodiment.
The second embodiment is different from the first embodiment in that the first electrode 41 has a two-layer structure. Other configurations in the second embodiment are the same as those in the first embodiment.

6A to 6C are cross-sectional views showing the vicinity of the first electrode 41 in the semiconductor light emitting device. Each figure shows a different specific example in the second embodiment.
As in the first embodiment, the first electrode 41 includes a first portion 41a that is in contact with a region of the second surface 10b that is not in contact with the dielectric layer 81, and the first semiconductor layer 10 of the dielectric layer 81. A second portion 41b in contact with a part of the opposite side.

FIG. 6A shows a first specific example of the second embodiment.
As shown in FIG. 6A, the first electrode 41 includes a first conductive layer 411 and a second conductive layer 412. The first conductive layer 411 has a first portion 41a. The second conductive layer 412 has a second portion 41 b and is in contact with the side of the first conductive layer 411 opposite to the first semiconductor layer 10. The portion where the first conductive layer 411 contacts the dielectric layer 81 is wider than the portion where the second conductive layer 412 contacts the dielectric layer 81.

  Here, the first conductive layer 411 preferably includes a material that is in ohmic contact with the first semiconductor layer 10 in order to inject carriers into the first semiconductor layer 10. Specifically, the first conductive layer 411 includes Ti, Au, Al, Ag, an alloy including any one of these, or a conductive transparent oxide (for example, ITO).

  On the other hand, the second conductive layer 412 includes a material different from the material of the first conductive layer 411. The second conductive layer 412 functions as an auxiliary wiring for reducing the resistance of the first electrode 41. The second conductive layer 412 preferably includes a material having a lower resistivity than the first conductive layer 411. Specifically, the second conductive layer 412 includes Al, Ag, Cu, or an alloy including any one of these.

  Next, a second specific example and a third specific example in the second embodiment will be described. The second specific example and the third specific example described below are modifications of the first specific example described above.

FIG. 6B shows a second specific example of the second embodiment.
As illustrated in FIG. 6B, the first electrode 41 includes a first conductive layer 411 and a second conductive layer 412. The dielectric layer 81 may be provided in contact with the peripheral portion 411p on the opposite side of the first conductive layer 411 from the first semiconductor layer 10. A peripheral portion 411 p of the first conductive layer 411 is covered with a dielectric layer 81. This makes it difficult for the first conductive layer 411 to peel off from the first semiconductor layer 10. Note that the second conductive layer 412 includes a material different from the material of the first conductive layer 411.

FIG. 6C shows a third specific example of the second embodiment.
As shown in FIG. 6C, the first conductive layer 411 may include a first portion 41a and a second portion 41b. The second conductive layer 412 is provided in a region overlapping the first conductive layer 411 when viewed from the Z direction, and is in contact with the opposite side of the first conductive layer 411 to the first semiconductor layer 10. Also in the third specific example, the dielectric layer 81 is provided in contact with the peripheral portion 411p of the first conductive layer 411 opposite to the first semiconductor layer 10. Note that the second conductive layer 412 includes a material different from the material of the first conductive layer 411. For example, the first conductive layer 411 and the second conductive layer 412 are patterned by a single etching process.

  In the second embodiment, the first electrode 41 includes a first conductive layer 411 responsible for carrier injection, and a second conductive layer 412 functioning as an auxiliary wiring. Thereby, an optimal material can be selected according to the roles of the first conductive layer 411 and the second conductive layer 412.

(Third embodiment)
FIG. 7 is a schematic cross-sectional view of the third embodiment.
The third embodiment is different from the first embodiment in that the first electrode 41 rides on the support substrate 54 side of the second electrode 50. Other configurations in the third embodiment are the same as those in the first embodiment.

  As shown in FIG. 7, the dielectric layer 81 is provided in contact with a part of the contact portion 51 of the second electrode 50 on the side opposite to the second semiconductor layer 20. The dielectric layer 81 is in contact with a part of the second surface 10 b of the first semiconductor layer 10, the side surface of the multilayer structure 100, the surface on the support substrate 54 side, and the peripheral portion of the second electrode 50.

  The second portion 41b of the first electrode 41 is provided up to a position overlapping the second electrode 50 when viewed from the Z direction. The second portion 41b also overlaps a part of the light emitting layer 30 and a part of the second semiconductor layer 20 when viewed from the Z direction. In this case, as viewed from the Z direction, the entire bonding metal portion 52 of the second electrode 50 overlaps the second portion 41 b of the first electrode 41 or the contact portion 51 of the second electrode 50. In other words, the bonding metal part 52 is hidden from the first surface 10a.

  In the third embodiment, the material on the side in contact with at least the second surface 10 b of the first electrode 41 is a material that is in ohmic contact with the first semiconductor layer 10, and has a light reflectance higher than that of the bonding metal part 52. It is preferable to include a material having a high value. With the above arrangement, the emitted light incident on the dielectric layer 81 from the light emitting layer 30 is reflected by the second portion 41 b of the first electrode 41 without reaching the bonding metal portion 52. Thereby, the light extraction efficiency is improved.

  The material of at least the side in contact with the second surface of the first electrode 41 is, for example, Al. The material on the second semiconductor layer 20 side of the bonding metal part 52 is Ti. Specifically, the first electrode 41 is, for example, Al / Ni / Au / Ti from the first semiconductor layer 10 side. The thickness of the first electrode 41 is, for example, 800 nm.

  In the third embodiment, the second portion 41 b of the first electrode 41 is provided up to the support substrate 54 side of the contact portion 51 of the second electrode 50. Thereby, the area of the 1st electrode 41 is expanded and the resistance of the 1st electrode 41 can be reduced arbitrarily.

  In addition, the resistance of the first electrode 41 can be reduced, and the length of the recess 100t in the X direction can be shortened. In other words, the area where the first electrode 41 and the dielectric layer 81 are in contact with the first semiconductor layer 10 can be reduced. Thereby, the area of the contact part 51 of the 2nd electrode 50 can be expanded. As described above, the resistivity of the p-type second semiconductor layer 20 is higher than the resistivity of the n-type first semiconductor layer 10. Therefore, since the area of the contact portion 51 of the second electrode 50 is large, the light emitting region can be expanded. In addition, since the current density can be reduced, the light emission efficiency is improved and the operating voltage is reduced.

  The method for manufacturing a semiconductor light emitting device according to the third embodiment is the same as that of the first embodiment except that the contact portion 51 of the second electrode 50 is formed before the first electrode 41 is formed. It is the same.

  As described above, a semiconductor light emitting element with high luminous efficiency can be provided.

Although this Embodiment and its modification were demonstrated above, this invention is not limited to these examples.
For example, as a method of forming the laminated structure 100, other techniques such as a molecular beam epitaxial growth method can be used in addition to the metal organic vapor phase growth method.
Further, the entire support substrate 54 does not need to have conductivity, and a conductor such as a metal wiring may be formed on the surface of an insulating base material such as resin.
The emission wavelength of the quantum well layer is not limited to the above. For example, when a GaInN gallium nitride compound semiconductor is used for the quantum well layer, light emission of 370 nm to 700 nm can be obtained.

  In addition, although this Embodiment and its modification were demonstrated above, this invention is not limited to these examples. For example, for each of the above-described embodiments or modifications thereof, those in which those skilled in the art appropriately added, deleted, and changed the design of the embodiments, and those that appropriately combined the features of each embodiment, As long as the gist of the present invention is provided, it is included in the scope of the present invention.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 10a ... 1st surface, 10b ... 2nd surface, 12 ... Uneven part, 20 ... 2nd semiconductor layer, 30 ... Light emitting layer, 41 ... 1st electrode, 41a ... 1st part, 41b ... Second part, 42 ... pad, 43 ... extension part, 50 ... second electrode, 51 ... contact part, 52 ... bonding metal part, 53 ... bonding layer, 54 ... support substrate, 55 ... back electrode, 81 ... dielectric Body layer, 81a ... first dielectric part, 81b ... second dielectric part, 83 ... dielectric layer, 100 ... laminated structure, 100t ... recess, 110, 191, 192 ... semiconductor light emitting element, 411 ... first conductivity Layer, 411p ... peripheral portion, 412 ... second conductive layer

Claims (18)

A first semiconductor layer of a first conductivity type having a first surface and a second surface opposite to the first surface;
A second semiconductor layer of a second conductivity type provided on the second surface side of the first semiconductor layer;
A light emitting layer provided between the first semiconductor layer and the second semiconductor layer;
A dielectric layer in contact with the second surface and having a refractive index lower than that of the first semiconductor layer;
A first electrode having a first portion in contact with the second surface and provided adjacent to the dielectric layer, and a second portion in contact with the opposite side of the dielectric layer from the first semiconductor layer; A first electrode that does not overlap the second semiconductor layer when projected onto a plane parallel to the second surface;
A second electrode in contact with a side of the second semiconductor layer opposite to the light emitting layer;
A support substrate provided on the opposite side of the second electrode from the second semiconductor layer and electrically connected to the second electrode;
A semiconductor light emitting device comprising: The first portion extends in a first direction along the second surface;
2. The semiconductor light emitting element according to claim 1, wherein a length of the first portion in the first direction is longer than a length of a second direction perpendicular to the first direction.   3. The semiconductor light emitting element according to claim 2, wherein the length of the first portion in the second direction is shorter than the length of the second electrode in a portion in contact with the second semiconductor layer.   4. The semiconductor light emitting element according to claim 1, wherein an area of a portion of the second electrode that is in contact with the second semiconductor layer is larger than an area of the first electrode. The first electrode has an extending portion that does not overlap the first semiconductor layer when projected onto a plane parallel to the second surface,
5. The semiconductor light emitting element according to claim 1, further comprising a pad provided on a side opposite to the support substrate in the extended portion and in contact with the extended portion. The first portion extends in a first direction along the second surface from the pad side;
The semiconductor light emitting element according to claim 5, wherein a length of the pad in a second direction perpendicular to the first direction is longer than a length of the first electrode in the second direction. The dielectric layer is
The semiconductor light emitting element according to claim 1, further comprising a portion that covers the first electrode on a side of the first electrode opposite to the first semiconductor layer. The first electrode is
A first conductive layer having the first portion;
A second conductive layer having the second portion, contacting the opposite side of the first conductive layer from the first semiconductor layer, and comprising a material different from the first conductive layer;
The semiconductor light-emitting device according to claim 1, comprising:   The semiconductor light emitting element according to claim 8, wherein the dielectric layer is in contact with a side of the first conductive layer opposite to the first semiconductor layer. The first electrode is
A first conductive layer having the first portion and the second portion;
A second conductive layer in contact with the first conductive layer on the opposite side of the first conductive layer from the first semiconductor layer and comprising a material different from the material of the first conductive layer;
The semiconductor light-emitting device according to claim 1, comprising: The second electrode is
A contact portion in contact with the second semiconductor layer;
A bonding metal portion provided on the opposite side of the contact portion from the second semiconductor layer, in contact with the support substrate, and overlapping the first electrode when projected onto a plane parallel to the second surface;
The semiconductor light emitting device according to claim 1, comprising: The first semiconductor layer includes
The semiconductor light emitting element according to claim 1, further comprising uneven portions provided on the first surface and provided at a pitch equal to or greater than a peak wavelength of emitted light emitted from the light emitting layer. The first conductivity type is n-type,
The semiconductor light-emitting element according to claim 1, wherein the second conductivity type is a p-type.   14. The semiconductor light emitting element according to claim 1, wherein a material on at least a side of the second electrode in contact with the second semiconductor layer contains Ag.   The material on the side in contact with at least the second surface of the first electrode includes Ti, Au, Al, Ag, an alloy containing any one of these, or ITO. The semiconductor light emitting element as described in one. The semiconductor light emitting element according to claim 1, wherein the dielectric layer includes SiO ₂ , SiN, or SiON. The first semiconductor layer includes GaN;
The semiconductor light emitting element according to claim 1, wherein the second semiconductor layer contains GaN.   18. The semiconductor light emitting element according to claim 1, wherein a distance between the first electrode and the second semiconductor layer is wider than a film thickness of the dielectric layer.

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