KR20120002130A - Flip-chip light-emitting device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A flip-chip light-emitting device and a method of manufacturing the same are provided to improve the optical extraction efficiency of a light emitting device by reflecting light circulating inside the light emitting device outside. CONSTITUTION: In a flip-chip light-emitting device and a method of manufacturing the same, an N type semiconductor layer(1210), an active layer(1230), and a p-type semiconductor layer(1250) are formed on a transparent substrate(1100). A transparent electrode layer(1510) is formed on the p-type semiconductor layer. A P-type electrode pad(1550) is formed on the transparent electrode layer. An insulating layer(1390) is formed between the P-type electrode pad and n type electrode pads(1310,1330). Under bump metals(1410,1430,1450) are formed on the N type electrode and the P-type electrode pad.

Description

Flip chip type light emitting device and manufacturing method thereof {FLIP-CHIP LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device having a flip chip structure and a method of manufacturing the same. More specifically, a light emitting device for improving light emission efficiency and luminance in a light emitting device having a flip chip structure and a method of manufacturing the same. It is about.

A light-emitting diode (LED) refers to a device that makes a minority carrier (electron or hole) injected using a pn junction structure of a semiconductor and emits a predetermined light by recombination thereof. GaAs, AlGaAs, Various colors may be realized by configuring a light emitting source by changing compound semiconductor materials such as GaN, InGaN, and AlGaInP.

Such a light emitting device has a smaller power consumption and a longer life than conventional light bulbs or fluorescent lamps, can be installed in a narrow space, and exhibits strong vibration resistance. These light emitting devices are used as display devices and backlights, and because they have excellent characteristics in terms of power consumption reduction and durability, applications have recently been extended to large LCD-TV backlights, automobile headlights, and general lighting. It is necessary to improve the luminous efficiency of the device, solve the heat emission problem, and achieve high brightness and high output of the light emitting device.

In order to solve this problem, the interest in flip-chip type semiconductor light emitting devices is increasing day by day.

1 is a conceptual cross-sectional view for describing a light emitting device having a conventional flip chip structure.

Referring to FIG. 1, a light emitting device having a conventional flip chip structure generally uses metal organic chemical vapor deposition (MOCVD) on a sapphire substrate 10, and includes an N-type semiconductor layer 12, an active layer 14, and a P. FIG. After sequentially forming the type semiconductor layer 16, a portion of the P type semiconductor layer 16, the active layer 14, and the N type semiconductor layer 12 are etched by mesa etching to form a part of the N type semiconductor layer 12. After exposing, the transparent electrode layer 18 is formed on the P-type semiconductor layer 16, and subsequently, the P-type electrode pad 20 is formed.

The transparent electrode layer 18 is formed with a metal layer in ohmic contact with the P-type semiconductor layer 16. Generally, a material containing Ni and Au, or a translucent metal oxide such as NiO, ZnO, and ITO is used. Can be formed.

The N-type semiconductor layer 12 and the transparent metal layer 24 for ohmic contact may be formed on the exposed N-type semiconductor layer 12, and the N-type electrode pad 26 may be formed thereon.

Thereafter, a protective layer 29 may be formed between the P-type electrode pad 20 and the N-type electrode pad 26 by using a general insulator such as SiO ₂ to protect the light emitting device from external moisture or impact. .

In addition, the light emitting device manufactured as described above is flip-chip bonded on a sub-mount substrate (not shown) using the bumps 22 and 28 and the conductive adhesive, wherein the conductive adhesive is generally conductive particles, solder and thermosetting. And / or an insulating resin having thermoplasticity. Specifically, when the manufactured light emitting device is placed in the inverted position on the bump (not shown) of the lower sub-mount substrate and reflowed to a temperature above the melting point of the solder, light emission of the upper part is caused by the surface tension of the molten solder. The device self-aligns in position, and the electrode of the light emitting device and the electrode of the substrate are electrically connected according to the wettability of the solder.

Such a light emitting device having a conventional flip chip structure has high heat emission efficiency and high light efficiency, and thus has been widely applied to various small packages.

However, in the semiconductor light emitting device of the conventional flip chip structure, many photons generated in the active layer 14 do not easily escape to the outside of the light emitting device, and are heterogeneous at the interface between the sapphire substrate 10 and the N-type semiconductor layer 12. The difference in refractive index between the materials causes total reflection and can be absorbed and disappear. That is, there is a problem that the luminous efficiency of the electrical energy is converted into the light energy to escape to the outside of the device is low.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and solves the problem of reducing the light emitting area of the P-type semiconductor layer due to the conventional mesa etching, and the high reflection insulating layer on the portion where the light generated in the active layer is absorbed. It is to provide a flip-chip type light emitting device and a manufacturing method thereof having a higher light output efficiency than the prior art by increasing the light reflectivity by forming a.

Still another object of the present invention is to form a slope on the side surface of the light emitting device and then deposit a highly reflective insulating layer, thereby protecting the light emitting device from external moisture, impact, and the like, as well as protecting the light absorbed between the semiconductor layers to the outside. It is to provide a flip-chip type light emitting device having a further improved light efficiency characteristics by reflection and a method of manufacturing the same.

According to an aspect of the present invention, A first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer formed on the substrate; A trench formed from a top surface of the second conductive semiconductor layer to a predetermined depth of the first conductive semiconductor layer; And an insulating layer covering the side surface of the trench.

Preferably, the light emitting device is formed with at least two trenches.

Preferably, the light emitting device further includes a first electrode formed in a space inside the trench.

Preferably, the light emitting device is characterized in that the overall shape of the first electrode is T-shaped.

Preferably, the light emitting device is characterized in that the insulating layer is formed by alternately stacking a high refractive index layer and a low refractive index layer.

According to another aspect of the invention, providing a transparent substrate; Stacking a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on the substrate; Forming a trench by digging a groove from an upper surface of the second conductive semiconductor layer to a predetermined depth of the first conductive semiconductor layer; And forming an insulating layer covering the side surface of the trench.

According to another aspect of the invention, the substrate; 10. A semiconductor laminated structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer formed on the substrate, comprising: the semiconductor laminated structure having a side slope; And an insulating layer laminated on the side slope portions of the semiconductor laminate structure.

Preferably, the light emitting device further includes two or more first electrodes formed on the exposed upper surface of the first conductivity type semiconductor.

Preferably, the light emitting device further includes a first electrode formed in the trench formed from an upper surface of the second conductive semiconductor layer to a predetermined depth of the first conductive semiconductor layer.

Preferably, in the light emitting device, predetermined irregularities are formed on an interface between the first conductivity-type semiconductor and the substrate.

According to another aspect of the invention, the step of preparing a transparent substrate; Stacking a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate to form a semiconductor laminate structure; Etching side surfaces of the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer to form a side slope portion in the semiconductor stacked structure; And forming an insulating layer on the side inclined portion of the semiconductor stacked structure.

Preferably, the method of manufacturing the light emitting device includes the step of forming the insulating layer alternately stacking a high refractive index layer and a low refractive index layer.

According to the present invention, the light emitting area of the P-type semiconductor layer can be further increased, and light extraction efficiency of the light emitting device can be further improved by reflecting light circulated in the light emitting device to the outside.

In addition, according to the present invention, by reducing the amount of light absorbed and extinguished in the light emitting device, and reflecting it to the outside, it is possible to increase the light efficiency of the light emitting device.

1 is a view schematically showing the structure of a conventional flip chip type light emitting device.
2 is a view schematically showing the structure of a flip chip type light emitting device according to an embodiment of the present invention.
3 and 4 are views for explaining a process of manufacturing a light emitting device according to an embodiment of the present invention.
5 is a view schematically showing the structure of a flip chip type light emitting device according to another embodiment of the present invention.
6 to 8 are views for explaining a process of manufacturing a light emitting device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that the spirit of the invention to those skilled in the art can fully convey. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout the specification.

Hereinafter, a flip chip type light emitting device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 4.

The flip chip type light emitting device 1000 according to the exemplary embodiment of the present invention submounts the light emitting diodes of the N-type semiconductor layer 1210, the active layer 1230, and the P-type semiconductor layer 1250 formed on the transparent substrate 1100. It can be formed by flip chip bonding to the substrate 1800.

The transparent substrate 1100 may be, for example, a sapphire substrate having a refractive index of about 1.78.

Further, N-type semiconductor layer 1210 may be formed of N-type _{Al x In y Ga 1 -x- y} N (0≤x, y, x + y≤1), may include the N-type clad layer and, P-type semiconductor layer 1250 may be formed of P-type _{Al x in y Ga 1 -x- y} N (0≤x, y, x + y≤1), may include a P-type clad layer have.

In addition, Si, Ge, Se, Te, or C may be used for the doping of the N-type semiconductor layer 1210, and the dopant such as Zn, Mg, or Be may be added to the P-type semiconductor layer 1250. Can be formed.

These semiconductor layers 1210 and 1250 are sequentially grown on the substrate 1100 using known deposition processes such as organometallic vapor deposition (MOCVD), molecular beam growth (MBE), or hybrid vapor deposition (HVPE). Can be.

In addition, the P-type semiconductor layer 1250 may be formed on the P-type semiconductor layer 1250 by forming a transparent electrode layer 1510 formed of a metal or metal oxide such as Ni / Au, ITO, TCO, or NiO, ZnO. ) To increase the efficiency of current diffusion while maintaining the transmittance above a certain level by increasing ohmic contact. In addition, a high reflection insulating layer 1530 may be formed on a portion of the upper surface of the transparent electrode layer 1510, and a P-type electrode pad 1550 may be formed thereon. A method of forming the high reflection insulating layer 1530 will be described later.

Meanwhile, for example, two or more N-type electrode pads 1350 and 1370 may be formed. Referring to FIG. 2, the N-type electrode pads 1550 may be adjacent to both sides of the P-type electrode pad 1550. 1350 and 1370 are formed, and the P-type electrode pad 1550 and the N-type electrode pads 1350 and 1370 may be insulated by the insulating layer 1390. By forming the plurality of N-type electrode pads 1350 and 1370 as described above, current spreading may be improved.

In addition, the N-type electrode pads 1350 and 1370 are not formed on a part of the exposed N-type semiconductor layer even in the formation position (see FIG. 1), but are formed through the high reflection insulating layers 1310 and 1330. It may be formed on the semiconductor layer 1250.

In addition, the P-type electrode pads 1550 and the N-type electrode pads 1350 and 1370 are for electrical connection of devices, but are not limited thereto, but may include gold (Au), silver (Ag), and aluminum (Al). , Copper (Cu), or an alloy containing them.

That is, according to one embodiment of the present invention, the P-type semiconductor layer 1250, the active layer 1230 and the N-type semiconductor layer 1210 is etched to expose the upper surface of the N-type semiconductor layer 1210, and then N-type electrode pads 1350 and 1370 are not formed on the exposed upper surface of the N-type semiconductor layer 1210.

Specifically, as shown in FIG. 3, by dry etching, for example, from a top surface of the P-type semiconductor layer 1250 to a predetermined depth of the N-type semiconductor layer 1210, for example, about 5000 kPa to about 7000 At depth, trenches 1300 and 1300 ′ are formed to correspond to the number and formation positions of the N-type electrode pads 1350 and 1370. In this case, the side surfaces of the trenches 1300 and 1300 ′ may be formed in a vertical direction with respect to the upper surface of the P-type semiconductor layer 1250, but may be formed with a predetermined inclination.

Thereafter, as shown in FIG. 4, the highly reflective insulating layers 1310 and 1330 are deposited along the side surfaces of the trenches 1300 and 1300 ′ and a portion of the upper surface of the P-type semiconductor layer 1250. By forming the pad material in the interior spaces of the trenches 1300 and 1300 ', the N-type electrode pads 1350 and 1370 having a T-shape can be formed as a whole.

Here, the highly reflective insulating layers 1310 and 1330 may be formed of a DBR, as described below, and alternately stack approximately 17 insulating layers with a thickness of about 40 to 50 nm per layer, for example, about 7000 The highly reflective insulating layers 1310 and 1330 may be formed to have a thickness of about Å to about 10,000 Å. In addition, in forming the N-type electrode pads 1350 and 1370, a method such as deposition of an metal using a photo mask or e-beam deposition may be used. In this case, materials used to form the N-type electrode pads 1350 and 1370 include gold (Au), copper (Cu), aluminum (Al), silver (Ag), nickel (Ni), and indium (In). Or combinations thereof, oxides thereof, and the like.

Here, the highly reflective insulating layer 1530 formed on the transparent electrode layer 1510 and the highly reflective insulating layers 1310 and 1330 formed on the sides of the trenches 1300 and 1300 'have an insulating layer having a higher reflectance than Al or Ag. It may be formed as, for example may include at least one element selected from Si, Ti, Ta, Nb, In and Sn. In addition, the high reflection insulating layers 1310, 1330, and 1530 may be formed by alternately stacking at least two layers selected from Si _x O _y N _z , Ti _x O _y , Ta _x O _y, and Nb _x O _y . And a distributed Bragg reflector (DBR).

The distributed Bragg reflector can maximize the reflectance of light of a specific wavelength by controlling the optical thicknesses of the alternating high and low refractive index layers. Accordingly, by forming a distributed Bragg reflector with an optimized reflectance according to the wavelength of light generated in the active layer 1230, for example, a highly reflective insulating layer 1310, 1330, 1530 having a high reflectance for ultraviolet light, visible light or infrared light is formed. can do.

Meanwhile, the insulating layer 1390 formed between the P-type electrode pad 1550 and the N-type electrode pads 1310 and 1330 may also be formed in the same manner as the high reflection insulating layers 1310, 1330 and 1530, in which case The high reflection insulating layers 1310 and 1330 and the insulating layer 1390 may be formed through the same process. That is, as shown in FIG. 3, in the state where the trenches 1300 and 1300 ′ are formed, the transparent electrode layer 1510, the high reflection insulating layer 1530, and the P-type electrode pad 1550 are formed on the P-type semiconductor layer 1250. ) Is formed in order, and then the insulating layer 1390 is formed along the upper portion and side surfaces of the P-type electrode pad 1550, and the high reflection insulating layers 1310 and 1330 are formed on the side surfaces of the trenches 1300 and 1300 ′. Can be formed, for example, into a DBR using the same material. In this case, that is, by forming the insulating layer 1390 as a highly reflective insulating layer, the reflection area capable of reflecting light generated in the active layer 1230 and circulating inside the light emitting element can be widened, thereby improving light efficiency. Can be further improved.

Referring back to FIG. 2, the light emitting device 1000 corresponds to an under bump metal (UBM) 1410, 1430, and 1450 formed on the N-type electrode pads 1350 and 1370 and the P-type electrode pad 1550. Flip chip bonding is performed on the submount substrate 1800 by bonding between the under bump metals 1610, 1630, and 1650 formed on the submount substrate 1800. That is, the light emitting device 1000 may be electrically connected to the sub-mount substrate 1800 without additional adhesive material through a thermocompression flip chip method or a method of applying ultrasonic waves simultaneously with thermocompression. Solder (not shown) may be electrically connected between the bump metals 1410, 1430, and 1450 and the under bump metals 1610, 1630, and 1650.

The sub-mount substrate 1800 may have a good thermal conductivity, and may be a substrate made of a material having a similar thermal expansion coefficient to the semiconductor layers 1210 and 1250. Preferably, it is preferably formed containing Si, Mo, Cu, AlN, BeO, SiC, GaAs or W. In addition to the under bump metals 1610, 1630, and 1650, the sub-mount substrate 1800 may include a P electrode 1710 and an N electrode 1730 for supplying current and wire bonding to the outside.

Although not shown, a high reflection insulating layer is disposed on the upper surface of the sub-mount substrate 1800 except for the positions where the under bump metals 1610, 1630 and 1650, and the P-type and N-type electrodes 1710 and 1730 are formed. In addition, by forming and reflecting light toward the sub-mount substrate 1800 to be emitted to the outside of the light emitting device 1000, the luminous efficiency of the light emitting device can be further increased.

In addition, the under bump metals 1410, 1430, 1450, 1610, 1630, and 1650 may be formed of, for example, a material including gold, a stacked structure such as Ti / Pt / Au, or Ti / Au, Ni / Au and Pt / Au may be formed in any one stacked structure.

On the other hand, according to the present invention, although not shown, after separating the sapphire substrate 1100 by irradiating a laser to the interface between the sapphire substrate 1100 and the N-type semiconductor layer 1210 using a laser lift-off technique In addition, light extraction efficiency may be further improved by etching the upper surface of the exposed N-type semiconductor layer 1210 to form irregularities.

According to one embodiment of the present invention, by forming the high reflection insulating layer (1310, 1330, 1390, 1530), the light propagating inside the semiconductor laminate structure the semiconductor layer (1210, 1250) or electrode pad (1350, 1370, It is possible to prevent the absorption at 1550 and reflect the light to be emitted to the outside of the light emitting diode, and improve the light efficiency by shortening the optical path inside the semiconductor laminate.

Hereinafter, a flip chip type light emitting device according to another embodiment of the present invention will be described with reference to FIGS. 5 to 7. However, in order to simplify the description, overlapping descriptions of the same or corresponding parts as in the previous embodiment will be omitted.

As shown in FIG. 5, the light emitting device 2000 according to another exemplary embodiment of the present invention includes an N-type semiconductor layer 2210, an active layer 2230, and a P-type semiconductor layer 2250 formed on a transparent substrate 2100. Can be formed by flip chip bonding a sub-mount substrate 2800 to the submount substrate 2800.

Specifically, looking at the manufacturing method of the light emitting device 2000, for example, after the N-type semiconductor layer 2210, the active layer 2230 and the P-type semiconductor layer 2250 are sequentially formed on the sapphire substrate, N A portion of the N-type semiconductor layer 2210, the active layer 2230, and the P-type semiconductor layer 2250 are etched by mesa etching to expose a portion of the N-type semiconductor layer 2210.

In this case, as shown in FIG. 6, by forming a predetermined slope on the side of the semiconductor laminate structure during mesa etching, the width of the upper P-type semiconductor layer 2250 compared to the width of the lower N-type semiconductor layer 2210 This can make it narrower. By doing so, the high reflection insulating layer 2550, which will be described later, may be deposited on the side of the inclined semiconductor laminate structure, and the light may be reflected to the outside of the light emitting device by the high reflection insulating layer 2550 to increase light efficiency. Can be.

Next, the transparent electrode layer 2530 may be formed on the surface of the P-type semiconductor layer 2250, and the P-type electrode pad 2550 may be sequentially formed on the upper portion thereof. Here, the transparent electrode layer 2530 is made of a metal or metal oxide such as Ni / Au, ITO, TCO or NiO, ZnO, and ohmic contact with the P-type semiconductor layer 2250, thereby forming a low contact resistance between the semiconductor and the metal. The current spreading properties contribute to the smooth flow of current.

On the other hand, the transparent metal layers 2310 and 2330 for ohmic contacts may be formed on the upper surface of the N-type semiconductor layer 2210 exposed by the mesa etching, and the N-type electrode pads 2350 and 2370 may be formed thereon. . Here, unlike the conventional light emitting device, for example, two or more n-type electrode pads 2350 and 2370 may be formed. Referring to FIG. 5, adjacent to both sides of the P-type electrode pad 2550. N-type electrode pads 2350 and 2370 may be formed. By forming the plurality of N-type electrode pads 2350 and 2370 as described above, current spreading may be improved as compared with the conventional light emitting device.

Alternatively, only the active layer 2230 and the P-type semiconductor layer 2250 are partially etched by mesa etching, except for the N-type semiconductor layer 2210 so as to form a side slope of the semiconductor laminate structure, and then shown in FIG. 2. A trench as shown in the drawing may be formed, an insulating layer may be formed on sidewalls of the trench, and an N-type electrode pad may be formed in an inner space thereof.

Next, referring to FIG. 7, the P-type electrode pad 2550 and the N-type electrode pads 2350 and 2370 may be insulated using the high reflection insulating layer 2390. In this case, the high reflection insulating layer 2390 may serve as a reflective layer in addition to the conventional passivation layer, thereby contributing to the improvement of light extraction efficiency.

Here, the high reflection insulating layer 2390 may be formed of an insulating layer having a higher reflectance than Al or Ag, and may include, for example, at least one element selected from Si, Ti, Ta, Nb, In, and Sn. In addition, the high reflection insulating layer 2390 may be formed by alternately stacking at least two layers selected from Si _x O _y N _z , Ti _x O _y , Ta _x O _y, and Nb _x O _y , and distribution Bragg It may be a reflector DBR.

The distributed Bragg reflector can maximize the reflectance of light of a specific wavelength by controlling the optical thicknesses of the alternating high and low refractive index layers. Accordingly, by forming a distributed Bragg reflector with optimized reflectance according to the wavelength of light generated in the active layer 2230, a high reflection insulating layer 2390 having a high reflectance with respect to ultraviolet rays, visible rays, or infrared rays, for example, may be formed.

In addition, the highly reflective insulating layer 2390 exposes a portion of the upper portions of the N-type electrode pads 2350 and 2370 and the P-type electrode pad 2550 in consideration of the formation positions of the under bump metals 2410, 2430, and 2450. And can be formed.

Alternatively, although not shown, high reflection insulation is also performed on the upper surface of the sub-mount substrate 2800 except for the positions where the under bump metals 2610, 2630 and 2650 and the P-type and N-type electrodes 2710 and 2730 are formed. By further forming a layer to reflect light toward the sub-mount substrate 2800 and exiting the light emitting device 2000, the luminous efficiency of the light emitting device may be further increased.

Next, the under bump metals 2410, 2430, and 2450 formed on the light emitting diodes and the under bump metals 2610, 2630, and 2650 formed on the submount substrate 2800 may be aligned, and then flip chip bonded.

In this case, the sub-mount substrate 2800 may be selected to have a good thermal conductivity. Further, the sub-mount substrate 2800 may be formed of a material having a similar thermal expansion coefficient to those of the semiconductor layers 2210 and 2250. Preferably, it is preferably formed containing Si, Mo, Cu, AlN, BeO, SiC, GaAs or W. In addition to the under bump metals 2610, 2630, and 2650, the sub-mount substrate 2800 may include a P electrode 2710 and an N electrode 2730 to which external power is applied.

In addition, the under bump metals 2410, 2430, 2450, 2610, 2630, and 2650 may be made of, for example, a material including gold, and have a laminated structure such as Ti / Pt / Au, or Ti / Au, Ni / Au and Pt / Au may be formed in any one stacked structure. In this case, the under bump metals 2410, 2430 and 2450 and the under bump metals 2610, 2630 and 2650 may be joined by solder (not shown).

On the other hand, according to the present invention, after separating the sapphire substrate 2100 by irradiating a laser to the interface between the sapphire substrate 2100 and the N-type semiconductor layer 2210 using a laser lift-off technique, The light extraction efficiency may be further improved by etching the upper surface of the exposed N-type semiconductor layer 2210 to form irregularities. Specifically, it is also possible to increase the probability of photons coming out of the outside air by forming the bent in nano or micro units on the exposed surface of the N-type semiconductor layer 2210 by dry or wet etching.

According to another embodiment of the present invention, the side surface of the light emitting diode is formed to be inclined and the high reflection insulating layer 2390 is formed on the inclined surface to prevent the light traveling inside the semiconductor laminate from being absorbed by the semiconductor layer or the electrode pad. And by reflecting this can be emitted to the outside of the light emitting diode, it is possible to improve the light efficiency by shortening the optical path inside the semiconductor laminate structure.

While some embodiments of the present invention have been described above by way of example, those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential features of the present invention. Therefore, the embodiments described above should not be construed as limiting the technical spirit of the present invention but merely for better understanding. The scope of the present invention is not limited by these embodiments, and should be interpreted by the following claims, and the technical spirit equivalent to the scope of the present invention should be construed as being included in the scope of the present invention.

10: sapphire substrate 12: N-type semiconductor layer
14: active layer 16: P-type semiconductor layer
18: transparent electrode layer 20: P-type electrode pad
24: n-metal contact layer 26: N-type electrode pad
22, 28 bump 29: insulation layer
1100 and 2100: Sapphire substrates 1210 and 2210: N-type semiconductor layer
1230 and 2230: active layers 1250 and 2250: P-type semiconductor layers
1300, 1300 ': Trench 1330, 1530, 2390: Highly reflective insulating layer
1710, 2710: p-electrode 1730, 1230: n-electrode
1800, 2800: submount substrate

Claims (12)

Board;
A first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer formed on the substrate;
A trench formed from a top surface of the second conductive semiconductor layer to a predetermined depth of the first conductive semiconductor layer; And
Light-emitting device comprising an insulating layer covering the side of the trench. The method according to claim 1,
At least two trenches are formed. The method according to claim 2,
The light emitting device further comprises a first electrode formed in the space inside the trench. The method according to claim 3,
The overall shape of the first electrode is a light emitting device, characterized in that the T-shape. The method according to claim 1,
The insulation layer is formed by alternately stacking a high refractive index layer and a low refractive index layer. Preparing a transparent substrate;
Stacking a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer on the substrate;
Forming a trench by digging a groove from an upper surface of the second conductive semiconductor layer to a predetermined depth of the first conductive semiconductor layer; And
Forming an insulating layer covering the side of the trench manufacturing method of a light emitting device. Board;
10. A semiconductor laminated structure comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer formed on the substrate, comprising: the semiconductor laminated structure having a side slope; And
And an insulating layer laminated on the side inclined portions of the semiconductor laminate. The method according to claim 7,
And at least two first electrodes formed on the exposed top surface of the first conductivity type semiconductor. The method according to claim 7,
And a first electrode formed in a trench formed from an upper surface of the second conductive semiconductor layer to a predetermined depth of the first conductive semiconductor layer. The method according to claim 7,
The light emitting device according to claim 1, wherein predetermined irregularities are formed on an interface between the first conductive semiconductor and the substrate. Preparing a transparent substrate;
Stacking a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate to form a semiconductor laminate structure;
Etching side surfaces of the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer to form a side slope portion in the semiconductor stacked structure; And
And forming an insulating layer on the side inclined portion of the semiconductor laminate. The method according to claim 11
Forming the insulating layer comprises a step of alternately stacking a high refractive index layer and a low refractive index layer.

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