JP7354088B2 - 半導体素子及びその製造方法 - Google Patents
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
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- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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Description
前記第1層は前記第1金属元素と酸素を含み、前記第2層は前記第2金属元素と酸素を含み、前記誘電膜と接する前記下部電極の第1接触面は前記第2層である。
30 誘電膜
50 上部電極
IF 界面
CS1,CS2 接触面
Claims (20)
- 基板と、
前記基板上のキャパシタと、を含み、
前記キャパシタは、前記基板上に順に積層される下部電極、誘電膜、及び上部電極を含み、
前記下部電極は、ABO3を含み、前記Aは、第1金属元素であり、前記Bは、前記第1金属元素より仕事関数が大きい第2金属元素であり、
前記誘電膜は、CDO3を含み、前記Cは、第3金属元素であり、前記Dは、第4金属元素であり、
前記下部電極は、第1層と第2層が交互に繰り返され、前記第1層は、前記第1金属元素と酸素を含み、前記第2層は、前記第2金属元素と酸素を含み、
前記誘電膜と接する前記下部電極の第1接触面は前記第2層である、半導体素子。 - 前記第1接触面は、{100}結晶面である、請求項1に記載の半導体素子。
- 前記下部電極及び前記誘電膜は、各々ペロブスカイト構造を有する、請求項1又は2に記載の半導体素子。
- 前記誘電膜は、第3層と第4層が交互に繰り返され、前記第3層は、前記第3金属元素と酸素を含み、前記第4層は、前記第4金属元素と酸素を含み、
前記下部電極と接する前記誘電膜の第2接触面は、前記第3層である、請求項1乃至3のいずれか一項に記載の半導体素子。 - 前記第4金属元素は、前記第3金属元素より仕事関数が大きい、請求項4に記載の半導体素子。
- 前記第2金属元素は、前記第4金属元素より仕事関数が大きい、請求項1に記載の半導体素子。
- 前記第2金属元素の仕事関数は、4.5eVより大きく6eVより小さい、請求項1に記載の半導体素子。
- 前記第1金属元素は、Sr、Ba、La、及びCaの中の少なくとも1つである、請求項1に記載の半導体素子。
- 前記第2金属元素は、Ru、Mo、Ir、Co、及びNiの中の少なくとも1つである、請求項1に記載の半導体素子。
- 前記第3金属元素は、Ba、Sr、及びCaの中の少なくとも1つである、請求項1に記載の半導体素子。
- 前記第4金属元素は、Ti、Zr、及びHfの中の少なくとも1つである、請求項1に記載の半導体素子。
- 前記下部電極の厚さは、約50Å乃至約100Åである、請求項1に記載の半導体素子。
- 前記キャパシタは、ベース電極をさらに含み、
前記下部電極は、前記ベース電極の側壁及び上面を覆う、請求項1に記載の半導体素子。 - 基板と、
前記基板上のキャパシタと、を含み、
前記キャパシタは、前記基板上に順に積層される下部電極、誘電膜、及び上部電極を含み、
前記下部電極の上面が、前記誘電膜の下面に接触しており、
前記下部電極は、第1金属元素、第2金属元素、及び酸素を含み、
前記誘電膜は、第3金属元素、第4金属元素、及び酸素を含み、
前記下部電極は、第1層と第2層が交互に繰り返され、前記第1層は、前記第1金属元素と酸素を含み、前記第2層は、前記第2金属元素と酸素を含み、
前記第1金属元素は、Sr、Ba、La、及びCaの中の少なくとも1つであり、前記第2金属元素は、Ru、Mo、Ir、Co、及びNiの中の少なくとも1つであり、
前記誘電膜と接する前記下部電極の第1接触面は、前記第2層である、半導体素子。 - 前記誘電膜は、第3層と第4層が交互に繰り返され、前記第3層は、前記第3金属元素と酸素を含み、前記第4層は、前記第4金属元素と酸素を含み、
前記下部電極と接する前記誘電膜の第2接触面は、前記第3層と前記第4層の中で仕事関数が小さい層である、請求項14に記載の半導体素子。 - 前記第3金属元素は、Ba、Sr、及びCaの中の少なくとも1つであり、
前記第4金属元素はTi、Zr、及びHfの中の少なくとも1つである、請求項14に記載の半導体素子。 - 前記キャパシタは、ベース電極をさらに含み、
前記下部電極は、前記ベース電極の側壁及び上面を覆う、請求項14に記載の半導体素子。 - 基板の上部に埋め込まれ、第1方向に延長される第1導電ラインと、
素子分離膜によって前記基板の上部に定義され、前記第1導電ラインを介して分離された第1不純物領域及び第2不純物領域を含む活性領域と、
前記基板上で前記第1方向と交差する第2方向に延長され、前記第1不純物領域と連結される第2導電ラインと、
前記第2不純物領域に連結されるコンタクトと、
前記コンタクトを通じて前記第2不純物領域に連結され、前記基板上にあるキャパシタと、を含み、
前記キャパシタは、前記基板上に順に積層される下部電極、誘電膜、及び上部電極を含み、
前記下部電極は、ABO3を含み、前記Aは、第1金属元素であり、前記Bは、前記第1金属元素より仕事関数が大きい第2金属元素であり、
前記誘電膜は、CDO3を含み、前記Cは、第3金属元素であり、前記Dは、第4金属元素であり、
前記下部電極は、第1層と第2層が交互に繰り返され、前記第1層は、前記第1金属元素と酸素を含み、前記第2層は、前記第2金属元素と酸素を含み、
前記誘電膜と接する前記下部電極の第1接触面は、前記第2層である、半導体素子。 - 前記誘電膜は、第3層と第4層が交互に繰り返され、前記第3層は、前記第3金属元素と酸素を含み、前記第4層は、前記第4金属元素と酸素を含み、
前記第4金属元素は、前記第3金属元素より仕事関数が大きい、請求項18に記載の半導体素子。 - 前記第1金属元素は、Sr、Ba、La、及びCaの中の少なくとも1つであり、
前記第2金属元素は、Ru、Mo、Ir、Co、及びNiの中の少なくとも1つであり、
前記第3金属元素は、Ba、Sr、及びCaの中の少なくとも1つであり、
前記第4金属元素は、Ti、Zr、及びHfの中の少なくとも1つである、請求項18に記載の半導体素子。
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KR10-2019-0174171 | 2019-12-24 | ||
KR1020190174171A KR20210082310A (ko) | 2019-12-24 | 2019-12-24 | 반도체 소자 및 그의 제조 방법 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000269424A (ja) | 1999-03-17 | 2000-09-29 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001284542A (ja) | 2000-03-30 | 2001-10-12 | Seiko Epson Corp | 強誘電体メモリ素子 |
US20170018604A1 (en) | 2015-07-15 | 2017-01-19 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor device |
US20170352666A1 (en) | 2016-06-02 | 2017-12-07 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
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JPH07111318A (ja) | 1993-10-12 | 1995-04-25 | Olympus Optical Co Ltd | 強誘電体メモリ |
KR100230418B1 (ko) * | 1997-04-17 | 1999-11-15 | 윤종용 | 백금족 금속층 형성방법 및 이를 이용한 커패시터 제조방법 |
JP2001077326A (ja) | 1999-08-31 | 2001-03-23 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2003243536A (ja) | 2002-02-15 | 2003-08-29 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2003264188A (ja) | 2002-03-12 | 2003-09-19 | Matsushita Electric Ind Co Ltd | 成膜方法 |
US8049423B2 (en) * | 2008-07-25 | 2011-11-01 | Samsung Sdi Co., Ltd. | Plasma display panel with improved luminance and low power consumption |
US20100068509A1 (en) | 2008-09-17 | 2010-03-18 | Nanochip, Inc. | Media having improved surface smoothness and methods for making the same |
US10074505B2 (en) | 2016-01-14 | 2018-09-11 | Wisconsin Alumni Research Foundation | Perovskites as ultra-low work function electron emission materials |
EP3501038B1 (en) | 2016-08-16 | 2021-12-01 | Ramot at Tel-Aviv University Ltd. | Heterostructure system and method of fabricating the same |
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Patent Citations (4)
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JP2000269424A (ja) | 1999-03-17 | 2000-09-29 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001284542A (ja) | 2000-03-30 | 2001-10-12 | Seiko Epson Corp | 強誘電体メモリ素子 |
US20170018604A1 (en) | 2015-07-15 | 2017-01-19 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor device |
US20170352666A1 (en) | 2016-06-02 | 2017-12-07 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
Non-Patent Citations (1)
Title |
---|
YEONG JAE SHIN, et al.,Interface Control of Ferroelectricity in an SrRuO3/BaTiO3/SrRuO3 Capacitor and its Critical Thickness,ADVANCED MATERIALS,2017年,Vol.29 No.1602795,p.1-6 |
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JP2021103772A (ja) | 2021-07-15 |
EP3843164A1 (en) | 2021-06-30 |
KR20210082310A (ko) | 2021-07-05 |
US20240030277A1 (en) | 2024-01-25 |
US20210193457A1 (en) | 2021-06-24 |
CN113036037A (zh) | 2021-06-25 |
US11804518B2 (en) | 2023-10-31 |
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