JP7210682B2 - 材料構造を改良するための処理 - Google Patents
材料構造を改良するための処理 Download PDFInfo
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- JP7210682B2 JP7210682B2 JP2021186256A JP2021186256A JP7210682B2 JP 7210682 B2 JP7210682 B2 JP 7210682B2 JP 2021186256 A JP2021186256 A JP 2021186256A JP 2021186256 A JP2021186256 A JP 2021186256A JP 7210682 B2 JP7210682 B2 JP 7210682B2
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Description
102 ファクトリインターフェース
104 ロードロックチャンバ
106 ロードロックチャンバ
108 移送チャンバ
110 移送チャンバ
112 移送ロボット
114 移送ロボット
116 チャンバ
118 チャンバ
120 処理チャンバ
122 処理チャンバ
124 処理チャンバ
126 処理チャンバ
128 処理チャンバ
130 処理チャンバ
140 ステーション
142 ファクトリインターフェースロボット
144 前方開口式一体型ポッド(FOUP)
148 ブレード
150 ポート
152 それぞれのポート
154 ポート
156 ポート
158 ポート
160 ポート
162 ポート
164 ポート
166 ポート
168 ポート
170 ポート
172 ポート
174 ポート
176 ポート
190 システムコントローラ
192 中央処理装置(CPU)
194 メモリ
196 サポート回路
200 方法
210 ブロック
220 ブロック
230 ブロック
240 ブロック
250 ブロック
260 ブロック
270 ブロック
280 ブロック
290 ブロック
300 半導体構造
302 基板
304 界面層
306 ゲート誘電体層
400 方法
410 ブロック
420 ブロック
430 ブロック
440 ブロック
450 ブロック
460 ブロック
480 ブロック
500 金属ゲート構造
502 誘電体キャップ層
504 犠牲シリコンキャップ層
506 金属層
Claims (25)
- 半導体構造を形成する方法であって、前記方法が、
基板上に形成された半導体構造上に高誘電率誘電体キャップ層を形成することを含み、前記高誘電率誘電体キャップ層を形成することが、
前記半導体構造上に前記高誘電率誘電体キャップ層を堆積させること、
前記高誘電率誘電体キャップ層上に犠牲シリコンキャップ層を堆積させること、
堆積直後の状態の前記高誘電率誘電体キャップ層を硬化および高密度化するように、キャップ後アニールプロセスを実行すること、ならびに
前記犠牲シリコンキャップ層を除去すること、
を含む、方法。 - 前記高誘電率誘電体キャップ層を形成することが、真空を破壊することなく処理システム内で実行される、請求項1に記載の方法。
- 前記基板上に前記半導体構造を形成することを、さらに含み、前記半導体構造を形成することが、
前記基板の表面を前洗浄すること、
前記基板の前洗浄された前記表面上に界面層を形成すること、
前記界面層上に高誘電率ゲート誘電体層を堆積させること、
堆積された前記高誘電率ゲート誘電体層内に窒素原子を挿入するように、プラズマ窒化プロセスを実行すること、および
プラズマ窒化された前記高誘電率ゲート誘電体層内の化学結合を不動態化するように、窒化後アニールプロセスを実行すること、
を含む、請求項1に記載の方法。 - 前記界面層が、酸化ケイ素(SiO2)を含み、
前記界面層を形成することが、亜酸化窒素(N2O)ガスを利用して前記基板を熱酸化することを含む、請求項3に記載の方法。 - 前記高誘電率ゲート誘電体層が、酸化ハフニウム(HfO2)を含む、請求項3に記載の方法。
- 前記プラズマ窒化プロセスが、堆積された前記高誘電率ゲート誘電体層を、窒素(N2)およびアンモニア(NH3)ガスの混合物を使用した窒素プラズマに曝すことを含む、請求項3に記載の方法。
- 前記窒化後アニールプロセスが、堆積された前記高誘電率ゲート誘電体層を、700℃から850℃の間の温度で、窒素(N2)およびアルゴン(Ar)雰囲気中でスパイクアニールすることを含む、請求項3に記載の方法。
- 堆積された前記高誘電率ゲート誘電体層を硬化および高密度化するように、前記プラズマ窒化プロセスの前に堆積後アニールプロセスを実行することを、さらに含み、前記堆積後アニールプロセスが、堆積された前記高誘電率ゲート誘電体層を、500℃から800℃の間の温度で、窒素(N2)およびアルゴン(Ar)雰囲気中でアニールすることを含む、請求項3に記載の方法。
- プラズマ窒化された前記高誘電率ゲート誘電体層内に窒素原子をさらに挿入するように、前記窒化後アニールプロセスの前に熱窒化プロセスを実行することを、さらに含み、前記熱窒化プロセスが、プラズマ窒化された前記高誘電率ゲート誘電体層を、700℃から900℃の間の温度で、アンモニア(NH3)雰囲気中でアニールすることを含む、請求項3に記載の方法。
- 前記高誘電率誘電体キャップ層が、TiSiNを含む、請求項1に記載の方法。
- 堆積直後の状態の前記高誘電率誘電体キャップ層を、700℃から850℃の間の温度で、窒素(N2)雰囲気中で硬化および高密度化するように、前記犠牲シリコンキャップ層の堆積の前に金属キャップアニールプロセスを実行することを、さらに含む、請求項1に記載の方法。
- 前記キャップ後アニールプロセスが、前記高誘電率誘電体キャップ層を、900℃から1000℃の間の温度で、窒素(N2)雰囲気中でアニールすることを含む、請求項1に記載の方法。
- 半導体構造を形成する方法であって、前記方法が、
基板上に形成された半導体構造上に高誘電率誘電体キャップ層を形成することを含み、前記高誘電率誘電体キャップ層を形成することが、
前記半導体構造上に前記高誘電率誘電体キャップ層を堆積させること、
前記高誘電率誘電体キャップ層上に犠牲シリコンキャップ層を堆積させること、
堆積直後の状態の前記高誘電率誘電体キャップ層を硬化および高密度化するように、キャップ後アニールプロセスを実行すること、ならびに
前記犠牲シリコンキャップ層を除去すること、
を含む、方法。 - 前記高誘電率誘電体キャップ層を形成することが、真空を破壊することなく処理システム内で実行される、請求項13に記載の方法。
- 前記基板上に前記半導体構造を形成することを、さらに含み、前記半導体構造を形成することが、
前記基板の表面を前洗浄すること、
前記基板上に高誘電率ゲート誘電体層を堆積させること、および
堆積された前記高誘電率ゲート誘電体層内に窒素原子を挿入するように、プラズマ窒化プロセスを実行すること、
を含む、請求項13に記載の方法。 - 亜酸化窒素(N2O)ガスを利用して前記基板を熱酸化することを含む、前記基板の前洗浄された前記表面上に界面層を形成することを、さらに含み、前記界面層が、酸化ケイ素(SiO2)を含む、請求項15に記載の方法。
- 前記高誘電率ゲート誘電体層が、酸化ハフニウム(HfO2)を含む、請求項15に記載の方法。
- 前記プラズマ窒化プロセスが、堆積された前記高誘電率ゲート誘電体層を、窒素(N2)およびアンモニア(NH3)ガスの混合物を使用した窒素プラズマに曝すことを含む、請求項15に記載の方法。
- 前記基板を熱酸化するように、前記プラズマ窒化プロセスの前に再酸化プロセスを実行すること、および
プラズマ窒化された前記高誘電率ゲート誘電体層内の化学結合を不動態化するように、前記プラズマ窒化プロセスに続いて窒化後アニールプロセスを実行すること、
をさらに含み、
前記再酸化プロセスが、前記高誘電率ゲート誘電体層を、400℃から900℃の間の温度で、酸素(O2)、亜酸化窒素(N2O)、およびH2雰囲気中でアニールすることを含み、
前記窒化後アニールプロセスが、プラズマ窒化された前記高誘電率ゲート誘電体層を、700℃から850℃の間の温度で、窒素(N2)およびアルゴン(Ar)雰囲気中でスパイクアニールすることを含む、請求項15に記載の方法。 - プラズマ窒化された前記高誘電率ゲート誘電体層内の残りの化学結合を不動態化し、前記基板を熱酸化するように、前記プラズマ窒化プロセスに続いて再酸化プロセスを実行することを、さらに含み、前記再酸化プロセスが、前記高誘電率ゲート誘電体層を、400℃から900℃の間の温度で、酸素(O2)、亜酸化窒素(N2O)、およびH2雰囲気中でアニールすることを含む、請求項15に記載の方法。
- 前記高誘電率誘電体キャップ層が、TiSiNを含む、請求項13に記載の方法。
- 堆積直後の状態の前記高誘電率誘電体キャップ層を、700℃から850℃の間の温度で、窒素(N2)雰囲気中で硬化および高密度化するように、前記犠牲シリコンキャップ層の堆積の前に金属キャップアニールプロセスを実行することを、さらに含む、請求項13に記載の方法。
- 前記キャップ後アニールプロセスが、前記高誘電率誘電体キャップ層を、900℃から1000℃の間の温度で、窒素(N2)雰囲気中でアニールすることを含む、請求項13に記載の方法。
- 第1の処理チャンバ、
第2の処理チャンバ、
第3の処理チャンバ、
第4の処理チャンバ、および
システムコントローラ、
を備える処理システムであって、前記システムコントローラが、
前記第1の処理チャンバ内で、高誘電率誘電体キャップ層を、基板上に形成された半導体構造上に堆積させること、
前記第2の処理チャンバ内で、前記高誘電率誘電体キャップ層上に犠牲シリコンキャップ層を堆積させること、
前記第3の処理チャンバ内で、堆積直後の状態の前記高誘電率誘電体キャップ層を硬化および高密度化するように、キャップ後アニールプロセスを実行すること、ならびに
前記第4の処理チャンバ内で、前記犠牲シリコンキャップ層を除去すること、
を行うように構成されており、
前記基板が、前記処理システム内の真空環境を破壊することなく、前記第1の処理チャンバ、前記第2の処理チャンバ、前記第3の処理チャンバ、および前記第4の処理チャンバの間で移送される、処理システム。 - 前記処理システムが、
第5の処理チャンバ、
第6の処理チャンバ、
第7の処理チャンバ、
第8の処理チャンバ、および
第9の処理チャンバ、
をさらに備え、
前記システムコントローラが、さらに、
前記第5の処理チャンバ内で、前記基板の表面を前洗浄すること、
前記第6の処理チャンバ内で、前記基板の前洗浄された前記表面上に界面層を形成すること、
前記第7の処理チャンバ内で、前記界面層上に高誘電率ゲート誘電体層を堆積させること、
堆積された前記高誘電率ゲート誘電体層を、前記第8の処理チャンバ内で、窒素プラズマに曝すこと、および
プラズマ窒化された前記高誘電率ゲート誘電体層を、前記第9の処理チャンバ内で、アニールすること、
を行うように構成されており、
前記基板が、前記処理システム内の真空環境を破壊することなく、前記第5の処理チャンバ、前記第6の処理チャンバ、前記第7の処理チャンバ、前記第8の処理チャンバ、および前記第9の処理チャンバの間で移送される、請求項24に記載の処理システム。
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