JP7178950B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7178950B2 JP7178950B2 JP2019079495A JP2019079495A JP7178950B2 JP 7178950 B2 JP7178950 B2 JP 7178950B2 JP 2019079495 A JP2019079495 A JP 2019079495A JP 2019079495 A JP2019079495 A JP 2019079495A JP 7178950 B2 JP7178950 B2 JP 7178950B2
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Description
実施の形態の説明に先立ってVDMOSの動作について、図1~図4を用いて説明する。図1は一般的なVDMOSの等価回路図である。図1に示すようにMOSトランジスタM1のドレイン端子DTとソース端子STとの間には、寄生npnトランジスタPT(寄生トランジスタ)が存在している。寄生npnトランジスタPTのベース電極は、MOSトランジスタM1のバックゲートに接続されている。また、MOSトランジスタM1のバックゲートとドレイン端子DTとの間には寄生ダイオードPDが存在している。
<装置構成>
図8は、本発明に係る実施の形態1の半導体装置100の構成を示す断面図である。図8に示すように半導体装置100は、n型不純物を比較的高濃度(n+)に含むn型(第1導電型)の基板1(第1の半導体層)の一方の主面上(第1の主面)に、n型不純物を基板1よりも低濃度(n-)に含むn型のエピタキシャル層2(第2の半導体層)が形成され、エピタキシャル層2の上層部に、p型(第2導電型)の不純物領域3a(第1の不純物領域)が形成されている。また、不純物領域3aの上層部には、n型の不純物領域4(第2の不純物領域)が形成されている。また、不純物領域3aおよびエピタキシャル層2上に跨るように、ゲート絶縁膜OXを間に介してゲート電極5が設けられ、不純物領域4上にはソース電極6(第1の主電極)が接続されている。ソース電極6が設けられた側とは反対側の基板1の他方の主面(第2の主面)上にはドレイン電極7(第2の主電極)が設けられている。
次に、半導体装置100の動作について、図11~図13を用いて説明する。なお、図11~図13では、便宜的に寄生npnトランジスタは省略している。
図12においては、ドレイン端子DTの相対電位がα-Vとなり、バックゲートの相対電位が0Vとなり、ゲート端子GTおよびソース端子STの相対電位がαとなっている。
従って、MOSトランジスタがオンするための電圧Vの条件は以下の数式(3)で表すことができる。
ここで、数式(3)の右辺第2項は小さいほうがより条件が厳しいため、数式(1)を使ってαをVで置き換えると、以下の数式(4)で表すことができる。
よって、数式(1)より、αは以下の数式(5)で表すことができる。
このようにドレイン電圧Vdが-Vthより低くなるとMOSトランジスタが自動的にオン状態となり、半導体装置100のチャネルを介して電流が流れるので、寄生ダイオードPDが順バイアスされて電流が流れる場合に比べて、不純物領域3aからエピタキシャル層2へのホール注入が抑制される。
図14は、本発明に係る実施の形態2の半導体装置100Aの構成を示す断面図である。図14に示すように半導体装置100Aにおいては、ソース電極6の下部において不純物領域4が部分的に設けられていない領域が存在し、そこには不純物領域3aが存在し、不純物領域3aにソース電極6が直接に接している。なお、図14においては、図8を用いて説明した半導体装置100と同一の構成については同一の符号を付し、重複する説明は省略する。
図20は、本発明に係る実施の形態3の半導体装置100Bの構成を示す断面図である。図20に示すように半導体装置100Bにおいては、ソース電極61が不純物領域3aとの間でショットキー接合を形成するショットキー電極で構成されており、ソース電極61が不純物領域3aに直接に接する構成となっている。
図25は、本発明に係る実施の形態4の半導体装置100Cの構成を示す断面図である。図25に示すように半導体装置100Cにおいては、ソース電極6の下部において不純物領域4が部分的に設けられていない領域が存在し、そこには不純物領域3aが存在し、不純物領域3a上に不純物領域3aよりもバンドギャップの狭い材料で構成され、n型不純物を含む狭バンドギャップ層9が設けられている。なお、狭バンドギャップ層9のn型不純物の不純物濃度は不純物領域4よりも高い方が好ましい。そして、狭バンドギャップ層9に接すると共に、不純物領域4に接するようにソース電極6が設けられている。なお、狭バンドギャップ層9が不純物領域4にも接するように設けられるのであれば、ソース電極6は不純物領域4に接していない構成であっても良い。
図28は、本発明に係る実施の形態5の半導体装置100Dの構成を示す断面図である。図28に示すように半導体装置100Dにおいては、不純物領域3a内において、不純物領域4に挟まれるようにp型不純物を含む不純物領域3b(第3の不純物領域)を設け、不純物領域3bと不純物領域4との間のpn接合を利用して、低耐圧の電圧クランプ用ダイオードを形成している。なお、不純物領域3bの不純物濃度は不純物領域3aよりも高濃度としている。なお、不純物領域3bのp型不純物の不純物濃度は不純物領域3aよりも高い方が好ましい。
図31は、本発明に係る実施の形態6の半導体装置100Eの構成を示す断面図である。図31に示すように半導体装置100Eにおいては、不純物領域3a内において、不純物領域4に囲まれるようにp型不純物を含む不純物領域8(第3の不純物領域)を設け、不純物領域3aと不純物領域4とのpn接合で形成されるpn接合ダイオードの接合容量を大きくしている。なお、図示は省略するが、不純物領域8の下の不純物領域4を部分的に除去して、不純物領域8が不純物領域3aに接する部分を設けている。
図34は、本発明に係る実施の形態7の半導体装置100Fの構成を示す断面図である。図34に示すように半導体装置100Fにおいては、図8に示した実施の形態1の
半導体装置100にMOS容量を加えた構成となっている。
図36は、本発明に係る実施の形態8の半導体装置100Gの構成を示す断面図である。図36に示すように半導体装置100Gは、図8に示した実施の形態1の半導体装置100において、不純物領域3aの上層部に、ソース電極6が接続された不純物領域4(第1の領域)とは別に不純物領域4(第2の領域)を設け、当該不純物領域4上から不純物領域3a上に跨るようにショート電極13を設けている。なお、ショート電極13は不純物領域4と不純物領域3aとをショートするために設けられている。
図38は、本発明に係る実施の形態9の半導体装置100Hの構成を示す断面図である。図38に示すように半導体装置100Hは、図8に示した実施の形態1の半導体装置100において、不純物領域3aの上層部に、ソース電極6が接続された不純物領域4(第1の領域)とは別に不純物領域4(第2の領域)を設け、当該不純物領域4上から不純物領域3a上に跨るようにショート電極13を設けている。そして、2つの不純物領域4の端縁部間に跨るように、ゲート絶縁膜OXを間に介してゲート電極5が形成されることで、MOSトランジスタが付加されている。なお、付加されたMOSトランジスタのゲート電極5は、半導体装置100Hのゲート電極5とショートされている。
図39は、本発明に係る実施の形態10の半導体装置100Iの構成を示す断面図である。図39に示す半導体装置100Iは、図8に示した実施の形態1の半導体装置100をトレンチ型の半導体装置に適用したものである。
Claims (12)
- 第1導電型の第1の半導体層と、
前記第1の半導体層の第1の主面上に設けられ、第1導電型の不純物濃度が前記第1の半導体層よりも低い第1導電型の第2の半導体層と、
前記第2の半導体層の上層部に設けられ、第2導電型の第1の不純物領域と、
前記第1の不純物領域の上層部に設けられ、第1導電型の第2の不純物領域と、
少なくとも前記第1の不純物領域と前記第2の半導体層にゲート絶縁膜を間に介して対向するように設けられたゲート電極と、
少なくとも一部が前記第2の不純物領域に接続され、前記第1の不純物領域とは直接には接しないように設けられる第1の主電極と、
前記第1の主電極が設けられた側とは反対側の前記第1の半導体層の第2の主面に接続される第2の主電極と、を備えたMOSトランジスタと、
前記第2の不純物領域をエミッタとし、前記第1の半導体層および前記第2の半導体層をコレクタとし、前記第1の不純物領域をベースとして構成される寄生トランジスタと、
前記第1の不純物領域をアノードとし、前記第1の半導体層および前記第2の半導体層をカソードとして構成される寄生ダイオードと、
前記第1の不純物領域をアノードとし、前記第2の不純物領域をカソードとして構成されるpn接合ダイオードと、を有し、
前記寄生トランジスタのエミッタ電流に対するコレクタ電流の比が1/1000以下であり、
前記pn接合ダイオードの接合耐圧が前記MOSトランジスタをオンさせるゲート電圧のしきい値以上である、半導体装置。 - 前記第1の主電極は、
前記第1の不純物領域と抵抗を介して接続される接続部を有するように設けられる、請求項1記載の半導体装置。 - 前記第1の主電極の前記接続部は、
前記第1の主電極と前記第1の不純物領域とが直接に接し、
前記抵抗はコンタクト抵抗で構成される、請求項2記載の半導体装置。 - 前記第1の主電極と、
前記第1の不純物領域との間に設けられたMOS容量をさらに有する、請求項1記載の半導体装置。 - 前記第2の不純物領域は、
前記第1の主電極が接続される第1の領域と、
前記第1の領域とは離れて設けられた第2の領域と、を有し、
前記第2の領域上および前記第1の不純物領域上に設けられ、前記第2の領域と前記第1の不純物領域とをショートするショート電極をさらに備える、請求項1記載の半導体装置。 - 前記ゲート電極は、
前記第1および第2の領域の端縁部間にも前記ゲート絶縁膜を間に介して設けられる、請求項5記載の半導体装置。 - 前記ゲート電極は、
前記第1および第2の不純物領域の側面に接し、前記第1の不純物領域の底面を超える深さに達するように前記第2の半導体層に設けられたトレンチ内に、前記ゲート絶縁膜を間に介して設けられる、請求項1記載の半導体装置。 - 第1導電型の第1の半導体層と、
前記第1の半導体層の第1の主面上に設けられ、第1導電型の不純物濃度が前記第1の半導体層よりも低い第1導電型の第2の半導体層と、
前記第2の半導体層の上層部に設けられ、第2導電型の第1の不純物領域と、
前記第1の不純物領域の上層部に設けられ、第1導電型の第2の不純物領域と、
少なくとも前記第1の不純物領域と前記第2の半導体層にゲート絶縁膜を間に介して対向するように設けられたゲート電極と、
少なくとも一部が前記第2の不純物領域に接続され、少なくとも一部が前記第1の不純物領域にショットキー接続される第1の主電極と、
前記第1の主電極が設けられた側とは反対側の前記第1の半導体層の第2の主面に接続される第2の主電極と、を備えたMOSトランジスタと、
前記第2の不純物領域をエミッタとし、前記第1の半導体層および前記第2の半導体層をコレクタとし、前記第1の不純物領域をベースとして構成される寄生トランジスタと、
前記第1の不純物領域をアノードとし、前記第1の半導体層および前記第2の半導体層をカソードとして構成される寄生ダイオードと、
前記第1の不純物領域をアノードとし、前記第1の主電極をカソードとして構成されるショットキーダイオードと、を有し、
前記寄生トランジスタのエミッタ電流に対するコレクタ電流の比が1/1000以下であり、
前記ショットキーダイオードのダイオード耐圧が前記MOSトランジスタをオンさせるゲート電圧のしきい値以上である、半導体装置。 - 第1導電型の第1の半導体層と、
前記第1の半導体層の第1の主面上に設けられ、第1導電型の不純物濃度が前記第1の半導体層よりも低い第1導電型の第2の半導体層と、
前記第2の半導体層の上層部に設けられ、第2導電型の第1の不純物領域と、
前記第1の不純物領域の上層部に設けられ、第1導電型の第2の不純物領域と、
少なくとも前記第1の不純物領域と前記第2の半導体層にゲート絶縁膜を間に介して対向するように設けられたゲート電極と、
少なくとも一部が前記第1の不純物領域に接続され、前記第1の不純物領域よりもバンドギャップが狭い第1導電型の狭バンドギャップ層と、
少なくとも一部が前記狭バンドギャップ層に接続され、前記第1の不純物領域とは直接には接しないように設けられる第1の主電極と、
前記第1の主電極が設けられた側とは反対側の前記第1の半導体層の第2の主面に接続される第2の主電極と、を備えたMOSトランジスタと、
前記第2の不純物領域をエミッタとし、前記第1の半導体層および前記第2の半導体層をコレクタとし、前記第1の不純物領域をベースとして構成される寄生トランジスタと、
前記第1の不純物領域をアノードとし、前記第1の半導体層および前記第2の半導体層をカソードとして構成される寄生ダイオードと、
前記第1の不純物領域をアノードとし、前記狭バンドギャップ層をカソードとして構成されるpn接合ダイオードと、を有する、半導体装置。 - 前記寄生トランジスタのエミッタ電流に対するコレクタ電流の比が1/1000以下であり、
前記pn接合ダイオードの接合耐圧が前記MOSトランジスタをオンさせるゲート電圧のしきい値以上である、請求項9記載の半導体装置。 - 第1導電型の第1の半導体層と、
前記第1の半導体層の第1の主面上に設けられ、第1導電型の不純物濃度が前記第1の半導体層よりも低い第1導電型の第2の半導体層と、
前記第2の半導体層の上層部に設けられ、第2導電型の第1の不純物領域と、
前記第1の不純物領域の上層部に設けられ、第1導電型の第2の不純物領域と、
前記第1の不純物領域または前記第2の不純物領域の上層部に設けられ、少なくとも一部が前記第2の不純物領域に接する第2導電型の第3の不純物領域と、
前記第1の不純物領域と前記第2の半導体層にゲート絶縁膜を間に介して対向するように設けられたゲート電極と、
少なくとも一部が前記第2の不純物領域に接続され、前記第1の不純物領域とは直接には接しないように設けられる第1の主電極と、
前記第1の主電極が設けられた側とは反対側の前記第1の半導体層の第2の主面に接続される第2の主電極と、を備えたMOSトランジスタと、
前記第2の不純物領域をエミッタとし、前記第1の半導体層および前記第2の半導体層をコレクタとし、前記第1の不純物領域をベースとして構成される寄生トランジスタと、
前記第1の不純物領域をアノードとし、前記第1の半導体層および前記第2の半導体層をカソードとして構成される寄生ダイオードと、
前記第3の不純物領域をアノードとし、前記第2の不純物領域をカソードとして構成される第1のpn接合ダイオードと、
前記第1の不純物領域をアノードとし、前記第2の不純物領域をカソードとして構成される第2のpn接合ダイオードと、を有する、半導体装置。 - 前記寄生トランジスタのエミッタ電流に対するコレクタ電流の比が1/1000以下であり、
前記第1のpn接合ダイオードの接合耐圧は、前記MOSトランジスタをオンさせるゲート電圧のしきい値以上、かつ前記MOSトランジスタの前記ゲート電極に印加できる最大電圧以下である、請求項11記載の半導体装置。
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