JP7175350B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

For example, a semiconductor device in which a semiconductor element such as a transistor is sealed with a resin package has been proposed. Patent Literature 1 discloses a semiconductor device including a semiconductor element having three electrodes, three leads electrically connected to these electrodes, and a resin package partially covering the semiconductor element and the three leads. The three electrodes are formed on the same surface of the semiconductor element. The semiconductor element is joined to one of the three leads. The three electrodes are individually electrically connected to the three leads via three wires. The resin package covers the entire semiconductor element, all of the three wires, and part of the three leads. Portions of the three leads that protrude from the resin package serve as terminal portions for mounting the semiconductor device.

In a conventional semiconductor device, the leads on which the semiconductor element is arranged are larger than the semiconductor element in plan view. This large lead determines the size of the resin package. Therefore, the large lead hinders miniaturization of the semiconductor device.

The three wires generally have a loop shape. Therefore, in order to properly cover the three wires, the resin package must have a suitable height. This increases the height of the semiconductor device. At the same time, in order to properly bond the three wires, it is necessary to secure a certain distance between the so-called first bonding portion and the second bonding portion. Furthermore, the terminal portions of the three leads protrude from the resin package. These increase the dimensions of the semiconductor device in plan view. As described above, the above semiconductor device has a problem that it is difficult to reduce its size.

JP 2012-190936 A

SUMMARY OF THE INVENTION The present invention has been conceived under the circumstances described above, and its main object is to provide a semiconductor device that can be miniaturized.

According to a first aspect of the present invention, there is provided a semiconductor element, a main lead on which the semiconductor element is arranged, and a resin package covering the semiconductor element and the main lead, wherein the main lead extends from the resin package. A semiconductor device is provided in which the semiconductor element has a portion that is exposed and does not overlap the main lead when viewed in the thickness direction of the semiconductor element.

Preferably, the main lead has a main lead surface and a main lead back surface facing opposite sides, the semiconductor element is arranged on the main lead main surface, and the main lead back surface is made of the resin. exposed from the package.

Preferably, the main lead includes a main full-thickness portion and a main eaves portion, the main full-thickness portion is a portion extending from the main lead main surface to the main lead back surface, and the main eaves portion includes the semiconductor. It protrudes from the main full-thickness portion in a direction perpendicular to the thickness direction of the element.

Preferably, the semiconductor element entirely overlaps the main full-thickness portion when viewed in the thickness direction of the semiconductor element.

Preferably, the semiconductor device further comprises a first sub-lead electrically connected to the semiconductor element, the first sub-lead being spaced apart from the main lead and exposed from the resin package.

Preferably, said main canopy portion has a main front portion, said main front portion projecting from said main full thickness portion toward said first minor lead.

Preferably, said main canopy portion has a main lateral portion, said main lateral portion projecting from said main full thickness portion in a direction perpendicular to the projecting direction of said main front portion. .

Preferably, the main lead includes a main side connecting portion protruding from the main side portion, and the main side connecting portion has an end surface exposed from the resin package.

Preferably, said main canopy portion has a main rear portion, said main rear portion projecting from said main full thickness portion in a direction opposite to the direction in which said main front portion projects.

Preferably, the main lead includes a main rear connecting portion protruding from the main rear portion, and the main rear connecting portion has an end surface exposed from the resin package.

Preferably, the main full-thickness portion is entirely surrounded by the main eaves portion when viewed in the thickness direction of the semiconductor element.

Preferably, the main eaves portion entirely overlaps the semiconductor element when viewed in the thickness direction of the semiconductor element.

Preferably, the semiconductor device further comprises a main surface plating layer formed on the main leads and interposed between the semiconductor element and the main leads.

Preferably, the main surface plating layer overlaps the entire main eaves.

Preferably, the semiconductor device further comprises a first sub-lead electrically connected to the semiconductor element, the first sub-lead being spaced apart from the main lead and extending outward of the resin package when viewed in the thickness direction of the semiconductor element. is exposed from the resin package.

Preferably, the first sub-lead includes a first sub-full-thickness portion and a first sub-eaves portion, and the first sub-lead has a first sub-lead main surface and a first sub-lead back surface facing opposite to each other. the back surface of the first sub-lead is exposed from the resin package; the first sub full-thickness portion is a portion extending from the main surface of the first sub-lead to the back surface of the first sub-lead; The one sub eaves portion protrudes from the first sub full thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and constitutes the first sub lead main surface.

Preferably, said first minor canopy portion has a first minor front portion, said first minor front portion projecting from said first minor full thickness portion toward said main lead.

Preferably, the first sub full thickness portion is exposed from the resin package toward the outside of the resin package when viewed in the thickness direction of the semiconductor element.

Preferably, the first sub-lead includes a first sub-extending portion and extends from the first sub-thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and The first sub-extending portion, which constitutes the back surface of the first sub-lead, is exposed from the resin package toward the outside of the resin package when viewed in the thickness direction of the semiconductor element.

Preferably, the first sub-lead has a first sub-lead main surface and a first sub-lead back surface facing opposite sides, and the first sub-lead back surface is exposed from the resin package.

Preferably, the resin package has a resin back surface facing in the same direction as the back surface of the first sub-lead, and the resin back surface is flush with the back surface of the first sub-lead.

Preferably, the first sub-lead has a first sub-lead end surface connected to the back surface of the first sub-lead, and the first sub-lead end surface faces the side opposite to the side where the main lead is located. .

Preferably, the end surface of the first sub-lead is exposed from the resin package.

Preferably, the resin package has a first resin end surface facing in the same direction as the first sub lead end surface, and the first resin end surface is flush with the first sub lead end surface. .

Preferably, the first sub-lead has a first sub-lead side surface connected to the back surface of the first sub-lead, and the first sub-lead side surface is defined by the direction in which the first sub-lead end surface faces and the thickness of the semiconductor element. oriented in a direction that is perpendicular to both the horizontal and vertical directions.

Preferably, the side surface of the first sub-lead is exposed from the resin package.

Preferably, the resin package has a first resin side surface facing in the same direction as the first sub lead side surface, and the first sub lead side surface is flush with the first resin side surface. .

Preferably, it further comprises a first wire that is directly connected to the semiconductor element and electrically connects the semiconductor element and the first sub-lead.

Preferably, it further comprises a first sub-plated layer interposed between the first sub-lead and the first wire.

Preferably, a second sub-lead electrically connected to the semiconductor element is further provided, the second sub-lead being spaced apart from the main lead and the first sub-lead, and viewed in the thickness direction of the semiconductor element. It is exposed from the resin package to the outside of the resin package.

Preferably, the device further comprises a second wire directly connected to the semiconductor element to electrically connect the semiconductor element and the second sub-lead.

Preferably, it further comprises a second sub-plated layer interposed between the second sub-lead and the second wire.

Preferably, the semiconductor element has a semiconductor layer laminated to each other, a eutectic layer of a semiconductor and a metal, and a single metal layer constituting the back electrode, and the single metal layer is directly bonded to the main lead. It is

Preferably, the eutectic layer is made of eutectic of Si and Au.

Preferably, the single metal layer is thinner than the eutectic layer.

Preferably, the semiconductor element further includes a first wire, the semiconductor element includes a first surface electrode to which the first wire is bonded, and the first surface electrode extends across the main entirety of the semiconductor element when viewed in the thickness direction of the semiconductor element. It overlaps the thick part.

Preferably, the semiconductor element further includes a second wire, the semiconductor element includes a second surface electrode to which the second wire is bonded, and the second surface electrode extends across the main entirety of the semiconductor element when viewed in the thickness direction of the semiconductor element. It overlaps the thick part.

Preferably, the semiconductor element further comprises a first wire and a second wire, wherein the semiconductor element has a first surface electrode to which the first wire is bonded and a second surface electrode to which the second wire is bonded; and at least one of the first surface electrode and the second surface electrode overlaps the main full-thickness portion when viewed in the thickness direction of the semiconductor element.

According to a second aspect of the present invention, it has a front surface and a back surface facing opposite directions in the thickness direction, a first surface electrode and a second surface electrode formed on the front surface, and a back surface electrode formed on the back surface. a semiconductor element, a main lead having a die pad portion electrically connected to the back surface electrode and a main back surface terminal portion facing the opposite side of the die pad portion, and a first lead connected to the first surface electrode via a first wire. a first sub-lead having a first wire-bonding portion and a first sub-back surface terminal portion facing away from the first wire-bonding portion; and a second wire-bonding connected to the second surface electrode via a second wire. and a second sub-back terminal portion facing away from the second wire bonding portion; the semiconductor element and the main lead; and a portion of the first sub-lead and the second sub-lead and a resin package that exposes the main back surface terminal portion, the first sub back surface terminal portion, and the second sub back surface terminal portion to the same side, and the main lead covers the die pad portion. a main full-thickness portion extending from the main rear surface terminal portion to the main back surface terminal portion; The die pad portion and the semiconductor element overlap both the main full-thickness portion and the main eaves portion when viewed in the thickness direction, and at least one of the first surface electrode and the second surface electrode overlaps the main eaves portion. Overlap, the first wire has a first bonding portion bonded to the first wire bonding portion and a second bonding portion bonded to the first surface electrode via a first bump, and The second wire has a first bonding portion bonded to the second wire bonding portion, and a second bonding portion bonded to the second surface electrode via a second bump. , a semiconductor device is provided.

Preferably, the first surface electrode is a gate electrode, the second surface electrode is a source electrode, the back surface electrode is a drain electrode, and the semiconductor element is configured as a transistor, and the first surface An electrode is spaced further from the first sub-lead and the second sub-lead than the second surface electrode.

Preferably, the first surface electrode overlaps the main full-thickness portion when viewed in the thickness direction, and the second surface electrode overlaps the main eaves portion when viewed in the thickness direction.

Preferably, the first surface electrode overlaps both the main full-thickness portion and the main eaves portion when viewed in the thickness direction.

Preferably, the first bump of the first wire and the second bonding portion of the first wire overlap both the main full-thickness portion and the main eaves portion when viewed in the thickness direction.

Preferably, the main eave portion has a main front portion projecting from the main full-thickness portion toward the first minor lead and the second minor lead.

Preferably, said main canopy has a main side projecting in a direction that is perpendicular to the direction in which said main front projects.

Preferably, the main lead has a main side connecting portion protruding from the main side portion and having one end surface exposed from the resin package.

Preferably, said main canopy has a main rear portion projecting opposite said main front portion.

Preferably, the main lead has a main rear connecting portion protruding from the main rear portion and having one end surface exposed from the resin package.

Preferably, all of said main full thickness is surrounded by said main eaves.

Preferably, a main surface plated layer is formed on the die pad portion.

Preferably, the main surface plating layer overlaps all of the main eaves.

Preferably, the first sub lead includes a first sub full thickness portion extending from the first wire bonding portion to the first sub back surface terminal portion, and a portion of the first sub full thickness portion on the side of the first wire bonding portion. and a first secondary eaves projecting in a direction perpendicular to the thickness direction.

Preferably, the first secondary canopy portion has a first secondary front portion projecting from the first secondary full thickness portion toward the primary lead.

Preferably, said first secondary eaves part has a first secondary lateral part projecting in a direction perpendicular to the direction in which said first secondary front part projects.

Preferably, the first sub-lead has a first sub-side connecting portion protruding from the first sub-side portion and having one end face exposed from the resin package.

Preferably, the first secondary eaves portion has a first secondary rear portion projecting opposite to the first secondary front portion.

Preferably, the first sub-lead has a first sub-rear connecting portion protruding from the first sub-rear portion and having one end face exposed from the resin package.

Preferably, the entire first sub-thickness portion is surrounded by the first sub-eaves portion.

Preferably, a first secondary surface plated layer is formed on the first wire bonding portion.

Preferably, the first sub-surface plating layer overlaps the entire first sub-eaves portion.

Preferably, the second sub lead includes a second sub full thickness portion extending from the second wire bonding portion to the second sub back surface terminal portion, and a portion extending from the second wire bonding portion side portion of the second sub full thickness portion. and a second secondary eaves projecting in a direction perpendicular to the thickness direction.

Preferably, the second secondary canopy portion has a second secondary front portion projecting from the second secondary full thickness portion toward the primary lead.

Preferably, the second secondary canopy portion has a second secondary lateral portion projecting in a direction perpendicular to the direction in which the second secondary front portion projects.

Preferably, the second sub-lead has a second sub-side connecting portion protruding from the second sub-side portion and having one end face exposed from the resin package.

Preferably, the second secondary eaves portion has a second secondary rear portion projecting opposite to the second secondary front portion.

Preferably, the second sub-lead has a second sub-rear connecting portion protruding from the second sub-rear portion and having one end face exposed from the resin package.

Preferably, the entire second minor full thickness portion is surrounded by the second minor eaves portion.

Preferably, a second sub-surface plated layer is formed on the second wire bonding portion.

Preferably, the second minor surface plated layer overlaps the entirety of the second minor eaves portion.

Preferably, the semiconductor element has a semiconductor layer laminated to each other, a eutectic layer of a semiconductor and a metal, and a single metal layer constituting the back electrode, and the single metal layer is directly bonded to the die pad portion. It is

Preferably, the eutectic layer is made of eutectic of Si and Au.

Preferably, the single metal layer is thinner than the eutectic layer.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a perspective view of a semiconductor device according to a first embodiment of the invention; FIG. 2 is a plan view of the semiconductor device shown in FIG. 1; FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1; FIG. 3 is a cross-sectional view taken along line IV-IV of FIG. 2; FIG. FIG. 3 is a cross-sectional view taken along line VV of FIG. 2; 2 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. 1; FIG. FIG. 3 is a cross-sectional view along line VII-VII of FIG. 2; FIG. 3 is a cross-sectional view along line VIII-VIII of FIG. 2; FIG. 3 is a cross-sectional view along line IX-IX of FIG. 2; 2 is an enlarged image showing a second bonding portion of the semiconductor device shown in FIG. 1; 2 is a cross-sectional view showing one step in the method of manufacturing the semiconductor device shown in FIG. 1; FIG. It is a perspective view of a semiconductor device according to a second embodiment of the present invention. 13 is a plan view of the semiconductor device shown in FIG. 12; FIG. 2 is an enlarged plan view of a main part showing a semiconductor element of the semiconductor device of FIG. 1; FIG. FIG. 10 is a plan view of a modification of the semiconductor device of the present invention; It is a perspective view showing an example of a semiconductor device based on a 3rd embodiment of the present invention. 17 is a perspective view showing the semiconductor device of FIG. 16; FIG. 17 is a plan view showing the semiconductor device of FIG. 16; FIG. FIG. 19 is a cross-sectional view along line XIX-XIX in FIG. 18; FIG. 19 is a cross-sectional view along line XX-XX of FIG. 18; 17 is an enlarged cross-sectional view of a main part showing the semiconductor device of FIG. 16; FIG. FIG. 19 is a cross-sectional view along line XXII-XXII of FIG. 18; FIG. 19 is a cross-sectional view along line XXIII-XXIII of FIG. 18; FIG. 19 is a cross-sectional view along line XXIV-XXIV of FIG. 18; 17 is an enlarged plan view of a main part showing a semiconductor element of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16; FIG. 17 is an enlarged image showing a second bonding portion formed in an example of the manufacturing process of the semiconductor device of FIG. 16; FIG. FIG. 17 is a plan view of a main part showing a cutting step in one example of the manufacturing steps of the semiconductor device of FIG. 16; 17 is an X-ray image showing the semiconductor device of FIG. 16; It is a top view which shows an example of the semiconductor device based on 4th Embodiment of this invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIGS. 1 to 11. FIG.

FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the invention. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a bottom view of the semiconductor device shown in FIG. 1. FIG. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. FIG. 5 is a cross-sectional view along line VV in FIG. FIG. 6 is a partially enlarged cross-sectional view of the semiconductor device shown in FIG. FIG. 7 is a cross-sectional view taken along line VII--VII of FIG. FIG. 8 is a cross-sectional view along line VIII-VIII of FIG. 9 is a cross-sectional view along line IX-IX in FIG. 2. FIG.

A semiconductor device 101 of this embodiment includes a semiconductor element 200 , a main lead 300 , a first sub-lead 400 , a second sub-lead 500 , a first wire 600 , a second wire 700 and a resin package 800 . 1 and 2, the resin package 800 is indicated by a two-dot chain line. The semiconductor device 101 is configured as a relatively small semiconductor device capable of so-called surface mounting. An example of the size of the semiconductor device 101 is about 0.4 to 0.8 mm in the x direction, about 0.2 to 0.6 mm in the y direction, and 0.3 to 0.3 mm in the z direction in the thickness direction. It is about 4 mm.

The semiconductor element 200 is configured as a so-called transistor in this embodiment. The semiconductor element 200 has a front surface 201 and a back surface 202, on which a first surface electrode 211, a second surface electrode 212 and a back surface electrode 220 are formed. The front surface 201 and back surface 202 face in opposite directions in the z-direction. An example of the size of the semiconductor element 200 is about 300 μm in the x direction and about 300 μm in the y direction.

As shown in FIG. 14, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are composed of parts of an electrode layer 213 made of, for example, an Au plating layer. In this embodiment, the first surface electrode 211 is the gate electrode and the second surface electrode 212 is the source electrode. In this embodiment, in FIG. 14, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Also, the first surface electrode 211 is positioned on the lower side in the y-direction view, and the second surface electrode 212 is positioned on the upper side in the y-direction view. A back electrode 220 is formed on the back surface 202 . In this embodiment, the back electrode 220 is the drain electrode.

A removed region 214 is formed by removing a portion of the electrode layer 231 . The removed region 214 has a shape surrounding the first surface electrode 211 . More specifically, the removal region 214 has a portion extending parallel to each other along the four sides of the semiconductor element 200 and a portion positioned across a relatively large area to surround the first surface electrode 211 . there is The first surface electrode 211 and the second surface electrode 212 are insulated by such an annular removed region 214 .

A peripheral area of the second surface electrode 212 is an active area 216 . A MOSFET 217 is built into the active region 216 at a portion inward from the surface 201 in the z-direction. The MOSFET 217 is composed of a plurality of unit cells 218 arranged in a matrix. Note that the arrangement form of the plurality of unit cells 218 is not limited to the matrix form, and may be, for example, a striped form or a zigzag form.

Although one second surface electrode 212 is provided as a source electrode in the present embodiment, the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

A semiconductor element 200 is arranged on the main lead 300 . As shown in FIGS. 2 and 3, in this embodiment, the semiconductor element 200 has a portion that does not overlap the main lead 300 when viewed in the thickness direction z. That is, the semiconductor element 200 has a portion protruding outside the main lead 300 when viewed in the thickness direction z. The main leads 300 are exposed from the resin package 800, which will be described in detail later. The primary lead 300 originates from the leadframe. Main lead 300 is formed by subjecting a metal plate made of Cu to patterning such as etching.

As shown in FIGS. 4, 5, etc., the main lead 300 has a main lead main surface 310 and a main lead back surface 320 facing opposite sides. Both the primary lead major surface 310 and the primary lead back surface 320 are flat.

The main lead main surface 310 faces upward in the thickness direction z. A semiconductor element 200 is arranged on the main lead main surface 310 . Further, in this embodiment, a main surface plated layer 311 is formed on the main lead main surface 310 of the main lead 300 . Main surface plating layer 311 is interposed between semiconductor element 200 and main lead 300 . The main surface plating layer 311 is formed over the entire main lead main surface 310 . The main surface plated layer 311 is made of Ag with a thickness of about 2 μm, for example.

In FIG. 3, the main lead back surface 320 is indicated by hatching. The main lead back surface 320 faces downward in the thickness direction z opposite to the main lead main surface 310 and is used for surface-mounting the semiconductor device 101 . The main lead back surface 320 is rectangular. The main lead rear surface 320 entirely overlaps the main lead main surface 310 when viewed in the thickness direction z, and is included in the main lead main surface 310 .

The main lead 300 includes a main full thickness portion 330 and a main eaves portion 340 .

The main full-thickness portion 330 is a portion extending from the main lead main surface 310 to the main lead back surface 320 in the thickness direction z. In this embodiment, the main full-thickness portion 330 entirely overlaps the semiconductor element 200 when viewed in the thickness direction z. At least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main full-thickness portion 330 in the thickness direction view z. In this embodiment, both the first surface electrode 211 and the second surface electrode 212 overlap the main full-thickness portion 330 in the thickness direction view z. That is, the first surface electrode 211 and the second surface electrode 212 are arranged near the center of the semiconductor element 200 in the thickness direction view z. Unlike the present embodiment, only the first surface electrode 211 overlaps the main full thickness portion 330 in the thickness direction view z, and the second surface electrode 212 overlaps the main full thickness portion 330 in the thickness direction view z. It doesn't have to be. Similarly, unlike the present embodiment, only the second surface electrode 212 overlaps the main full-thickness portion 330 in the thickness direction z, and the first surface electrode 211 overlaps the main full-thickness portion 330 in the thickness direction z. may not overlap. In this embodiment, the thickness of the main full-thickness portion 330 is approximately 0.9 to 1.1 mm. The main full-thickness portion 330 constitutes the main lead back surface 320 .

The main eaves 340 protrude from the main full-thickness portion 330 in a direction perpendicular to the thickness direction z. In this embodiment, the main eaves 340 protrude from the main full-thickness portion 330 in the x- and y-directions, which are perpendicular to the thickness direction z. Further, in this embodiment, the main eaves portion 340 protrudes from the portion of the main full-thickness portion 330 on the main lead main surface 310 side in the x-direction and the y-direction perpendicular to the thickness direction z. The thickness of the main eaves portion 340 is, for example, half the thickness of the main full-thickness portion 330, which is about 0.05 mm. The main eaves portion 340 and the main full-thickness portion 330 constitute the main lead main surface 310 described above. On the other hand, the main eaves portion 340 does not constitute the main lead back surface 320 . The main eaves portion 340 surrounds the main full-thickness portion 330 when viewed in the thickness direction z. Further, in the present embodiment, the main eaves portion 340 entirely overlaps the semiconductor element 200 when viewed in the thickness direction z.

In this embodiment, the main eaves portion 340 has a main front portion 341 , a main side portion 342 and a main rear portion 343 .

A main front portion 341 protrudes from the main full thickness portion 330 toward the first secondary lead 400 . Further, in this embodiment, the main front portion 341 protrudes from the main full-thickness portion 330 toward the second secondary lead 500 .

Main lateral portions 342 project from main full thickness portion 330 in a direction that is perpendicular to the direction in which main front portion 341 projects. Specifically, the main lateral portions 342 protrude from the main full-thickness portion 330 in the y-direction. In this embodiment, two main lateral portions 342 are formed. Also, in this embodiment, the main lead 300 has two main side connecting portions 351 . The main side connecting portions 351 extend from the main side portions 342 of the main eaves 340 and have the same thickness as the main side portions 342 . The y-direction end surface of the main side connecting portion 351 is exposed from the resin package 800 .

A rear main portion 343 projects from the main full thickness portion 330 in a direction opposite to the direction in which the main front portion 341 projects. In this embodiment, the main lead 300 has a main rear connection 352 . The main rear connection portion 352 extends from the main rear portion 343 of the main canopy portion 340 and is the same thickness as the main rear portion 343 . The x-direction end surface of the main rear connecting portion 352 is exposed from the resin package 800 .

As shown in FIG. 6, the semiconductor element 200 has the back electrode 220 bonded to the main lead main surface 310 (main surface plating layer 311). Specifically, the back electrode 220 as a single metal layer is directly bonded to the main lead main surface 310 (main surface plated layer 311) by, for example, thermocompression bonding. In this thermocompression bonding, only heat and pressure are applied without vibration.

The first secondary lead 400 is spaced apart from the primary lead 300 . Specifically, the first sub-lead 400 is spaced apart from the main lead 300 in the x-direction. Also, the first sub-lead 400 is separated from the second sub-lead 500 . The first sub-lead 400 is exposed from the resin package 800 to the outside of the resin package 800 when viewed in the thickness direction z. In this embodiment, the first sub-lead 400 is exposed from the resin package 800 in the directions x and y from the resin package 800 . The first secondary lead 400 originates from the leadframe. The first sub-lead 400 is formed by subjecting a metal plate made of Cu to patterning such as etching.

The first minor lead 400 has a first minor lead main surface 410 , a first minor lead rear surface 420 , a first minor lead end surface 481 and a first minor lead side surface 482 . The first minor lead main surface 410, the first minor lead back surface 420, the first minor lead end surface 481, and the first minor lead side surface 482 are all flat.

The first sub-lead main surface 410 faces upward in the thickness direction z. A first wire 600 is bonded to the first sub-lead main surface 410 . In this embodiment, a first sub-surface plated layer 411 is formed on the first sub-lead main surface 410 . First minor surface plating layer 411 is interposed between first minor lead major surface 410 and first wire 600 . The first sub-surface plated layer 411 is formed over the entire first sub-lead main surface 410 . The first sub-surface plated layer 411 is made of Ag with a thickness of about 2 μm, for example. In addition, in FIG. 1, the first sub-surface plated layer 411 is half-toned for convenience of understanding.

The first secondary lead rear surface 420 faces the opposite direction to the direction in which the primary secondary lead surface 410 faces. Specifically, the first sub-lead rear surface 420 faces downward in the thickness direction z opposite to the first sub-lead main surface 410 . The first sub-lead rear surface 420 is exposed from the resin package 800 . The first sub-lead rear surface 420 is used for surface-mounting the semiconductor device 101 . In FIG. 3, the back surface 420 of the first sub-lead is indicated by hatching.

The first sub-lead end surface 481 faces the side opposite to the side where the main lead 300 is located. Specifically, the first sub-lead end face 481 faces rightward in FIG. The first sub-lead end surface 481 is connected to the first sub-lead rear surface 420 . The first sub lead end surface 481 is exposed from the resin package 800 .

The first sub-lead side surface 482 faces in a direction perpendicular to both the direction in which the first sub-lead end surface 481 faces and the thickness direction z of the semiconductor element 200 . Specifically, the first minor lead side surface 482 faces downward in FIG. The first sub-lead side surface 482 is connected to the first sub-lead back surface 420 . The first sub lead side surface 482 is exposed from the resin package 800 .

The first secondary lead 400 includes a first secondary full-thickness portion 430 and a first secondary eaves portion 440 .

The first sub-full-thickness portion 430 is a portion extending from the first sub-lead main surface 410 to the first sub-lead rear surface 420 in the thickness direction z. In this embodiment, the thickness of the first sub full thickness portion 430 is approximately 0.1 mm. The first secondary full-thickness portion 430 constitutes the first secondary lead main surface 410 and the first secondary lead rear surface 420 . In this embodiment, the first sub full thickness portion 430 is exposed from the resin package 800 . Therefore, the first sub full-thickness portion 430 forms a first sub lead end surface 481 and a first sub lead side surface 482 .

The first minor eaves portion 440 protrudes from the first minor full thickness portion 430 in a direction perpendicular to the thickness direction z. In this embodiment, the first secondary eaves portion 440 protrudes in the x-direction and the y-direction. The thickness of the first sub eaves portion 440 is, for example, half the thickness of the first sub full-thickness portion 430, which is about 0.05 mm. The first sub eaves portion 440 constitutes the first sub lead main surface 410 . On the other hand, the first sub eaves portion 440 does not constitute the first sub lead back surface 420 .

In this embodiment, the first secondary eaves portion 440 has a first secondary front portion 441 and a first secondary inner portion 442 .

A first minor front portion 441 protrudes from the first minor full thickness portion 430 toward the main lead 300 . The first minor inner portion 442 protrudes from the first minor full thickness portion 430 toward the second minor lead 500 .

The second secondary lead 500 is spaced apart from the primary lead 300 . Specifically, the second sub-lead 500 is spaced apart from the main lead 300 in the x-direction. Also, the second sub-lead 500 is separated from the first sub-lead 400 . The second sub-lead 500 is exposed from the resin package 800 to the outside of the resin package 800 when viewed in the thickness direction z. In this embodiment, the second sub-lead 500 is exposed from the resin package 800 in the directions x and y from the resin package 800 . A second secondary lead 500 originates from the lead frame. The second sub-lead 500 is formed by subjecting a metal plate made of Cu to patterning such as etching.

The second minor lead 500 has a second minor lead main surface 510 , a second minor lead rear surface 520 , a second minor lead end surface 581 and a second minor lead side surface 582 . The second minor lead main surface 510, the second minor lead rear surface 520, the second minor lead end surface 581, and the second minor lead side surface 582 are all flat.

The second minor lead main surface 510 faces upward in the thickness direction z. A second wire 700 is bonded to the second minor lead main surface 510 . In this embodiment, a second sub-surface plated layer 511 is formed on the second sub-lead main surface 510 . The second minor surface plating layer 511 is interposed between the second minor lead major surface 510 and the second wire 700 . The second sub-surface plated layer 511 is formed over the entire second sub-lead main surface 510 . The second sub-surface plated layer 511 is made of Ag with a thickness of about 2 μm, for example. In addition, in FIG. 1, the second sub-surface plated layer 511 is half-toned for convenience of understanding.

The second sub-lead rear surface 520 faces the opposite direction to the direction in which the second sub-lead main surface 510 faces. Specifically, the back surface 520 of the second sub-lead faces downward in the thickness direction z opposite to the main surface 510 of the second sub-lead. The second sub-lead rear surface 520 is exposed from the resin package 800 . The second sub-lead rear surface 520 is used for surface-mounting the semiconductor device 101 . In FIG. 3, the back surface 520 of the second sub-lead is indicated by hatching.

The second sub-lead end surface 581 faces the side opposite to the side where the main lead 300 is located. Specifically, the second sub-lead end face 581 faces rightward in FIG. The second sub-lead end surface 581 is connected to the second sub-lead rear surface 520 . The second sub lead end surface 581 is exposed from the resin package 800 .

The second sub-lead side surface 582 faces in a direction perpendicular to both the direction in which the second sub-lead end surface 581 faces and the thickness direction z of the semiconductor element 200 . Specifically, the second minor lead side surface 582 faces upward in FIG. The second sub-lead side surface 582 is connected to the second sub-lead rear surface 520 . The second sub lead side surface 582 is exposed from the resin package 800 .

The second secondary lead 500 includes a second secondary full-thickness portion 530 and a second secondary eaves portion 540 .

The second secondary full-thickness portion 530 is a portion extending from the second secondary lead main surface 510 to the second secondary lead rear surface 520 in the thickness direction z. In this embodiment, the thickness of the second sub full-thickness portion 530 is approximately 0.1 mm. The second secondary full-thickness portion 530 constitutes the second secondary lead main surface 510 and the second secondary lead rear surface 520 . In this embodiment, the second sub full thickness portion 530 is exposed from the resin package 800 . Therefore, the second secondary full-thickness portion 530 forms a second secondary lead end surface 581 and a second secondary lead side surface 582 .

The second minor eaves portion 540 protrudes from the second minor full thickness portion 530 in a direction perpendicular to the thickness direction z. In this embodiment, the second secondary eaves portion 540 protrudes in the x-direction and the y-direction. The thickness of the second sub eaves portion 540 is, for example, half the thickness of the second sub full-thickness portion 530, which is about 0.05 mm. The second secondary eaves portion 540 constitutes the second secondary lead main surface 510 . On the other hand, the second sub eaves portion 540 does not constitute the second sub lead back surface 520 .

In this embodiment, the second secondary eaves portion 540 has a second secondary front portion 541 and a second secondary inner portion 542 .

A second minor front portion 541 protrudes from the second minor full thickness portion 530 toward the main lead 300 . The second secondary inner portion 542 protrudes from the second secondary full-thickness portion 530 toward the first secondary lead 400 .

The first wire 600 is directly connected to the semiconductor element 200 and electrically connects the semiconductor element 200 and the first sub-lead 400 . Specifically, the first wire 600 is joined to the first surface electrode 211 and the first sub-surface plated layer 411 of the semiconductor element 200 .

The first wire 600 has a first bonding portion 610 and a second bonding portion 620 . The first wire 600 is made of Au with a diameter of about 20 μm.

The first bonding portion 610 is bonded to the first sub-surface plating layer 411 and has a crown-shaped block portion.

Second bonding portion 620 is bonded to first surface electrode 211 of semiconductor element 200 via first bump 630 . The second bonding portion 620 has a tapered shape in which the thickness in the thickness direction z decreases toward the tip.

The first bump 630 is a portion similar to the lump portion of the first bonding portion 610 . In the present embodiment, the first bump 630 has a slightly smaller volume than the bulk portion of the first bonding portion 610 . The first bump 630 overlaps the main full-thickness portion 330 when viewed in the thickness direction z. 10 shows an enlarged image of the second bonding portion 620 of the semiconductor device shown in FIG.

The second wire 700 is directly connected to the semiconductor element 200 and electrically connects the semiconductor element 200 and the second sub-lead 500 . Specifically, the second wire 700 is joined to the second surface electrode 212 and the second sub-surface plated layer 511 of the semiconductor element 200 .

The second wire 700 has a first bonding portion 710 and a second bonding portion 720 . The second wire 700 is made of Au with a diameter of about 20 μm.

The first bonding portion 710 is bonded to the second sub-surface plating layer 511 and has a crown-shaped block portion.

Second bonding portion 720 is bonded to second surface electrode 212 of semiconductor element 200 via second bump 730 . The second bonding portion 720 has a tapered shape in which the thickness in the thickness direction z decreases toward the tip.

The second bump 730 is a portion of the first bonding portion 710 similar to the lump portion. The second bump 730 overlaps the main full-thickness portion 330 when viewed in the thickness direction z. In this embodiment, the second bump 730 has a slightly smaller volume than the bulk portion of the first bonding portion 710 .

The resin package 800 covers the semiconductor element 200 , the main lead 300 , the first sub-lead 400 , the second sub-lead 500 , the first wire 600 and the second wire 700 . Resin package 800 is made of, for example, black epoxy resin. In addition, the resin package 800 is configured so that all of the main lead back surface 320 of the main lead 300, the first sub lead back surface 420 of the first sub lead 400, and the second sub lead back surface 520 of the second sub lead 500 are downward in the thickness direction z. exposed on the side.

The resin package 800 has a resin main surface 801 , a resin back surface 802 , a first resin side surface 803 , a second resin side surface 804 , a first resin end surface 805 and a second resin end surface 806 .

The resin main surface 801 faces in the same direction as the main lead main surface 310 faces. In this embodiment, the resin main surface 801 is flat.

The resin back surface 802 faces the same direction as the main lead back surface 320 faces. That is, the resin rear surface 802 faces in the direction opposite to the direction in which the resin main surface 801 faces. The resin back surface 802 is flat. The main lead 300 , the first sub-lead 400 and the second sub-lead 500 are exposed from the resin back surface 802 . In this embodiment, the resin back surface 802 is flush with all of the main lead back surface 320 , the first sub-lead back surface 420 , and the second sub-lead back surface 520 .

The first resin side surface 803 faces the same direction as the first sub lead side surface 482 of the first sub lead 400 faces. The first resin side surface 803 is flat. The first sub-lead 400 is exposed from the first resin side surface 803 . In this embodiment, the first secondary full-thickness portion 430 is exposed from the second resin side surface 804 . The first resin side surface 803 is flush with the first sub-lead side surface 482 . Further, in this embodiment, the main lead 300 is exposed on the first resin side surface 803 . Specifically, the main side connecting portion 351 of the main lead 300 is exposed on the first resin side surface 803 . The first resin side surface 803 is flush with the end surface of the main side connecting portion 351 .

The second resin side surface 804 faces the same direction as the second sub lead side surface 582 of the second sub lead 500 faces. The second resin side 804 is flat. The second sub-lead 500 is exposed from the second resin side surface 804 . The second resin side surface 804 is flush with the second sub-lead side surface 582 . In this embodiment, the second sub full-thickness portion 530 is exposed from the second resin side surface 804 . Further, in this embodiment, the main lead 300 is exposed on the second resin side surface 804 . Specifically, the main side connecting portion 351 of the main lead 300 is exposed on the second resin side surface 804 . The second resin side surface 804 is flush with the end surface of the main side connecting portion 351 .

The first resin end face 805 faces in the same direction as the first sub lead end face 481 of the first sub lead 400 faces. The first resin end surface 805 is flat. The first sub-lead 400 is exposed from the first resin end surface 805 . The first resin end face 805 is flush with the first sub-lead end face 481 . In this embodiment, the first sub full thickness portion 430 is exposed from the first resin end surface 805 . Similarly, the first resin end face 805 faces the same direction as the second sub lead end face 581 of the second sub lead 500 faces. The second sub-lead 500 is exposed from the first resin end surface 805 . The first resin end face 805 is flush with the second sub-lead end face 581 . In this embodiment, the second sub full thickness portion 530 is exposed from the first resin end surface 805 .

The second resin end face 806 faces in the direction opposite to the direction in which the first resin end face 805 faces. The second resin end surface 806 is flat. The main lead 300 is exposed from the second resin end surface 806 . In this embodiment, the main rear connecting portion 352 is exposed from the second resin end face 806 . The second resin end face 806 is flush with the end face of the main rear connecting portion 352 .

The reason why the surface of the resin and the surface of the lead (the main lead 300, the first sub-lead 400, or the second sub-lead 500) are flush with each other is that when the semiconductor device 101 is manufactured, the lead frame and the , and the resin member to be the resin package are diced together. FIG. 11 shows a cross-sectional view of one step in the method of manufacturing the semiconductor device shown in FIG. This figure shows the vicinity of the first sub-lead 400 . In this embodiment, the leads and the resin member are diced along the line Ct1 in the figure.

Next, the effects of this embodiment will be described.

In this embodiment, the semiconductor element 200 has a portion that does not overlap the main lead 300 when viewed in the thickness direction z of the semiconductor element 200 . With such a configuration, the size of the main lead 300 can be made relatively smaller than the size of the semiconductor element 200 when viewed in the thickness direction z. As a result, the size of the resin package 800 as viewed in the thickness direction z is determined by the semiconductor element 200 rather than by the main leads 300 . As a result, the size of the semiconductor device 101 viewed in the thickness direction z can be reduced.

In this embodiment, primary lead 300 includes primary full thickness portion 330 and primary eaves portion 340 . With such a configuration, the bonding area between the semiconductor element 200 and the main lead 300 can be increased. Thereby, the semiconductor element 200 can be reliably bonded by the main lead 300 .

Second bonding portion 620 of first wire 600 is bonded to first surface electrode 211 via first bump 630 , and second bonding portion 720 of second wire 700 is bonded to second surface electrode 212 via second bump 730 . By adopting a configuration in which the first wire 600 and the second wire 700 are joined to each other, the thickness direction z height of the first wire 600 and the second wire 700 can be reduced. This contributes to reducing the height of the semiconductor device 101 in the thickness direction z. Therefore, according to this embodiment, the size of the semiconductor device 101 can be reduced.

Since the first surface electrode 211 as the gate electrode is spaced further from the first sub-lead 400 and the second sub-lead 500 than the second surface electrode 212 as the source electrode, the length of the first wire 600 is can be longer than the second wire 700 . The longer first wire 600 tends to increase the bonding strength particularly at the second bonding portion 620 . Generally, the first surface electrode 211 as a gate electrode is formed on the relatively smooth surface of the semiconductor layer 231 with an insulating layer (not shown) interposed therebetween. Such a first surface electrode 211 is relatively difficult to improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as a source electrode is often connected to metal portions filled in a plurality of trenches (vertical holes) formed in the semiconductor layer 231 . With such a configuration, the second surface electrode 212 relatively easily improves the bonding strength of wire bonding. Therefore, bonding the first wire 600, which tends to increase the bonding strength, to the first surface electrode 211 serving as the gate electrode, which is likely to have relatively insufficient bonding strength, is advantageous in avoiding problems such as wire peeling. .

Since main eaves portion 340 has main front portion 341 , the bonding strength between main lead 300 and resin package 800 can be increased. In addition, while bringing the semiconductor element 200 close to the first sub-lead 400 and the second sub-lead 500, it is possible to prevent the back surface 320 of the main lead and the back surface 420 and the second sub-lead 520 from being unduly close to each other. can do.

Since main eaves portion 340 has main side portion 342 and main rear portion 343 , the bonding strength between main lead 300 and resin package 800 can be increased. The configuration in which the entire main full-thickness portion 330 is surrounded by the main eaves portion 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800 .

Main side connecting portion 351 and main rear connecting portion 352 properly hold main lead 300 during the manufacturing process of semiconductor device 101 . The y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352 are exposed from the resin package 800 but separated from the main lead rear surface 320 . Therefore, the solder for surface-mounting the semiconductor device 101 is less likely to erroneously spread over the y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352 .

By forming the main surface plating layer 311 on the main lead main surface 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the main lead main surface 310 can be increased. By having the main surface plating layer 311 overlap the entire main eaves portion 340, the area that can be used as the main lead main surface 310 can be expanded.

Since the first sub-lead 400 has the first sub-eaves portion 440, the bonding strength between the first sub-lead 400 and the resin package 800 can be increased. The first sub eaves portion 440 has the first sub front portion 441, so that the distance between the first sub lead back surface 420 and the main lead back surface 320 becomes unduly close while increasing the joint strength with the resin package 800. can be avoided. This is because even if the entire semiconductor device 101 is miniaturized, the back surface 420 of the first sub-lead and the back surface 320 of the main lead are separated from the solder attached to the back surface 420 of the first sub-lead and the back surface 320 of the main lead. It means that it is possible to prevent the problem of conduction through the solder.

Since the first sub eaves portion 440 has the first sub inner portion 442 , the bonding strength between the first sub lead 400 and the resin package 800 can be increased. Since the first sub eaves portion 440 has the first sub inner portion 442 , the bonding strength with the resin package 800 is increased, and the distance between the first sub lead back surface 420 and the second sub lead back surface 520 is reduced. can be avoided from approaching This is because even if the entire semiconductor device 101 is miniaturized, the back surface 420 of the first sub-lead and the back surface 520 of the second sub-lead are separated from the solder adhering to the back surface 420 of the first sub-lead and the back surface 520 of the second sub-lead. This means that it is possible to prevent the problem of conduction via the solder adhering to the back surface 520 .

In this embodiment, the first sub-lead 400 has a first sub-lead end surface 481 connected to the first sub-lead back surface 420 . The first sub lead end surface 481 is exposed from the resin package 800 . Therefore, the first sub-lead rear surface 420 can be made wider. As a result, the tape 901 (see FIG. 11) used in resin molding for forming the resin package 800 and the back surface 420 of the first sub-lead can be more strongly bonded. Therefore, it is possible to prevent the resin material from entering between the tape 901 and the back surface 420 of the first sub-lead during resin molding. As a result, it is possible to prevent resin burrs from occurring on the rear surface 420 of the first sub-lead. Similarly, by exposing the first sub-lead side surface 482 from the resin package 800, a similar effect can be obtained. In addition, the exposure of the second sub-lead end surface 581 of the second sub-lead 500 from the resin package 800 and the exposure of the second sub-lead side surface 582 also contribute to the effect on the first sub-lead 400. and the same effect as described above.

By forming the first sub-surface plated layer 411 on the first sub-lead main surface 410, the bonding strength between the first wire 600 and the first sub-lead main surface 410 can be increased.

Since the second sub-lead 500 has the second sub-eaves portion 540, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. The second sub eaves portion 540 has the second sub front portion 541, so that the distance between the second sub lead back surface 520 and the main lead back surface 320 becomes unduly close while increasing the joint strength with the resin package 800. can be avoided.

Since the second sub eaves portion 540 has the second sub inner portion 542 , the bonding strength between the second sub lead 500 and the resin package 800 can be increased. Since the second sub eaves portion 540 has the second sub inner portion 542 , the bonding strength with the resin package 800 is increased, and the distance between the second sub lead back surface 520 and the first sub lead back surface 420 is not inappropriate. can be avoided from approaching This is because even if the entire semiconductor device 101 is miniaturized, the back surface 420 of the first sub-lead and the back surface 520 of the second sub-lead are separated from the solder adhering to the back surface 420 of the first sub-lead and the back surface 520 of the second sub-lead. This means that it is possible to prevent the problem of conduction via the solder adhering to the back surface 520 .

By forming the second sub-surface plated layer 511 on the second sub-lead main surface 510, the bonding strength between the second wire 700 and the second sub-lead main surface 510 can be increased.

In the bonding between the semiconductor element 200 and the main lead main surface 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly bonded to the main lead main surface 310, and vibration is applied during the bonding. do not have. With such a configuration, it is not necessary to set a marginal area in consideration of vibration in the area of the main lead 300 located around the semiconductor element 200 . This is advantageous for miniaturization of the semiconductor device 101 .

A second embodiment of the present invention will be described with reference to FIGS. 12 and 13. FIG.

FIG. 12 is a perspective view of a semiconductor device according to a second embodiment of the invention. 13 is a plan view of the semiconductor device shown in FIG. 12. FIG.

The semiconductor device 102 shown in these figures differs from the semiconductor device 101 in the shapes of the first sub-lead 400 and the second sub-lead 500 . Configurations other than those described below are the same as those of the semiconductor device 101, so the same reference numerals as in the first embodiment are used, and the description thereof is omitted.

In this embodiment, the first sub lead 400 includes a first sub full-thickness portion 430 , a first sub eaves portion 440 , and a first sub extension portion 460 .

In this embodiment, the first sub full thickness portion 430 is not exposed from the resin package 800 .

A first minor extension 460 extends from the first minor full thickness portion 430 in a direction perpendicular to the thickness direction z. The thickness of the first secondary extension portion 460 is, for example, half the thickness of the first secondary full thickness portion 430, which is approximately 0.05 mm. The first sub-extending portion 460 constitutes the first sub-lead rear surface 420 . On the other hand, the first sub-extending portion 460 does not constitute the first sub-lead main surface 410 . The first sub-extending portion 460 is exposed from the resin package 800 toward the outside of the resin package 800 when viewed in the thickness direction z. Specifically, first sub-extending portion 460 is exposed from resin package 800 in directions x and y from resin package 800 . Therefore, the first sub-extending portion 460 forms a first sub-lead end surface 481 and a first sub-lead side surface 482 .

In this embodiment, the first minor extension 460 has a first minor rear portion 461 and a first minor side portion 462 .

The first secondary rear portion 461 protrudes from the first secondary full-thickness portion 430 toward the side opposite to the side where the main lead 300 is located. The first secondary rear portion 461 constitutes a first secondary lead end surface 481 . The first secondary side portion 462 protrudes from the first secondary full-thickness portion 430 toward the side opposite to the side where the second secondary lead 500 is located. The first secondary side portion 462 constitutes a first secondary lead side surface 482 .

In this embodiment, the second sub full-thickness portion 530 is not exposed from the resin package 800 .

The second minor extension 560 extends from the second minor full thickness portion 530 in a direction perpendicular to the thickness direction z. The thickness of the second sub-extending portion 560 is, for example, half the thickness of the second sub full-thickness portion 530, which is about 0.05 mm. The second sub-extending portion 560 constitutes the second sub-lead rear surface 520 . On the other hand, the second sub-extending portion 560 does not constitute the second sub-lead main surface 510 . The second sub-extending portion 560 is exposed from the resin package 800 toward the outside of the resin package 800 when viewed in the thickness direction z. Specifically, the second sub-extending portion 560 is exposed from the resin package 800 in the directions x and y from the resin package 800 . Therefore, the second sub-extending portion 560 forms a second sub-lead end surface 581 and a second sub-lead side surface 582 .

In this embodiment, the second minor extension 560 has a second minor rear portion 561 and a second minor side portion 562 .

The second secondary rear portion 561 protrudes from the second secondary full-thickness portion 530 toward the side opposite to the side where the main lead 300 is located. The second secondary rear portion 561 constitutes a second secondary lead end surface 581 . The second secondary side portion 562 protrudes from the second secondary full-thickness portion 530 toward the side opposite to the side where the first secondary lead 400 is located. The second secondary side portion 562 constitutes a second secondary lead side surface 582 .

When manufacturing the semiconductor device 102, the leads and the resin member are diced along the line Ct2 in FIG.

Next, the effects of this embodiment will be described.

According to this embodiment, in addition to the same effects as those described for the semiconductor device 101, the following effects are obtained.

According to this embodiment, when cutting the first sub-lead 400 of the lead frame, the first sub-thickness portion 430 need not be diced, and the comparatively thin portion can be diced. The occurrence of burrs is proportional to the thickness of the lead frame to be cut. Therefore, it is possible to suppress the occurrence of metal burrs that may be formed by cutting the portion of the lead frame that is to become the first sub-lead 400 . Similarly, it is possible to suppress the occurrence of metal burrs that may be formed by cutting the portion of the lead frame that is to become the second sub-lead 500 .

Actually, when the main lead 300, the first sub-lead 400 and the second sub-lead 500 are patterned by etching, the boundary between the main full-thickness portion 330 and the main eaves portion 340 is shown in FIGS. The sharp corners shown in are not formed and can be curved. Similarly, the boundary between the first sub full-thickness portion 430 and the first sub eaves portion 440 in the first sub lead 400 , the boundary between the first sub eaves portion 440 and the first sub extension portion 460 , the second sub lead 500 The boundary between the second secondary full-thickness portion 530 and the second secondary eaves portion 540, the boundary between the second secondary eaves portion 540 and the second secondary extension portion 560, and the like can also be curved surfaces. This is because, even if the semiconductor devices 101 and 102 are designed to have the configurations shown in FIGS. This is because it may occur.

FIG. 15 shows a modification of the semiconductor device. As shown in the figure, the positions of the first surface electrode 211 as the gate electrode, the second surface electrode 212 as the source electrode, the second bonding portions 620 and 720, the first bump 630, and the second bump 730 are , is different from the semiconductor device shown in FIG. Since the description of the semiconductor device 101 can be applied to the description of the semiconductor device shown in FIG. 15 other than these positions, the description other than the position is omitted. In FIG. 2 , the first surface electrode 211 as the gate electrode is positioned on the left side of the semiconductor element 200 , and the second surface electrode 212 as the source electrode is positioned on the right side of the semiconductor element 200 . Also, the second bonding portion 620 and the first bump 630 were located on the left side of the second bonding portion 720 and the second bump 730 . On the other hand, in FIG. 15 , the first surface electrode 211 as the gate electrode is positioned on the right side of the semiconductor element 200 , and the second surface electrode 212 as the source electrode is positioned on the left side of the semiconductor element 200 . Second bonding portion 620 and first bump 630 are positioned to the right of second bonding portion 720 and second bump 730 . In this manner, the positions of the first surface electrode 211 as the gate electrode and the second surface electrode 212 as the source electrode in plan view can be freely changed.

The invention is not limited to the embodiments described above. The specific configuration of each part of the present invention can be changed in various ways. A semiconductor element is not limited to a transistor, and may be a diode, for example.

16 to 24 show an example of a semiconductor device according to the third embodiment of the invention.

A semiconductor device 101 of this embodiment includes a semiconductor element 200 , main leads 300 , first sub leads 400 , second sub leads 500 , first wires 600 , second wires 700 and a resin package 800 . The semiconductor device 101 is configured as a relatively small semiconductor device that can be surface-mounted. The directional dimension is about 0.36 mm. The z-direction is the thickness direction of the semiconductor element, the main lead, the first sub-lead and the second sub-lead referred to in the present invention. FIG. 16 is a perspective view of the semiconductor device 101 viewed from above in the z direction. FIG. 17 is a perspective view of the semiconductor device 101 viewed from below in the z direction. FIG. 18 is a plan view of the semiconductor device 101. FIG. 19 is a cross-sectional view in the zx plane along line XIX-XIX in FIG. 18. FIG. 20 is a cross-sectional view in the zx plane along line XX-XX in FIG. 18. FIG. FIG. 21 is an enlarged cross-sectional view of a main part in the zx plane that traverses the semiconductor element 200. FIG. 22 is a cross-sectional view in the yz plane taken along line XXII-XXII of FIG. 18. FIG. 23 is a cross-sectional view in the yz plane along line XXIII-XXIII of FIG. 18. FIG. 24 is a cross-sectional view in the yz plane taken along line XXIV-XXIV of FIG. 18. FIG.

The semiconductor element 200 is configured as a so-called transistor in this embodiment. The semiconductor element 200 has a front surface 201 and a back surface 202, on which a first surface electrode 211, a second surface electrode 212 and a back surface electrode 220 are formed. The front surface 201 and back surface 202 face in opposite directions in the z-direction. An example of the size of the semiconductor element 200 is about 300 μm in the x direction and about 300 μm in the y direction.

As shown in FIG. 25, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are composed of parts of an electrode layer 213 made of, for example, an Au plating layer. In this embodiment, the first surface electrode 211 is the gate electrode and the second surface electrode 212 is the source electrode. In this embodiment, in FIGS. 18 and 25, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Also, the first surface electrode 211 is located on the lower side in the y-direction drawing, and the second surface electrode 212 is located on the upper side in the y-direction drawing. A back electrode 220 is formed on the back surface 202 . In this embodiment, the back electrode 220 is the drain electrode.

A removed region 214 is formed by removing a portion of the electrode layer 231 . The removed region 214 has a shape surrounding the first surface electrode 211 . More specifically, the removal region 214 has a portion extending parallel to each other along the four sides of the semiconductor element 200 and a portion positioned across a relatively large area to surround the first surface electrode 211 . there is The first surface electrode 211 and the second surface electrode 212 are insulated by such an annular removed region 214 .

A peripheral region of the second surface electrode 212 is an active region 216 . A MOSFET 217 is built into the active region 216 at a portion inward from the surface 201 in the z-direction. The MOSFET 217 is composed of a plurality of unit cells 218 arranged in a matrix. Note that the arrangement form of the plurality of unit cells 218 is not limited to the matrix form, and may be, for example, a striped form or a zigzag form.

In this embodiment, one second surface electrode 212 is provided as a source electrode, but the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

FIG. 21 shows the vicinity of the back electrode 220 of the semiconductor element 200 . The semiconductor device 200 of this embodiment has a semiconductor layer 231 and an eutectic layer 232 . The semiconductor layer 231 is a layer in which parts functioning as transistors are built, and is made of Si, for example. The eutectic layer 232 is made of a eutectic of the semiconductor and metal forming the semiconductor layer 231 . In this embodiment, the eutectic layer 232 is made of a eutectic of Si as a semiconductor and Au as a metal. The eutectic layer 232 is formed by stacking a layer made of Au on the semiconductor layer 231 and then heating them for alloying. A back electrode 220 is laminated below the eutectic layer 232 in the z direction. The rear surface electrode 220 is an example of the single metal layer referred to in the present invention, which is formed by depositing an Au layer on the eutectic layer 232, for example. The eutectic layer 232 has a thickness of about 1200 nm, for example. The back electrode 220 as a single metal layer has a thickness of about 600 nm, for example, and is thinner than the eutectic layer 232 . In this embodiment, the surface of the eutectic layer 232 facing downward in the z-direction is defined as the back surface 202 of the semiconductor element 200 .

The main lead 300 has a die pad portion 310 , a main rear terminal portion 320 , a main full thickness portion 330 and a main eaves portion 340 . Main lead 300 is formed by subjecting a metal plate made of Cu to patterning such as etching.

The die pad portion 310 faces upward in the z-direction and is a portion on which the semiconductor element 200 is mounted. In this embodiment, the die pad portion 310 has a rectangular shape with an x-direction dimension of about 0.4 mm and a y-direction dimension of about 0.5 mm. Further, in this embodiment, a main surface plated layer 311 is formed on the die pad portion 310 . Main surface plating layer 311 is formed over the entire die pad portion 310 . The main surface plated layer 311 is made of Ag with a thickness of about 2 μm, for example. In addition, in FIG. 16, the main surface plated layer 311 is half-toned for convenience of understanding.

The main back surface terminal portion 320 faces downward in the z direction opposite to the die pad portion 310 and is used for surface-mounting the semiconductor device 101 . The main back surface terminal portion 320 has a rectangular shape with an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.48 mm. The main back surface terminal portion 320 entirely overlaps the die pad portion 310 when viewed in the z direction, and is included in the die pad portion 310 . In this embodiment, the main lead 300 is formed with a main back plated layer 321 . The main back plated layer 321 is laminated on a portion of the main lead 300 for forming the main back terminal portion 320, and is made of, for example, Ni, Sn, or an alloy thereof with a thickness of about 0.06 mm. In this embodiment, for the sake of convenience, the lower surface of the main back surface plating layer 321 in the z direction is defined as the main back surface terminal portion 320. A terminal portion 320 may be configured.

The main full-thickness portion 330 is a portion extending from the die pad portion 310 to the main back surface terminal portion 320 in the z-direction. In this embodiment, the main full-thickness portion 330 refers to a portion made of Cu excluding the main back surface plating layer 321 and has a thickness of about 0.1 mm. The main full-thickness portion 330 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.48 mm, like the main back terminal portion 320 .

The main eaves portion 340 protrudes from the die pad portion 310 side portion of the main full-thickness portion 330 in the x-direction and the y-direction perpendicular to the z-direction. The main eaves portion 340 is flush with the main full-thickness portion 330 in the z-direction upper end surface. In this embodiment, the main eaves portion 340 has a main front portion 341 , a main side portion 342 and a main rear portion 343 . The thickness of the main eaves portion 340 is, for example, half the thickness of the main full-thickness portion 330, which is about 0.05 mm.

The main front portion 341 protrudes from the main full-thickness portion 330 toward the first minor lead 400 and the second minor lead 500 in the x-direction. In this embodiment, the main front portion 341 has a rectangular shape with an x-direction dimension of approximately 0.21 mm and a y-direction dimension of approximately 0.5 mm.

The main lateral portions 342 protrude from the main full thickness portion 330 in the y-direction. In this embodiment, two main lateral portions 342 are formed. The main side portion 342 has an x-direction dimension of approximately 0.18 mm and a y-direction dimension of approximately 0.01 mm. Also, in this embodiment, the main lead 300 has two main side connecting portions 351 . The main side connecting portions 351 extend from the main side portions 342 of the main eaves 340 and have the same thickness as the main side portions 342 . The y-direction end surface of the main side connecting portion 351 is exposed from the resin package 800 . The main side connecting portion 351 has an x-direction dimension of about 0.1 mm and a y-direction dimension of about 0.04 mm.

A main rear portion 343 projects from the main full-thickness portion 330 on the side opposite to the main front portion 341 . The main rear portion 343 has an x-direction dimension of approximately 0.01 mm and a y-direction dimension of approximately 0.5 mm. In this embodiment, the main lead 300 has two main rear connections 352 . The main rear connection portion 352 extends from the main rear portion 343 of the main canopy portion 340 and is the same thickness as the main rear portion 343 . The x-direction end surface of the main rear connecting portion 352 is exposed from the resin package 800 . The main rear link 352 has an x-direction dimension of approximately 0.04 mm and a y-direction dimension of approximately 0.1 mm.

Due to the configuration described above, in this embodiment, the main full-thickness portion 330 is entirely surrounded by the main eaves portion 340 when viewed in the z direction. Moreover, the z-direction upper surfaces of the main full-thickness portion 330 and the main eaves portion 340 are the die pad portion 310 , and the main surface plated layer 311 overlaps all of the main full-thickness portion 330 and the main eaves portion 340 . 18, about half of the semiconductor element 200 overlaps the main full-thickness portion 330 when viewed in the z-direction, and about half of the semiconductor element 200 overlaps the main front portion 341 of the main eaves portion 340. As shown in FIG. there is The first surface electrode 211 as the gate electrode overlaps the main full-thickness portion 330 , and the second surface electrode 212 as the source electrode overlaps the main front portion 341 of the main eaves portion 340 .

As shown in FIG. 21, a semiconductor element 200 has a back electrode 220 bonded to a die pad portion 310 (main surface plating layer 311). Specifically, the back electrode 220 as a single metal layer is directly bonded to the die pad portion 310 (main surface plated layer 311) by, for example, thermocompression bonding. In this thermocompression bonding, only heat and pressure are applied without vibration.

The first sub-lead 400 is spaced apart in the x-direction with respect to the main lead 300, and includes a first wire bonding portion 410, a first sub-back surface terminal portion 420, a first sub-thickness portion 430 and a first sub-lead. It has an eaves portion 440 . First sub-lead 400 is formed by subjecting a metal plate made of Cu to patterning such as etching.

The first wire bonding portion 410 faces upward in the z-direction and is a portion to which the first wire 600 is bonded. In this embodiment, the first wire bonding portion 410 has a rectangular shape with an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.2 mm. Further, in this embodiment, the first sub-surface plated layer 411 is formed on the first wire bonding portion 410 . The first sub-surface plated layer 411 is formed over the entire first wire bonding portion 410 . The first sub-surface plated layer 411 is made of Ag with a thickness of about 2 μm, for example. In addition, in FIG. 16, the first sub-surface plated layer 411 is half-toned for convenience of understanding.

The first sub-back surface terminal portion 420 faces downward in the z direction opposite to the first wire bonding portion 410 and is used for surface-mounting the semiconductor device 101 . The first sub-back surface terminal portion 420 has a rectangular shape with an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm.
The first sub-back surface terminal portion 420 entirely overlaps with the first wire bonding portion 410 when viewed in the z direction, and is included in the first wire bonding portion 410 . In this embodiment, the first sub-lead 400 is formed with the first sub-back plated layer 421 . The first sub-back surface plating layer 421 is laminated on a portion of the first sub-lead 400 for forming the first sub-back surface terminal portion 420, and has a thickness of about 0.06 mm. Made of alloy. In this embodiment, for the sake of convenience, the z-direction lower surface of the first sub-back surface plating layer 421 is defined as the first sub-back surface terminal portion 420. For example, in a configuration without the first sub-back surface plating layer 421, the Cu The first sub-back surface terminal portion 420 may be configured by a portion consisting of .

The first sub full-thickness portion 430 is a portion extending from the first wire bonding portion 410 to the first sub back terminal portion 420 in the z-direction. In this embodiment, the first sub full thickness portion 430 refers to a portion made of Cu excluding the first sub back plated layer 421 and has a thickness of about 0.1 mm. The first sub full-thickness portion 430 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm, like the first sub back terminal portion 420 .

The first sub eaves portion 440 protrudes in the x direction and the y direction perpendicular to the z direction from the first wire bonding portion 410 side portion of the first sub full thickness portion 430 . The first sub eaves portion 440 is flush with the first sub full-thickness portion 430 at its z-direction upper end surface. In this embodiment, the first secondary eaves portion 440 has a first secondary front portion 441 , a first secondary side portion 442 and a first secondary rear portion 443 . The thickness of the first sub eaves portion 440 is, for example, half the thickness of the first sub full thickness portion 430, which is about 0.05 mm.

The first minor front portion 441 protrudes from the first minor full thickness portion 430 toward the main lead 300 in the x-direction. In this embodiment, the first secondary front portion 441 has an x-direction dimension of approximately 0.01 mm and a y-direction dimension of approximately 0.2 mm.

The first minor side portion 442 protrudes from the first minor full thickness portion 430 in the y direction. In this embodiment, two first secondary side portions 442 are formed. In FIG. 18, the first sub-side portion 442 positioned on the upper side in the y-direction protrudes toward the second sub-lead 500, and has an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.06 mm. be. The first sub-side portion 442 located at the bottom in the y-direction view has a y-direction x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.01 mm. Also, in this embodiment, the first sub lead 400 has a first sub side connecting portion 451 . The first secondary side connecting portion 451 extends downward in the y-direction view in FIG. ing. The y-direction end surface of the first secondary side connecting portion 451 is exposed from the resin package 800 . The first secondary side connecting portion 451 has an x-direction dimension of about 0.1 mm and a y-direction dimension of about 0.04 mm.

The first secondary rear portion 443 protrudes from the first secondary full-thickness portion 430 to the side opposite to the first secondary front portion 441 . The first sub-rear portion 443 has an x-direction dimension of approximately 0.01 mm and a y-direction dimension of approximately 0.14 mm. In this embodiment, the first secondary lead 400 has a first secondary rear connecting portion 452 . The first secondary rear connecting portion 452 extends from the first secondary rearward portion 443 of the first secondary eaves portion 440 and has the same thickness as the first secondary rearward portion 443 . The x-direction end face of the first secondary rear connecting portion 452 is exposed from the resin package 800 . The first secondary rear connecting portion 452 has an x-direction dimension of about 0.04 mm and a y-direction dimension of about 0.1 mm.

Due to the configuration described above, in the present embodiment, the entire first secondary full-thickness portion 430 is surrounded by the first secondary eaves portion 440 when viewed in the z direction. In addition, the z-direction upper surfaces of the first sub-full-thickness portion 430 and the first sub-eaves portion 440 are the first wire-bonding portions 410, and the first sub-surface plated layer 411 is formed on the first sub-full-thickness portion 430 and the first sub-eaves portion 440. It overlaps all of the first secondary eaves portion 440 .

The second sub-lead 500 is arranged side by side with the first sub-lead 400 in the y-direction and spaced apart from the main lead 300 in the x-direction. 520 , a second secondary full thickness portion 530 and a second secondary eaves portion 540 . The second sub-lead 500 is formed by subjecting a metal plate made of Cu to patterning such as etching.

The second wire bonding portion 510 faces upward in the z-direction and is a portion to which the second wire 700 is bonded. In this embodiment, the second wire bonding portion 510 has a rectangular shape with an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.2 mm. Further, in this embodiment, a second secondary surface plated layer 511 is formed on the second wire bonding portion 510 . The second sub-surface plating layer 511 is formed over the entire area of the second wire bonding portion 510 . The second sub-surface plated layer 511 is made of Ag with a thickness of about 2 μm, for example. In addition, in FIG. 16, the second sub-surface plated layer 511 is half-toned for convenience of understanding.

The second sub-back surface terminal portion 520 faces downward in the z-direction opposite to the second wire bonding portion 510 and is used for surface-mounting the semiconductor device 101 . The second sub-back surface terminal portion 520 has a rectangular shape with an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm. The second sub-back surface terminal portion 520 entirely overlaps with the second wire bonding portion 510 when viewed in the z direction, and is included in the second wire bonding portion 510 . In this embodiment, the second sub-lead 500 is formed with a second sub-back plated layer 521 . The second sub-back surface plating layer 521 is laminated on a portion of the second sub-lead 500 for forming the second sub-back surface terminal portion 520, and has a thickness of about 0.06 mm. Made of alloy. In this embodiment, for the sake of convenience, the z-direction lower surface of the second sub-back surface plating layer 521 is defined as the second sub-back surface terminal portion 520. For example, in a configuration without the second sub-back surface plating layer 521, the Cu The second sub-back surface terminal portion 520 may be configured by a portion consisting of .

The second sub full thickness portion 530 is a portion extending from the second wire bonding portion 510 to the second sub back surface terminal portion 520 in the z direction. In this embodiment, the second sub full thickness portion 530 refers to a portion made of Cu excluding the second sub back plated layer 521 and has a thickness of about 0.1 mm. The second sub full-thickness portion 530 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm, like the second sub back terminal portion 520 .

The second sub eaves portion 540 protrudes from the second wire bonding portion 510 side portion of the second sub full thickness portion 530 in the x direction and the y direction perpendicular to the z direction. The second sub eaves portion 540 is flush with the second sub full-thickness portion 530 in the z-direction upper end surface. In this embodiment, the second secondary eaves portion 540 has a second secondary front portion 541 , a second secondary side portion 542 and a second secondary rear portion 543 . The thickness of the second sub eaves portion 540 is, for example, half the thickness of the second sub full thickness portion 530, which is about 0.05 mm.

The second minor front portion 541 protrudes from the second minor full thickness portion 530 toward the main lead 300 in the x-direction. In this embodiment, the second minor front portion 541 has an x-direction dimension of approximately 0.01 mm and a y-direction dimension of approximately 0.2 mm.

The second minor side portion 542 protrudes from the second minor full thickness portion 530 in the y direction. In this embodiment, two second secondary side portions 542 are formed. In FIG. 18, the second sub-side portion 542 located at the bottom in the y-direction view protrudes toward the first sub-lead 400, and has a dimension in the x-direction of about 0.2 mm and a dimension in the y-direction of about 0.06 mm. be. The second secondary side portion 542 located on the upper side in the y-direction view has an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.01 mm. Also, in this embodiment, the second sub lead 500 has a second sub side connecting portion 551 . The second secondary side connecting portion 551 extends upward in the y-direction view in FIG. ing. The y-direction end face of the second secondary side connecting portion 551 is exposed from the resin package 800 . The second secondary side connecting portion 551 has an x-direction dimension of about 0.1 mm and a y-direction dimension of about 0.04 mm.

The second secondary rear portion 543 protrudes from the second secondary full-thickness portion 530 to the side opposite to the second secondary front portion 541 . The second minor rear portion 543 has an x-direction dimension of approximately 0.01 mm and a y-direction dimension of approximately 0.14 mm. In this embodiment, the second secondary lead 500 has a second secondary rear connecting portion 552 . The second secondary rear connecting portion 552 extends from the second secondary rear portion 543 of the second secondary eaves portion 540 and has the same thickness as the second secondary rear portion 543 . The x-direction end surface of the second secondary rear connecting portion 552 is exposed from the resin package 800 . The second secondary rear connecting portion 552 has an x-direction dimension of about 0.04 mm and a y-direction dimension of about 0.1 mm.

Due to the configuration described above, in the present embodiment, the second secondary full-thickness portion 530 is entirely surrounded by the second secondary eaves portion 540 when viewed in the z-direction. In addition, the z-direction upper surfaces of the second sub-full-thickness portion 530 and the second sub-eaves portion 540 are the second wire-bonding portions 510, and the second sub-surface plated layer 511 is the second sub-full-thickness portion 530 and the second sub-eaves portion 540. It overlaps all of the second secondary eaves portion 540 .

First wire 600 is joined to first surface electrode 211 of semiconductor element 200 and first wire bonding portion 410 of first sub-lead 400 , and has first bonding portion 610 and second bonding portion 620 . The first wire 600 is made of Au with a diameter of about 20 μm.

First bonding portion 610 is bonded to first wire bonding portion 410 of first sub-lead 400 and has a crown-shaped lump portion. Second bonding portion 620 is bonded to first surface electrode 211 of semiconductor element 200 via first bump 630 . The second bonding portion 620 has a tapered shape in which the z-direction thickness decreases toward the tip. The first bump 630 is a portion of the first bonding portion 610 similar to the lump portion. In this embodiment, the volume of the first bump 630 is slightly smaller than the bulk portion of the first bonding portion 610 .

Second wire 700 is joined to second surface electrode 212 of semiconductor element 200 and second wire bonding portion 510 of second sub-lead 500 , and has first bonding portion 710 and second bonding portion 720 . The second wire 700 is made of Au with a diameter of about 20 μm.

First bonding portion 710 is bonded to second wire bonding portion 510 of second sub-lead 500 and has a crown-shaped lump portion. Second bonding portion 720 is bonded to second surface electrode 212 of semiconductor element 200 via second bump 730 . The second bonding portion 720 has a tapered shape in which the z-direction thickness decreases toward the tip. The second bump 730 is a portion similar to the lump portion of the first bonding portion 710 . In this embodiment, the second bump 730 has a slightly smaller volume than the bulk portion of the first bonding portion 710 .

Resin package 800 covers semiconductor element 200 and parts of main leads 300, first sub-leads 400 and second sub-leads 500, and is made of, for example, black epoxy resin. In addition, the resin package 800 is arranged such that all of the main back terminal portion 320 of the main lead 300, the first sub back terminal portion 420 of the first sub lead 400, and the second sub back terminal portion 520 of the second sub lead 500 are arranged in the z direction. It is exposed on the lower side. Further, in the present embodiment, the distance between the z-direction upper ends of the first wires 600 and the second wires 700 and the z-direction upper end of the resin package 800 is approximately 50 μm.

Next, an example of a method for manufacturing the semiconductor device 101 will be described below with reference to FIGS. 26 to 33. FIG.

26 to 32, the process of bonding the first wire 600 will be mainly described, but the second wire 700 is also bonded by the same process. First, as shown in FIG. 26, the semiconductor element 200 is bonded to the main lead 300 . At this time, manufacturing efficiency can be improved by using a lead frame in which a plurality of main leads 300, first sub leads 400, and second sub leads 500 are connected. A capillary Cp is prepared and the wire 601 is exposed from its tip. The wire 601 is made of Au with a diameter of about 20 μm. A ball 602 is formed at the tip of the wire 601 by generating a spark just above the first surface electrode 211 of the semiconductor element 200 .

Next, as shown in FIG. 27, the ball 602 is bonded to the first surface electrode 211 of the semiconductor element 200 by lowering the capillary Cp. Then, the capillary Cp is raised while the wire 601 is fixed to the capillary Cp. Thereby, a first bump 630 is formed on the first surface electrode 211 as shown in FIG.

Next, as shown in FIG. 29, a spark is generated directly above the first wire bonding portion 410 of the first sub-lead 400 to form a ball 602 again at the tip of the wire 601 . Next, as shown in FIG. 30, the ball 602 is bonded to the first wire bonding portion 410 of the first sub-lead 400 by lowering the capillary Cp.

Next, the capillary Cp is moved as shown in FIG. 31 without fixing the wire 601 to the capillary Cp. As a result, the first bonding portion 610 is first formed. Also, the tip of the capillary Cp is pressed against the first bump 630 . At this time, the wire 601 is sandwiched between the capillary Cp and the first bump 630 . Also, for example, heat and vibration may be applied via a support base (not shown) that holds the main lead 300 . Then, the capillary Cp is separated from the semiconductor element 200 while the wire 601 is fixed to the capillary Cp. Thereby, a second bonding portion 620 is formed. FIG. 32 is an enlarged image of the second bonding portion 620 and the first bump 630 photographed from above in the z direction. As shown in the drawing, the second bonding portion 620 having a slightly widened shape is bonded onto the first bump 630 having a circular shape in plan view.

After that, the bonding process of the second wire 700 is performed together with the bonding process of the first wire 600 . For example, black epoxy resin is used to cover semiconductor element 200, main lead 300, first sub-lead 400 and second sub-lead 500, and first wire 600 and second wire 700. to form a plate-shaped resin member. FIG. 33 shows the above lead frame, semiconductor element 200, first wire 600 and second wire 700, which are covered with the resin member (not shown). Then, the semiconductor device 101 shown in FIGS. 16 to 24 is obtained by collectively cutting the resin member and the lead frame along the cutting line CL in the drawing.

Next, operation of the semiconductor device 101 will be described.

According to this embodiment, the die pad portion 310 and the semiconductor element 200 overlap both the main full-thickness portion 330 and the main eaves portion 340 when viewed in the z-direction. The main eaves portion 340 exhibits a function of increasing the bonding strength between the main lead 300 and the resin package 800 . It is possible to prevent the main lead 300 from excessively protruding from the semiconductor element 200 while improving the bonding strength. This contributes to reducing the size of the semiconductor device 101 when viewed in the z direction. Moreover, at least one of the first surface electrode 211 and the second surface electrode 212 overlapping the main eaves portion 340 is advantageous in reducing the z-direction size of the semiconductor device 101 . Second bonding portion 620 of first wire 600 is bonded to first surface electrode 211 via first bump 630 , and second bonding portion 720 of second wire 700 is bonded to second surface electrode 212 via second bump 730 . The z-direction height of the first wire 600 and the second wire 700 can be reduced. This contributes to reducing the height of the semiconductor device 101 in the z direction. Therefore, according to this embodiment, the size of the semiconductor device 101 can be reduced.

Since the first surface electrode 211 as the gate electrode is spaced further from the first sub-lead 400 and the second sub-lead 500 than the second surface electrode 212 as the source electrode, the length of the first wire 600 is can be longer than the second wire 700 . A longer first wire 600 tends to increase the bonding strength particularly at the second bonding portion 620 . Generally, the first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of the semiconductor layer 231 with an insulating layer (not shown) interposed therebetween. Such a first surface electrode 211 is relatively difficult to improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as a source electrode is often connected to metal portions filled in a plurality of trenches (vertical holes) formed in the semiconductor layer 231 . With such a configuration, the second surface electrode 212 relatively easily improves the bonding strength of wire bonding. Therefore, bonding the first wire 600, which tends to increase the bonding strength, to the first surface electrode 211 serving as the gate electrode, which is likely to have relatively insufficient bonding strength, is advantageous in avoiding problems such as wire peeling. .

As shown in FIGS. 27 and 31, the first front surface electrode 211 as a gate electrode is likely to have relatively insufficient bonding strength due to the fact that the first front surface electrode 211 overlaps the main full-thickness portion 330 when viewed in the z-direction. can be pressed against the capillary Cp more reliably. On the other hand, the size of the semiconductor device 101 viewed in the z direction is reduced by arranging the second surface electrode 212 as the source electrode, which relatively tends to improve the bonding strength, at a position overlapping the main overhang portion 340 viewed in the z direction. be able to.

By having main front portion 341 , main eaves portion 340 can increase the bonding strength between main lead 300 and resin package 800 . In addition, while the semiconductor element 200 is brought close to the first sub-lead 400 and the second sub-lead 500, the main back-surface terminal 320 and the first sub-back-surface terminal 420 and the second sub-back-surface terminal 520 are brought unduly close to each other. can be avoided.

Since main eaves portion 340 has main side portion 342 and main rear portion 343 , the bonding strength between main lead 300 and resin package 800 can be increased. The configuration in which the entire main full-thickness portion 330 is surrounded by the main eaves portion 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800 .

Main side connecting portion 351 and main rear connecting portion 352 properly hold main lead 300 during the manufacturing process of semiconductor device 101 . The y-direction end surface of the main side connecting portion 351 and the x-direction end surface of the main rear connecting portion 352 are exposed from the resin package 800 but are separated from the main rear surface terminal portion 320 . Therefore, the solder for surface-mounting the semiconductor device 101 is less likely to erroneously spread over the y-direction end face of the main side connecting portion 351 and the x-direction end face of the main rear connecting portion 352 .

By forming the main surface plating layer 311 on the die pad portion 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the die pad portion 310 can be increased. Main surface plating layer 311 overlaps all of main eaves portion 340, so that the area that can be used as die pad portion 310 can be expanded.

Since first sub-lead 400 has first sub-eaves portion 440 , the bonding strength between first sub-lead 400 and resin package 800 can be increased. Since first sub eaves portion 440 has first sub front portion 441, the distance between first sub back surface terminal portion 420 and main back surface terminal portion 320 is made unreasonable while increasing the bonding strength with resin package 800. You can avoid getting too close.

Since first sub eaves portion 440 has first sub side portion 442 and first sub rear portion 443 , bonding strength between first sub lead 400 and resin package 800 can be increased. The configuration in which the entire first secondary full-thickness portion 430 is surrounded by the first secondary eaves portion 440 is suitable for increasing the bonding strength between the first secondary lead 400 and the resin package 800 . Since the first sub side portion 442 on the second sub lead 500 side is relatively large, the joint strength is improved and the first sub back surface terminal portion 420 and the second sub back surface terminal portion 520 are not improperly formed. can be avoided from approaching

The first secondary side connecting portion 451 and the first secondary rear connecting portion 452 appropriately hold the first secondary lead 400 during the manufacturing process of the semiconductor device 101 . The y-direction end surface of the first secondary side connecting portion 451 and the x-direction end surface of the first secondary rear connecting portion 452 are exposed from the resin package 800 but are separated from the first secondary rear surface terminal portion 420 . Therefore, the solder for surface-mounting the semiconductor device 101 is less likely to erroneously spread over the y-direction end face of the first secondary side connecting portion 451 and the x-direction end face of the first secondary rear connecting portion 452 .

By forming the first secondary surface plating layer 411 on the first wire bonding portion 410, the bonding strength between the first wire 600 and the first wire bonding portion 410 can be increased.

Since the second sub-lead 500 has the second sub-eaves portion 540, the bonding strength between the second sub-lead 500 and the resin package 800 can be increased. Since the second sub eaves portion 540 has the second sub front portion 541, the distance between the second sub back surface terminal portion 520 and the main back surface terminal portion 320 is made unreasonable while increasing the joint strength with the resin package 800. You can avoid getting too close.

Since second sub eaves portion 540 has second sub side portion 542 and second sub rear portion 543 , bonding strength between second sub lead 500 and resin package 800 can be increased. The configuration in which the entire second secondary full-thickness portion 530 is surrounded by the second secondary eaves portion 540 is suitable for increasing the bonding strength between the second secondary lead 500 and the resin package 800 . Since the second sub side portion 542 on the first sub lead 400 side is relatively large, the joint strength is improved and the second sub back surface terminal portion 520 and the first sub back surface terminal portion 420 are not properly aligned. can be avoided from approaching

The second secondary side connecting portion 551 and the second secondary rear connecting portion 552 appropriately hold the second secondary lead 500 during the manufacturing process of the semiconductor device 101 . The y-direction end surface of the second secondary side connecting portion 551 and the x-direction end surface of the second secondary rear connecting portion 552 are exposed from the resin package 800 but are separated from the second secondary rear surface terminal portion 520 . Therefore, the solder for surface-mounting the semiconductor device 101 is less likely to erroneously spread over the y-direction end face of the second secondary side connecting portion 551 and the x-direction end face of the second secondary rear connecting portion 552 .

By forming the second secondary surface plating layer 511 on the second wire bonding portion 510, the bonding strength between the second wire 700 and the second wire bonding portion 510 can be increased.

In bonding the semiconductor element 200 and the die pad portion 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly bonded to the die pad portion 310, and vibration is not applied during the bonding. With such a configuration, it is not necessary to set a marginal area in consideration of vibration in the area of the main lead 300 located around the semiconductor element 200 . This is advantageous for miniaturization of the semiconductor device 101 .

FIG. 34 is an X-ray image of the semiconductor device 101. FIG. As shown in FIG. 16, when the main lead 300, the first sub-lead 400 and the second sub-lead 500 are patterned by etching, the boundary between the main full-thickness portion 330 and the main eaves portion 340 is as shown in FIG. 24 are not formed, and curved surfaces are formed. Similarly, the boundary between the first sub-full-thickness portion 440 and the first sub-eaves portion 440 in the first sub-lead 400 or the boundary between the second sub-full-thickness portion 540 and the second sub-eaves portion 540 in the second sub-lead 500 The boundary also becomes a curved surface. This is because even if the design intended for the forms shown in FIGS. 16 to 24 is used, the above-described curved surface is inevitably formed in the etching process when the semiconductor device 101 has the above-described very small configuration. .

FIG. 35 shows a semiconductor device according to the fourth embodiment of the invention. In addition, in the same figure, the same code|symbol as the said embodiment is attached|subjected to the same or similar element as the said embodiment.

In this embodiment, the first surface electrode 211 overlaps both the main full-thickness portion 330 and the main eaves portion 340 when viewed in the z-direction. The first bump 630 and the second bonding portion 620 of the first wire 600 overlap both the main full-thickness portion 330 and the main eaves portion 340 when viewed in the z-direction. In the figure, the first bump 630 and the second bonding portion 620 of the first wire 600 are overlapped by a dashed line extending in the y direction. This dashed line is the boundary between the main full-thickness portion 330 and the main eaves portion 340 as viewed in the z-direction. Such an embodiment can also reduce the size of the semiconductor device 102 .

A semiconductor device according to the present invention is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present invention can be changed in various ways.

The semiconductor element referred to in the present invention is not limited to a transistor, and various semiconductor elements having a first surface electrode and a second surface electrode can be used.

101 semiconductor device 102 semiconductor device 200 semiconductor element 201 front surface 202 rear surface 211 first surface electrode 212 second surface electrode 220 rear electrode 231 semiconductor layer 232 eutectic layer 300 main lead 310 main lead main surface 311 main surface plating layer 320 main lead rear surface 330 Main full-thickness portion 340 Main eaves portion 341 Main front portion 342 Main side portion 343 Main rear portion 351 Main side connection portion 352 Main rear connection portion 400 First auxiliary lead 410 First auxiliary lead main surface 411 First auxiliary surface Plating layer 420 First secondary lead rear surface 430 First secondary full thickness part 440 First secondary eaves part 441 First secondary front part 442 First secondary inner part 460 First secondary extension part 461 First secondary rear part 462 First Secondary side portion 481 First secondary lead end surface 482 First secondary lead side surface 500 Second secondary lead 510 Second secondary lead main surface 511 Second secondary surface plated layer 520 Second secondary lead back surface 530 Second secondary full thickness portion 540 Second secondary eaves portion 541 Second secondary front portion 542 Second secondary inner portion 560 Second secondary extension portion 561 Second secondary rear portion 562 Second secondary side portion 581 Second secondary lead end surface 582 Second secondary lead side surface 600 First wire 610 First bonding portion 620 Second bonding portion 630 First bump 700 Second wire 710 First bonding portion 720 Second bonding portion 730 Second bump 800 Resin package 801 Resin main surface 802 Resin back surface 803 First resin side surface 804 Second resin side surface 805 first resin end face 806 second resin end face 901 tape Ct1 line Ct2 line x direction y direction z thickness direction 214 removed region 216 active region 217 MOSFET
218 unit cell 220 back electrode (single metal layer)
231 semiconductor layer 232 eutectic layer 300 main lead 310 die pad portion 311 main surface plating layer 320 main back surface terminal portion 321 main rear surface plating layer 330 main full thickness portion 340 main overhang portion 341 main front portion 342 main side portion 343 main rear portion 351 Main side connecting portion 352 Main rear connecting portion 400 First sub lead 410 First wire bonding portion 411 First sub surface plating layer 420 First sub back surface terminal portion 421 First sub back surface plating layer 430 First sub full thickness portion 440 First sub eaves portion 441 First sub front portion 442 First sub side portion 443 First sub rear portion 451 First sub side connection portion 452 First sub rear connection portion 500 Second sub lead 510 Second wire bonding Part 511 Second sub-surface plating layer 520 Second sub-back terminal part 521 Second sub-back plating layer 530 Second sub full thickness part 540 Second sub eaves part 541 Second sub front part 542 Second sub side part 543 2nd secondary rear part 551 2nd secondary side connection part 552 2nd secondary rear connection part 600 1st wire 610 1st bonding part 620 2nd bonding part 630 1st bump 700 2nd wire 710 1st bonding part 720 2nd bonding part 730 2nd Bump 800 Resin package Cp Capillary 601 Wire

Claims (10)

a transistor element having a gate electrode, a source electrode and a drain electrode;
a main lead on which said transistor element is disposed and in communication with said drain electrode of said transistor element;
a first sub-lead spaced apart from the main lead and conducting with the gate electrode of the transistor element;
a second sub-lead spaced apart from the main lead and the first sub-lead and conducting to the source electrode of the transistor element;
a resin package covering the transistor element, the main lead, the first sub-lead and the second sub-lead and having a rectangular shape when viewed in the thickness direction of the transistor element;
The resin package has a first surface having a normal direction parallel to the thickness direction, a second surface orthogonal to the first surface, and a third surface orthogonal to the first surface and the second surface. have
the main lead, the first sub-lead and the second sub-lead exposed from the first surface of the resin package;
the main lead has a first portion exposed from the second surface of the resin package,
the first sub-lead has a second portion exposed from the second surface of the resin package and a third portion exposed from the third surface of the resin package;
the second sub-lead has a fourth portion exposed from the third surface of the resin package,
The maximum dimension in the thickness direction of the second part is larger than the maximum dimension in the thickness direction of the first part,
The semiconductor device, wherein the maximum dimension in the thickness direction of the fourth part is the same as the maximum dimension in the thickness direction of the third part. 2. The semiconductor device according to claim 1, wherein on said second surface, said first portion is separated from said first surface, and said second portion reaches said first surface. 3. The semiconductor device according to claim 2, wherein said third portion and said fourth portion reach said first surface on said third surface. 4. The semiconductor device according to claim 3, wherein the maximum dimension in said thickness direction of said third part and said fourth part is the same as the maximum dimension in said thickness direction of said second part. 5. The semiconductor device according to claim 4, wherein said second portion and said third portion are connected to each other. The resin package has a fourth surface facing away from the second surface,
the main lead has a fifth portion exposed from the fourth surface,
the second sub-lead has a sixth portion exposed from the fourth surface,
6. The semiconductor device according to claim 5, wherein the maximum dimension of said sixth portion in said thickness direction is larger than the maximum dimension of said fifth portion in said thickness direction. 7. The semiconductor device according to claim 6, wherein, on said fourth surface, said fifth portion is separated from said first surface, and said sixth portion reaches said first surface. 8. The semiconductor device according to claim 7, wherein said fourth part and said sixth part are connected to each other. the first sub-lead has a back surface of the first lead exposed from the first surface,
9. The semiconductor device according to claim 8, wherein said second portion and said third portion are connected to the rear surface of said first lead. the second sub-lead has a back surface of the second lead exposed from the first surface,
10. The semiconductor device according to claim 9, wherein said fourth portion and said sixth portion are connected to the back surface of said second lead.

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