JP4137719B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve bonding performance between a pellet and a die pad by preventing diffusion of Si on the surface of a backside electrode. <P>SOLUTION: A gold film 15a is vacuum-evaporated about 0.3 &mu;m on the rear surface of a semiconductor substrate 1 on which a semiconductor element such as a power MISFET is formed. Then, after a gold film 15b is vacuum-evaporated about 0.6 &mu;m, the temperature of the substrate is raised to 435&deg;C for about 40 minutes, and after the substrate is left for a predetermined time, the substrate is cooled for about 40 minutes, thereby alloying the entire of the gold films 15a, 15b or a part thereof on the substrate 1 side with the Si (Au-Si alloying) constituting the substrate. Then a gold film 15c is further vacuum-evaporated about 0.3 &mu;m, and the substrate is cooled. As described above, since film forming is performed for 50% or more (preferably, 75% or more) of the evaporated gold film in total before thermal treatment (alloying), thereby shortening a film forming time thereafter and reducing the diffusion of the Si due to a radiant heat. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device having a gold (Au) wiring on its back surface.
[0002]
[Prior art]
Some semiconductor devices form electrodes on the back surface that are electrically connected to the respective portions of the semiconductor elements formed on the front surface.
[0003]
For example, a back electrode of a small signal MISFET (Metal Insulator Semiconductor Field Effect Transistor) has been developed.
[0004]
[Problems to be solved by the invention]
For example, in the small signal MISFET, the back electrode is configured in order to (1) eliminate the step of placing the gold foil on the pellet to reduce the cost, and (2) eliminate scrubbing during bonding and improve the throughput. A process that can be alloyed in the apparatus during the deposition of gold (Au) is being studied.
[0005]
However, in the developed technology, no measures have been taken regarding the thermal load after the deposition of gold constituting the back electrode.
[0006]
The present inventor is engaged in research and development of small signal MISFETs and power MISFETs, and for these products, for example, a back electrode is formed using a gold film having a thickness of about 0.9 μm.
[0007]
However, regarding these products, poor shear strength was observed in an apparatus that was left for a long time after the formation of the back electrode and an apparatus that was baked with ink marked in the probing process.
[0008]
This shear strength refers to the strength at which a pellet is peeled by applying stress to the pellet from the lateral direction after the semiconductor chip (pellet, tab) is bonded onto the die pad (tab frame).
[0009]
A product with poor shear strength has a higher resistance between the back electrode and the die pad than a good product, and ohmic properties are impaired, and there is a high possibility that electrical characteristics will be poor during sorting.
[0010]
As a result of examination of such defects by the present inventors, in products left for a long time or products subjected to thermal load, Si (silicon) tends to diffuse on the surface of the back electrode, and diffused Si and its oxide are It was found to be an inhibitory film during adhesion with the pellet.
[0011]
In addition, a material having a low shear strength has a small Si residual ratio. That is, when stress is applied to the pellets from the lateral direction and the pellets are peeled off, Si that is a semiconductor constituting the pellets remains on the die pad. However, when the shear strength is low, the back electrode portion is the starting point of peeling, and the area of Si remaining on the die pad is small. The ratio of the area of Si remaining on the die pad to the pellet area is referred to as the Si remaining ratio.
[0012]
Furthermore, the defect is confirmed in a semiconductor substrate having a crystal axis of (100). For example, in the back electrode of the semiconductor substrate having a crystal axis of (111), diffusion of the semiconductor (Si) is not a problem. It seems that the state of crystal growth of the metal (alloy) constituting the back electrode is also involved.
[0013]
An object of the present invention is to prevent the diffusion of a semiconductor, particularly Si, into the surface of the back electrode. Moreover, it exists in improving the adhesiveness of a pellet and a die pad.
[0014]
Another object of the present invention is to improve the reliability of a semiconductor device.
[0015]
The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0017]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a semiconductor element is formed on a surface of a semiconductor substrate, and an electrode including gold (Au) is formed on the back surface of the semiconductor substrate, The forming step includes: (a) forming a first gold film having a thickness of 50% or more of the thickness of the electrode on the back surface of the semiconductor substrate; and (b) after the step (a), And (c) after the step (b), a step of forming a second gold film on the upper portion of the first gold film.
[0018]
A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a semiconductor element is formed on a surface of a semiconductor substrate, and an electrode including gold (Au) is formed on the back surface of the semiconductor substrate, The forming step is performed by roughening the back surface of the semiconductor substrate and then forming a gold film on the top surface.
[0019]
For example, the semiconductor substrate has a crystal axis of (100).
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that in all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the repeated description thereof is omitted.
[0021]
(Embodiment 1)
Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to the drawings. 1 and 2 are cross-sectional views of the main part of the substrate showing the method of manufacturing the semiconductor device of the present embodiment.
[0022]
First, as shown in FIG. 1, a semiconductor substrate 1 on which a semiconductor element such as a power MISFET is formed is prepared.
[0023]
A process for forming the power MISFET will be briefly described.
[0024]
First, a semiconductor substrate (hereinafter simply referred to as a “substrate”) 1 made of, for example, p-type single crystal silicon is prepared, and the substrate 1 is thermally oxidized to provide a clean gate oxide film (gate insulating film) 5 on its surface. Form. Note that element isolation and wells may be formed as necessary. Further, channel implantation is performed in advance to form the channel region 3.
[0025]
Next, a polycrystalline silicon film is formed on the substrate 1 and etched to form the gate electrode 7. Next, n-type impurities are ion-implanted into the substrate 1 on both sides of the gate electrode 7 to form n-type semiconductor regions (source and drain regions) 9.
[0026]
Next, for example, an interlayer insulating film 11 is formed by depositing a silicon oxide film by a CVD method, and a contact hole is formed by appropriately removing the interlayer insulating film 11 on the n-type semiconductor region 9 by etching.
[0027]
Next, a plug 13 is formed by embedding a conductive film on the interlayer insulating film 11 including the inside of the contact hole.
[0028]
Thereafter, a wiring or an insulating film may be formed on the plug 13 as necessary, but the illustration thereof is omitted here. A protective film is formed on the uppermost layer wiring.
[0029]
Thereafter, the front surface of the substrate (power MISFET formation side, protective film side) is the lower side, and the back surface of the substrate is polished to thin the substrate 1. Next, after spin-etching the back surface of the substrate, vacuum baking (heat treatment) is performed.
[0030]
Next, the back electrode 15 is formed on the back surface of the substrate 1. The process of forming the back electrode 15 will be described in detail with reference to FIGS.
[0031]
First, as shown in FIG. 2, a gold film 15a is vacuum-deposited by about 0.3 μm. Next, the gold film 15b is vacuum-deposited to about 0.6 μm. Here, in order to form a gold film with good controllability, a gold film having a total thickness of 0.9 μm was formed by two vacuum depositions, but a 0.9 μm gold film may be formed by one deposition.
[0032]
Next, as shown in FIG. 3, the temperature of the substrate is raised to 435 ° C., for example, over about 40 minutes. Next, after standing at 435 ° C. for about 10 minutes, it is allowed to cool for about 40 minutes. By this heat treatment, all of the gold films 15a and 15b or a part on the substrate 1 side is alloyed (Au—Si alloy) with Si (silicon) constituting the substrate. In FIG. 2, illustration of the alloyed portion is omitted.
[0033]
Next, a gold film 15c is further vacuum-deposited by about 0.3 μm on the gold film 15b and allowed to cool. FIG. 3 is a diagram showing the relationship between the deposition power of the gold film and the deposition time, and the relationship between the heating temperature and the heating time. A is the heating temperature, B is the heating time, C is the thickness of the deposited gold before alloying, and D is the cooling time (same in FIGS. 4 and 10).
[0034]
As described above, according to the present embodiment, since a gold film is deposited to a certain thickness (in this case, 0.9 μm) and then subjected to heat treatment (alloying), Si diffusion can be reduced, which will be described later. Thus, the shear strength of the pellet can be ensured. In this case, the Si residual ratio in the shear test was 98.6%.
[0035]
Here, the thickness of the gold film before the heat treatment (alloying) is desirably 50% or more of the deposited film thickness gauge of the gold film (in this case, 0.3 + 0.9 + 0.3 = 1.2 μm). More preferably, it is 75% or more.
[0036]
On the other hand, when gold was deposited under the conditions shown in FIG. 4, the Si remaining rate in the shear test was low. FIG. 4 is a diagram showing the relationship between the deposition power of the gold film and the deposition time and the relationship between the heating temperature and the heating time in order to show the effect of the present embodiment.
[0037]
That is, as shown in FIG. 4, after the gold film 15a is vacuum-deposited by about 0.3 μm, heat treatment (alloying) is performed, and then the gold film 15b is vacuum-deposited by about 0.3 μm, and the gold film 15c is further formed. When vacuum deposition of about 0.6 μm was performed, the Si remaining rate in the shear test was low.
[0038]
Specifically, after the gold film 15a is vacuum-deposited by about 0.3 μm, the temperature of the substrate is raised to 340 ° C., for example, over about 20 minutes. Next, after standing at 340 ° C. for about 10 minutes, it is allowed to cool for about 20 minutes. By this heat treatment, all of the gold film 15a or part of the substrate 1 side is alloyed (alloyed) with Si (silicon) constituting the substrate.
[0039]
Next, gold films 15b and 15c are further vacuum deposited on the gold film 15a by about 0.3 μm and 0.6 μm, respectively, and allowed to cool. In this case, the Si residual ratio in the shear test was low.
[0040]
Therefore, it can be seen that the diffusion of Si is suppressed by increasing the thickness of the gold film before heat treatment (alloying). Considering this reason, there are the following two points.
[0041]
First, reduction of radiant heat at the time of vapor deposition of the gold film after heat treatment (alloying) can be considered. That is, as shown in FIG. 3, when the gold film 15c is deposited, the heater switch is turned off and no thermal load is applied to the substrate itself, but gold particles evaporate (scatter) on the gold target. Heat is applied to make it easier. It is conceivable that the substrate temperature rises due to the influence of radiant heat from the target, and Si diffuses through the grain boundaries of gold or an alloy of gold and Si.
[0042]
Accordingly, the deposition time of the gold film after heat treatment (alloying) is longer, in other words, the greater the film thickness of the gold film to be deposited after heat treatment (alloying), the more easily Si diffuses due to the influence of radiant heat.
[0043]
On the other hand, in this embodiment, the film formation of 50% or more (more preferably 75% or more) of the total gold film is performed before the heat treatment (alloying), so that the subsequent film formation time can be shortened. Si diffusion due to radiant heat can be reduced.
[0044]
Furthermore, it is considered that the larger the film thickness of the continuous vapor deposition, the smaller the amount of Si diffusing on the surface of the gold film.
[0045]
First, the vapor deposition growth of a gold film from a Si substrate having a crystal axis of (100) is considered to be a Volmer-Weber type growth. 5A to 5D schematically show the growth of the Volmer-Weber type. In the growth of the Volmer-Weber type, as shown in the figure, first, after the gold particles reach the substrate, the surface diffuses and nuclei are formed (a), and gold grows around the nuclei to form islands. Moreover, each island unites (b). Thereafter, individual islands further grow (c), and a plurality of crystal grains (grains) having a grain boundary substantially perpendicular to the substrate are formed (d).
[0046]
During such growth, the energy (chemical potential) of the gold surface is larger during vapor deposition (deposition) than the grain boundaries of grains. Therefore, Au diffuses into the grain boundaries with low energy and relieves stress.
[0047]
However, when the deposition is stopped, the surface energy of Au decreases, and Au boils from the grain boundary.
[0048]
Accordingly, it is considered that Si that diffuses at the grain boundary also diffuses to the grain grain boundary during the vapor deposition and to the surface of the Au film after the vapor deposition is stopped.
[0049]
Therefore, if only a thin Au film is formed before heat treatment (alloying), it is considered that a large amount of Si is boiling on the surface.
[0050]
On the other hand, in the present embodiment, although the vapor deposition is performed twice, a film of 50% or more (more preferably 75% or more) of the total gold film is formed before the heat treatment (alloying). Therefore, Si diffusion can be reduced.
[0051]
Here, the total film thickness is the sum of the film thicknesses of the deposited gold and is approximately the same as the thickness of the back electrode.
[0052]
Thus, after forming the back surface electrode 15 consisting of the gold films 15a, 15b and 15c, a probe test is performed on each chip of the substrate 1 in the wafer state to mark defective chips. A heat treatment (ink bake) is performed to fix the marking ink. Although Si may be diffused during the ink baking, according to the present embodiment, since the diffusion of Si is suppressed in advance, the diffusion of Si during the ink baking can also be reduced.
[0053]
Next, a plurality of semiconductor chips (pellets) 23 are formed by dicing the substrate 1 in a wafer state.
[0054]
Next, as shown in FIGS. 6 and 7, the pellet 23 is bonded onto the lead frame 20. This lead frame is composed of a die pad portion 20a and a lead portion 20b, and silver (Ag) plating 21 is applied to the respective surfaces (see FIG. 7). FIG. 6 is a perspective view of main parts of the substrate showing the method for manufacturing the semiconductor device of the present embodiment, and FIG. 7 is a cross-sectional view of main parts of the substrate showing the method of manufacturing the semiconductor device of the present embodiment. This corresponds to the AA cross section of FIG.
[0055]
While heating the lead frame 20 to 400 ° C. to 460 ° C., the pellet is pressed onto the die pad portion 20a, Si, Au and Ag are eutectic alloyed, and the pellet is welded onto the die pad portion 20a (die bonding). Reference numeral 25 denotes a eutectic alloying part.
[0056]
Next, the pad portion on the surface of the pellet and the lead portion are connected by a wire 27 (wire bonding). The pad portion is a portion where the uppermost layer wiring is exposed from the protective film.
[0057]
After die bonding, for example, a stress is applied to the pellet from the lateral direction to measure the stress at which the pellet peels. Moreover, the peeling trace on the die pad part 20a at the time of peeling is verified.
[0058]
That is, when the pellet peels in the middle of its thickness, the peeling trace becomes Si and the Si remaining rate becomes 100%. On the other hand, when peeling off at the back wiring (15a, 15b, 15c) part, the peeling trace becomes gold and the Si remaining rate becomes 0%. If this Si residual ratio is large, the shear strength increases.
[0059]
When Si or its oxide is deposited on the back electrode surface or the back electrode, these serve as an inhibition film, and the Si residual ratio decreases. FIG. 8 shows the relationship between the Auger analysis strength of the Si and oxygen (O) pellet back surface and the Si wetting rate (residual rate) on the pellet back surface. (A) is a graph about Si, (b) is a graph about oxygen. It can be seen that the surface concentration of Si and oxygen decreases as the Si residual ratio increases. Incidentally, the standard of the Si remaining rate is, for example, 50% or more.
[0060]
Thus, according to the present embodiment, since the diffusion of Si can be suppressed, the Si remaining rate can be increased and the standard can be observed.
[0061]
Next, FIG. 9 shows the relationship between the ink baking temperature and the Auger analysis intensity of Si on the back of the pellet. As shown in the figure, the strength of Si increases as the ink baking temperature rises. Further, when compared with a constant ink baking temperature, the strength of Si is larger when the baking time is longer. The ink bake time was examined for each specification of 70 minutes, 90 minutes and 110 minutes.
[0062]
However, according to the present embodiment, since the diffusion of Si can be suppressed, even if ink baking is performed, the Si remaining rate can be increased and the shear strength can be ensured.
[0063]
Next, the heat treatment (alloying) temperature, the heating rate, etc. will be considered. FIG. 10 is a chart showing the relationship between the heat treatment (alloying) temperature, the heating rate, etc., and the Si residual rate.
[0064]
(A) corresponds to the case of the above embodiment. (B) When the heating time and the cooling time are shortened to 20 minutes, (c) When the heating temperature and the cooling time are shortened to 20 minutes and the heating temperature is lowered to 280 ° C. Indicates. The film thickness of the gold films 15a, 15b and 15c and the timing of heat treatment (alloying) are the same as in the case of (a).
[0065]
In (a), when ink baking was not performed, the Si remaining rate was 98.6%, and when ink baking was performed, the Si remaining rate was 98.7%. That is, according to the back electrode deposition method of the present embodiment, it was possible to increase the Si remaining rate regardless of whether or not ink baking was performed. In this case, the yield was 99.30%, and the VSDF defect rate was 0%. This VSDF is one of the electrical characteristic inspection items in a small signal MISFET using the back electrode as a source electrode, and is a source-drain forward voltage at a certain drain current value. Since a product having a poor shear strength has a higher resistance between the back electrode and the die pad than a good product, the VSDF defect rate is high. That is, this VSDF defect rate is considered to reflect the degree of shear strength defect.
[0066]
In (b), when ink baking was not performed, the Si remaining rate was 97.5%, and when ink baking was performed, the Si remaining rate was 96.3%. Moreover, the yield was 99.10% and the VSDF defect rate was 0%. Therefore, it can be seen that the characteristics of the apparatus are improved in the case of (a) in which the temperature is increased slowly and the cooling time is kept long.
[0067]
In (c), when ink baking was not performed, the Si remaining rate was 98.0%, and when ink baking was performed, the Si remaining rate was 97.7%. Moreover, the yield was 98.70% and the VSDF defect rate was 0%.
[0068]
From these comparative tests, the higher the heating temperature, the better the yield, but in this case, it is better to secure a longer heating and cooling time, raise the temperature slowly, and cool completely. I understand.
[0069]
(Embodiment 2)
In the present embodiment, before forming the back electrode, the back surface of the substrate is roughened to change the growth state of the gold film, thereby reducing the crystal grain boundary that becomes the diffusion path of Si. Note that the steps up to the vacuum baking (heat treatment) after spin etching on the back surface of the substrate 1 are the same as those in the first embodiment, and thus the description thereof is omitted.
[0070]
After the vacuum baking, the back surface of the substrate 1 is roughened. Specifically, the surface is roughened by performing CF ₄ (carbon tetrafluoride) treatment.
[0071]
Next, a gold film 15a is deposited on the back surface of the roughened substrate by about 0.3 μm, for example. At this time, since the back surface of the substrate is roughened, it is considered that the growth direction of the gold film is not affected by the substrate (Si) having a crystal axis of (100) and grows in a random direction.
[0072]
For example, it is considered that the epitaxy relationship of Au when growing on the substrate with the crystal axis (100) is broken, and Au grows in a state close to amorphous.
[0073]
As a result, crystal grain boundaries (paths between dendrites described with reference to FIG. 5) serving as Si diffusion paths are reduced, and Si diffusion can be suppressed.
[0074]
Thereafter, for example, heat treatment (alloying) is performed, and a gold film 15b of about 0.6 μm and a gold film 15c of about 0.3 μm are deposited.
[0075]
The growth of the gold film at this time is also considered to be that Au grows in a state close to amorphous because the epitaxy relationship of the underlying gold film 15a is broken.
[0076]
Thus, according to the present embodiment, the back surface of the substrate is roughened before the growth of the metal constituting the back electrode, and the influence of the crystal axis is reduced, so that the grain boundaries of the growing metal are reduced. In addition, diffusion of the semiconductor constituting the substrate to the surface of the back electrode can be prevented.
[0077]
The present invention made by the inventor has been specifically described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. Needless to say.
[0078]
In particular, in the above-described embodiments, the power MISFET has been described as an example. However, the present invention is not limited to this element, and can be widely applied to semiconductor devices in which the back electrode side of the pellet is bonded to the die pad.
[0079]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0080]
In the formation of a semiconductor device having a back electrode, a first gold film having a thickness of 50% or more of the thickness of the back electrode is formed on the back surface of the semiconductor substrate, and then heat treatment is performed. Since the second gold film is formed, it is possible to prevent the diffusion of the semiconductor, particularly Si, to the surface of the back electrode. As a result, the adhesion between the pellet and the die pad can be improved. In addition, the reliability of the semiconductor device can be improved. In addition, the yield of the semiconductor device can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of main parts of a substrate showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing the relationship between the deposition power and deposition time of a gold film, and the relationship between the heating temperature and the heating time.
FIG. 4 is a diagram showing the relationship between the deposition power and deposition time of a gold film and the relationship between the heating temperature and the heating time in order to show the effect of the first embodiment of the present invention.
FIGS. 5A to 5D are diagrams schematically showing a growth state of a Volmer-Weber type. FIG.
6 is a perspective view of the essential part of the substrate, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention; FIG.
7 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention; FIG.
FIG. 8 is a graph (graph) showing the relationship between the Auger analysis intensity of Si and oxygen (O) on the pellet back surface and the Si wetting rate (residual rate) on the pellet back surface.
FIG. 9 is a graph (graph) showing the relationship between the ink baking temperature and the Auger analysis intensity of Si on the pellet back surface.
FIG. 10 is a chart showing the relationship between the heat treatment (alloying) temperature, the rate of temperature increase, and the Si residual rate.
[Explanation of symbols]
1 Semiconductor substrate (substrate)
3 channel region 5 gate oxide film 7 gate electrode 9 n-type semiconductor region 11 interlayer insulating film 13 plug 15 back electrode 15a gold film 15b gold film 15c gold film 20 lead frame 20a die pad part 20b lead part 21 silver plating 23 pellet 25 eutectic Alloying part 27 wire

Claims (12)

A semiconductor device manufacturing method in which a semiconductor element is formed on a surface of a semiconductor substrate, and an electrode including gold (Au) is formed on a back surface of the semiconductor substrate,
The electrode forming step includes:
(A) forming a first gold film having a thickness of 50% or more of the thickness of the electrode on the back surface of the semiconductor substrate;
(B) after the step (a), performing a heat treatment on the first gold film;
(C) after the step (b), forming a second gold film on the first gold film;
(D) After the step (c), dividing the semiconductor substrate into pieces and forming a semiconductor chip;
(E) welding the semiconductor chip onto a die pad of a lead frame;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device in which a semiconductor element is formed on a surface of a semiconductor substrate containing silicon, and an electrode containing gold is formed on the back surface of the semiconductor substrate,
The electrode forming step includes:
(A) depositing a first gold film constituting the electrode on the back surface of the semiconductor substrate;
(B) After the step (a), heat treatment is performed, and silicon contained in the semiconductor substrate and the first 1 Alloying the gold film;
(C) after the step (b), depositing a second gold film constituting the electrode on the first gold film;
(D) After the step (c), dividing the semiconductor substrate into pieces and forming a semiconductor chip;
(E) welding the semiconductor chip onto a die pad of a lead frame;
Have
The method of manufacturing a semiconductor device, wherein the thickness of the first gold film is 50% or more of the thickness of the electrode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein silver plating is formed on a surface of the lead frame. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the second gold film formed on the back surface of the semiconductor chip is in direct contact with silver plating on the surface of the lead frame. 4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step (e), a eutectic alloy of the second gold film, the silver plating, and silicon in the semiconductor substrate is formed. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor element is a power MISFET. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the thickness of the first gold film is 75% or more of the thickness of the electrode. A method of manufacturing a semiconductor device in which a semiconductor element is formed on a surface of a semiconductor substrate containing silicon, and an electrode containing gold is formed on the back surface of the semiconductor substrate,
The electrode forming step includes:
(A) depositing a first gold film constituting the electrode on the back surface of the semiconductor substrate;
(B) depositing a second gold film constituting the electrode on the first gold film;
(C) after the step (b), performing a heat treatment to alloy the silicon contained in the semiconductor substrate with the first gold film and the second gold film ;
(D) After the step (c), depositing a third gold film constituting the electrode on the second gold film;
(E) After the step (d), the step of separating the semiconductor substrate and forming a semiconductor chip;
(F) welding the semiconductor chip on a die pad of a lead frame;
Have
The total thickness of the first gold film and the second gold film is 50% or more of the thickness of the electrode. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a silver plating is formed on a surface of the lead frame. 10. The method for manufacturing a semiconductor device according to claim 9, wherein in the step (f), a eutectic alloy of the third gold film, the silver plating, and silicon in the semiconductor substrate is formed. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor element is a power MISFET. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the total thickness of the first gold film and the second gold film is 75% or more of the thickness of the electrode.

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