JP2008147294A - Electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized high-performance wide band gap semiconductor electronic device which has an ohmic electrode that is formed on a wide band gap semiconductor layer and that has contact resistance as low as that of a conventional ohmic electrode even when subjected to an annealing process under a high temperature for a short time. <P>SOLUTION: The electronic device has at least one electrode which is formed on a wide band gap compound semiconductor layer formed on a substrate, and at least contains an adhesion layer, an ohmic layer, and an oxidation preventive layer in this order from the side of the wide band gap compound semiconductor layer. Preferably, the electronic device also has a mutual diffusion preventive layer between the ohmic layer and the oxidation preventive layer, and the oxidation preventive layer contains a layer made of gold and a layer made of tungsten in this order. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic device such as a field effect transistor (FET) or a high electron mobility transistor (HEMT) using a wide band gap semiconductor suitable for high power applications.

  Generally, wide band gap semiconductors that can realize a wider band gap than InGaAlP / GaAs compound semiconductors used in red lasers and LEDs, such as diamond, SiC (silicon carbide), ZnSSe (zinc selenide), GaN ( Gallium nitride) -based semiconductors and the like are expected as semiconductor materials for blue light emitting diodes and blue lasers and for electronic devices suitable for use at high power and at high temperatures because the operating voltage can be increased.

  Among these, Group 3-5 GaN (nitride) compound semiconductors such as GaN, AlGaN, InGaN, etc., can be obtained by changing the ratio of Group III elements Ga (gallium), Al (aluminum), In (indium), Since semiconductors with different band gaps (1.8 eV to 6.2 eV) can be easily realized, blue light emitting diodes, blue lasers, high power field effect transistors (FETs), high electron mobility transistors (HEMTs), etc. It has come to be used for electronic devices.

  Since it is necessary to pass a large current in these elements, a technique for obtaining an electrode (ohmic electrode) having a contact resistance between the wide band gap semiconductor and the electrode as low as possible is important.

  For example, in the FET, the source electrode and the gate electrode need to be ohmic electrodes. As an ohmic electrode structure used for a GaN-based semiconductor, for example, in Patent Document 1, an Hf layer of 5 nm, a Ti layer of 30 nm, and an Al layer of 300 nm are stacked on the surface of an n-type gallium nitride compound semiconductor layer, and the temperature is 400 ° C. for 10 minutes. An electrode having a low resistance ohmic characteristic with a contact resistance Rc = 0.31 Ωmm is disclosed by annealing.

  Patent Documents 2 and 3 disclose that an ohmic electrode is obtained by laminating Ti / Al (/ Ti / Au), for example, and annealing at 400 ° C. or more and 1200 ° C. or less.

  Here, in the above document, Al is an ohmic metal for diffusing a part to the semiconductor layer by annealing to form an ohmic electrode. On the other hand, Hf and Ti are adhesion layers for preventing Al, which is an ohmic metal, from being peeled off from the semiconductor, and also functioning to inhibit diffusion so that Al does not diffuse too much into the semiconductor. it is conceivable that.

  However, the conventional electrode structure as described above has a problem that the surface of the electrode becomes rough when annealing is performed at a temperature higher than 400 ° C. When the surface of the electrode is rough, the connection state between the electrode and the external circuit is deteriorated, the contact resistance is increased, and the resistance may be increased when used for a long time. In severe cases, the electrode might be peeled off. Therefore, in order to prevent the surface of the electrode from being rough, it is common to perform annealing for a relatively long time of about 10 minutes while keeping the annealing temperature at a relatively low temperature of 400 ° C.

However, the annealing time of 10 minutes has a problem in mass productivity because the processing time is too long. In addition, in an electronic device such as an FET, an AlGaN layer having a larger band gap must be formed on a GaN layer in order to form a two-dimensional electron gas layer, and an ohmic electrode must be formed on the AlGaN layer. Since an oxide is easily formed on the surface of the semiconductor layer containing Al, it is necessary to increase the annealing temperature. Therefore, an element capable of increasing the annealing temperature and realizing an electrode structure capable of providing a sufficiently low contact resistance with a short annealing process has been desired.
Japanese Patent Laid-Open No. 2001-15452 Japanese Patent No. 2783349 Japanese Patent No. 3154364

  The present invention has been made in view of the above-described problems, and is an electronic device having an ohmic electrode formed on a wide band gap semiconductor layer, which is a conventional ohmic electrode even by annealing at a high temperature for a short time. An object of the present invention is to provide a small and high-performance wide bandgap semiconductor electronic device having an ohmic electrode having a low contact resistance.

  The electronic device of the present invention is formed on a layer made of a wide bandgap compound semiconductor formed on a substrate, and at least an adhesion layer, an ohmic layer, and an antioxidant layer from the side of the layer made of the wide bandgap compound semiconductor Is an electronic device having at least one electrode including these in this order.

  Here, the layer made of the wide band gap compound semiconductor is preferably formed on a silicon substrate.

The wide band gap compound semiconductor is preferably a compound semiconductor composed of In _a Al _b Ga _c B _d N (a + b + c + d = 1, 0 ≦ a, b, c, d ≦ 1).

  The adhesion layer is made of Hf or Ti, the ohmic layer is made of Al, and the antioxidant layer has a single layer structure made of Au, a single layer structure made of W, or made of Au. A two-layer structure of a layer and a layer made of W is preferable.

  The electronic device of the present invention preferably has an interdiffusion prevention layer made of Hf, Ti, Mo, Ni, Nb or Pt between the ohmic layer and the antioxidant layer.

  The thickness of the adhesion layer is preferably smaller than the thickness of the mutual diffusion prevention layer, the thickness of the ohmic layer is preferably larger than the thickness of the mutual diffusion prevention layer, and the thickness of the antioxidant layer made of Au The thickness is preferably larger than the thickness of the mutual diffusion preventing layer.

  In the electronic device of the present invention, the thickness of the portion of the layer made of the wide band gap compound semiconductor where the electrode including at least the adhesion layer, the ohmic layer, and the antioxidant layer in this order is formed is It may be smaller than the thickness of the portion not formed.

The wide band gap compound semiconductor is a compound semiconductor made of Al _x Ga _1-x N (0 <x ≦ 1), and the layer made of the wide band gap compound semiconductor is a GaN layer formed on a silicon substrate. Preferably formed on top.

  In the case where the antioxidant layer has a two-layer structure of a layer made of Au and a layer made of W, the layer made of Au and the layer made of W are the side of the layer made of the wide band gap compound semiconductor. Therefore, the layers are preferably laminated in this order.

  Furthermore, in the electronic device of the present invention, the antioxidant layer may include a layer made of W, and the antioxidant layer made of W may be a layer to which a compressive stress is applied.

  The antioxidant layer may be formed so as to cover at least the side surfaces of the adhesion layer and the ohmic layer.

  The electronic device of the present invention is an electronic device having a plurality of electrodes, a dielectric layer covering the plurality of electrodes, one or more surface pad electrodes formed on the surface of the dielectric layer, Each of the surface pad electrodes is preferably electrically connected to at least one of the plurality of electrodes via a first via hole.

  Here, the dielectric layer is preferably made of a dielectric having a relative dielectric constant of 2 or more. The surface pad electrode is preferably made of Al.

  The electronic device of the present invention further includes one or a plurality of back surface pad electrodes formed on the surface of the substrate opposite to the side on which the layer made of the wide band gap compound semiconductor is formed, Each of the pad electrodes is preferably configured to be electrically connected to at least one of the plurality of electrodes through the second via hole. Here, Au is preferably used as the main component constituting the back electrode. More preferably, the substrate is a silicon substrate, the front surface pad electrode is made of Al, and the main component constituting the back surface pad electrode is Au.

  According to the present invention, an electronic device including an ohmic electrode having a contact resistance as low as that of a conventional ohmic electrode of about 0.38 Ω · mm is provided even by annealing at a high temperature for a short time. Since the electronic device of the present invention can anneal electrodes at a high temperature in a short time, the production process can be greatly shortened. Such an electronic device of the present invention can be suitably used not only for high power but also as any other electronic device including an electrode that requires ohmic characteristics.

  Hereinafter, the present invention will be described in more detail with reference to embodiments. The electronic device of the present invention includes at least one ohmic electrode having a specific structure. Therefore, in the following, the electrode structure which is a characteristic part of the electronic device of the present invention will be described first, and then the electronic device will be described.

<First Embodiment>
(Structure of ohmic electrode)
FIG. 1 is a schematic cross-sectional view of an ohmic electrode according to a first embodiment of the present invention. As shown in FIG. 1, the ohmic electrode 101 of the present embodiment is formed on a layer 107 made of a wide band gap compound semiconductor, and includes an adhesion layer 102, an ohmic layer 103, a first antioxidant layer 105, and a second layer. And an anti-diffusion layer 104 between the ohmic layer 103 and the first anti-oxidation layer 105. A layer 107 made of AlGaN, which is a wide band gap compound semiconductor, is formed on an n-type or non-doped GaN layer 108 formed on a silicon (Si) substrate 110 via an AlN buffer layer 109. The electrode having such a configuration has a contact resistance as low as that of a conventional ohmic electrode even by annealing at a high temperature for a short time.

  Note that the substrate is not limited to Si, and may be a crystal that can form the layer 107 made of a wide band gap compound semiconductor. Examples of such include sapphire, SiC, GaN, and the like. The buffer layer 109 is not limited to the AlN layer, and an AlGaN layer, a GaN-based superlattice layer, or the like can be used.

As the wide band gap compound semiconductor for forming the layer 107 made of the wide band gap compound semiconductor, AlGaN is illustrated in FIG. 1, but is not limited thereto. For example, diamond, SiC (silicon carbide), ZnSSe is used. (Zinc selenide) -based semiconductors, GaN (gallium nitride) -based semiconductors, and the like can be used. In particular, In _a Al _b Ga _c B _d N (Al _x Ga _1-x N (0 <x ≦ 1)) a + b + c + d = 1, 0 ≦ a, b, c, d ≦ 1) is preferably used.

  Here, the adhesion layer 102 is formed so that the ohmic layer 103 is not peeled off, and for example, Hf (hafnium), Ti (titanium), or the like can be used.

  For the ohmic layer 103, Al (aluminum) having a low resistance can be suitably used. It is possible to use Au (gold) if only the resistivity is taken into account, but since Au is more easily diffused, it is necessary to control the annealing temperature and time for obtaining an ohmic electrode more precisely. Moreover, when using a p-type Si substrate, you may form by vapor-depositing Au and Zn (zinc).

  The first antioxidant layer 105 is provided to prevent the ohmic layer 103 from being oxidized. The first antioxidant layer 105 is not particularly limited, but Au that is not oxidizable can be suitably used. The first antioxidant layer 105 can prevent the ohmic layer 103 made of highly oxidizable Al from being oxidized in the device manufacturing process. Here, when the first antioxidant layer 105 is laminated on the ohmic layer 103, if Au is directly deposited on the Al layer, mutual diffusion occurs at the time of annealing, so that an inappropriate alloy as an electrode metal is formed. As in the embodiment, the interdiffusion prevention layer 104 is preferably interposed between the ohmic layer 103 and the first antioxidant layer 105. As the interdiffusion prevention layer 104, for example, Ti, Mo (molybdenum), Nb (niobium), Ni, Pt, etc. can be used in addition to Hf. The interdiffusion prevention layer 104 is provided as necessary, and may be omitted.

  In the present embodiment, the second antioxidant layer 106 is formed on the first antioxidant layer 105. In general, a smooth electrode surface after annealing is important for reducing parasitic resistance of an electronic device and improving long-term reliability. However, an Au layer whose surface is the first antioxidant layer 105 is used. In this case, the surface of the electrode before annealing is flat, but after annealing, a pattern due to unevenness is visually observed. This is considered to be caused by the re-evaporation of Au due to annealing at a high temperature. Therefore, as in this embodiment, it is preferable to form the second antioxidant layer 106 on the first antioxidant layer 105 to ensure the flatness of the electrode surface after annealing. As the second antioxidant layer 106, W (tungsten) having a high melting point, an alloy of W and Ti, Ta (tantalum), Mo (molybdenum), or the like can be preferably used. In the present embodiment, both the first antioxidant layer 105 and the second antioxidant layer 106 are provided. However, the second antioxidant layer 106 may be omitted. Alternatively, only the second antioxidant layer 106 may be stacked without forming the first antioxidant layer 105.

  Next, the thickness of each layer will be described. The thickness of each of the above layers is as follows in consideration of the contact resistance Rc of the obtained ohmic electrode, the annealing conditions (annealing temperature and time) necessary for obtaining a good contact resistance Rc, and the unevenness of the electrode surface. It is preferable.

  First, the thickness of the adhesion layer 102 is preferably smaller than the thickness of the interdiffusion prevention layer 104. The contact resistance value is almost determined by the ratio between the thickness of the adhesion layer and the thickness of the ohmic layer (the optimum ratio of the ohmic layer and the adhesion layer is 1:24). Further, by making the thickness of the adhesion layer 102 smaller than the thickness of the mutual diffusion prevention layer 104, diffusion between the adhesion layer, the ohmic layer and the antioxidant layer can be prevented.

  In addition, the thickness of the ohmic layer 103 is preferably larger than the thickness of the interdiffusion prevention layer 104. When the interdiffusion prevention layer is made thick, contact resistance may increase due to diffusion of the layer itself. Therefore, the interdiffusion prevention layer is preferably thinner than at least the ohmic layer.

  Further, the thickness of the first antioxidant layer 105 is preferably larger than the thickness of the interdiffusion prevention layer 104. The antioxidant layer is desirably thick enough to prevent oxidation, and is preferably at least thicker than the interdiffusion prevention layer.

  More specifically, the thickness of the ohmic layer 103 is preferably 30 to 90 nm, and more preferably 30 to 70 nm. This point will be described with reference to experimental results. FIG. 2 is a graph showing the relationship between the thickness of the ohmic layer (Al layer) and the optimum annealing time for obtaining the lowest contact resistance Rc under the annealing temperature of 900 ° C. The thicknesses of the adhesion layer 102 (Hf layer), the mutual diffusion prevention layer 104 (Hf layer), the first antioxidant layer 105 (Au layer), and the second antioxidant layer 106 (W layer) are respectively 2. The thickness was set to 5 nm, 10 nm, 60 nm, and 100 nm. As shown in FIG. 2, the optimum annealing time for obtaining the lowest contact resistance Rc increases as the thickness of the ohmic layer increases. When the thickness of the ohmic layer was 30 nm, the contact resistance Rc became a minimum of 0.48 Ω · mm after an annealing time of 10 seconds. In order to obtain a contact resistance value of 0.4 Ω · mm or less obtained by a normal GaAs-based HEMT, the thickness of the ohmic layer needs to be 50 nm or more, as will be described later. Is 15 seconds. However, it can be seen from FIG. 2 that when the thickness of the ohmic layer exceeds 70 nm, the optimum annealing time is rapidly increased.

  FIG. 3 is a graph showing the relationship between the thickness of the ohmic layer (Al layer) and the minimum value of the contact resistance Rc. Here, the minimum value of the contact resistance Rc is derived by variously changing the annealing temperature and annealing time. The thicknesses of the adhesion layer 102 (Hf layer), the mutual diffusion prevention layer 104 (Hf layer), the first antioxidant layer 105 (Au layer), and the second antioxidant layer 106 (W layer) are respectively 2. The thickness was set to 5 nm, 10 nm, 60 nm, and 100 nm. As shown in FIG. 3, the contact resistance Rc decreases as the thickness of the ohmic layer increases. That is, if the thickness of the ohmic layer is 50 nm or more, Rc can be 0.4 Ω · mm or less, and if the thickness of the ohmic layer is 90 nm, the contact resistance Rc is 0.37 Ω · mm. mm can be used.

  As described above, the contact resistance Rc can be lowered by increasing the thickness of the ohmic layer. Specifically, the contact resistance Rc can be lowered to 0.48 to 0.37 Ω · mm by setting the thickness of the ohmic layer to 30 to 90 nm. However, when the thickness of the ohmic layer exceeds 70 nm, the optimum annealing time tends to be abruptly increased. Therefore, the thickness of the ohmic layer is preferably 30 to 70 nm. In particular, the ohmic layer thickness is more preferably about 50 nm because contact resistance equivalent to that of a normal GaAs-based HEMT can be obtained and production efficiency is good.

  Further, the thickness of the adhesion layer 102 is not particularly limited, but is preferably 2.5 nm (25 Å) or more, and more preferably 5 nm (50 Å) or more. Here, FIG. 4 is a graph showing the relationship between the thickness of the adhesion layer (Hf layer) and the contact resistance Rc. The measurement is performed under conditions of an annealing temperature of 900 ° C. and an annealing time of about 25 to 35 seconds. The annealing time of 25 to 35 seconds is a time during which the contact resistance Rc becomes substantially constant regardless of the thickness of the adhesion layer. The ohmic layer 103 (Al layer), the interdiffusion prevention layer 104 (Hf layer), the first antioxidant layer 105 (Au layer), and the second antioxidant layer 106 (W layer) have a thickness of 50 nm, respectively. The thickness was set to 10 nm, 60 nm, and 100 nm. As shown in FIG. 4, the thicker the adhesion layer (Hf layer), the lower the contact resistance Rc. However, when the thickness exceeds 50 mm, the minimum value is substantially constant.

  The thickness of the interdiffusion prevention layer 104 is not particularly limited, but is preferably 10 nm or more. This is because if the thickness is 10 nm or more, diffusion of the ohmic layer and the antioxidant layer can be prevented. The thickness of the first antioxidant layer 105 is not particularly limited, but is preferably 60 nm or more.

  Furthermore, the thickness of the second antioxidant layer 106 is not particularly limited, but is preferably 100 nm or more, more preferably 200 nm or more, particularly about 500 nm or more. preferable. FIG. 5 is a graph showing the relationship between annealing time and electrode surface flatness (size of irregularities on the electrode surface) when the thickness of the second antioxidant layer (W layer) is changed. As shown in FIG. 5, when the thickness of the second antioxidant layer (W layer) is relatively thin at 100 nm, the flatness of the surface does not change much even if the annealing time is changed, and is about 90 to 100 nm. An electrode having surface flatness is obtained. On the other hand, when the thickness of the second antioxidant layer (W layer) is relatively thick, such as 200 to 500 nm, the dependency of the surface flatness on the annealing time increases, but the electrode with very good flatness Is obtained. In particular, when the thickness of the second antioxidant layer (W layer) is 500 nm, the flatness is very high at 30 nm or less.

  Note that the contact resistance Rc is measured by a transmission line model method (TLM method), which will be outlined below. The contact resistance Rc (Ω · mm) can be regarded as Rs · Lt, where Rs is the sheet resistance and Lt is the transition length. That is, the following formula [1] is established.

Rc = Rs · Lt [1]
On the other hand, the total resistance Rt is expressed by the following equation [2].

Here, ro is the width of the ohmic electrode, and d is the distance between the two ohmic electrodes. Therefore, first, ro is constant (for example, 40 μm), and the total resistance Rt is measured using a four-probe method for a plurality of samples (for example, four points) having different d. Next, the measurement points are plotted with the horizontal axis d and the vertical axis Rt, and the most probable straight line equation is obtained by the least square method or the like, and the total resistance value Rt ₀ at d = 0 is obtained. If d = 0 is substituted into the above equation [2], the total resistance value Rt _{0 at} d = 0 becomes Rs · Lt / πro, and if the above equation [1] is substituted for this, the following equation [3 ] Is obtained.

Rc = πroRt ₀ [3]
From the above equation [3], the contact resistance Rc can be obtained. As a numerical value for evaluating the performance of the ohmic contact, in addition to the contact resistance Rc, there is a specific contact resistance (Ω · mm ² ) represented by Rs · Lt ² , which is obtained by the above plot. Rs can be obtained from the slope of the straight line, and Lt can be obtained by calculating Lt using the above equation [1].

(Method for producing ohmic electrode)
Next, with reference to FIGS. 6A and 6B, a method for producing the ohmic electrode of the present embodiment will be described. FIG. 6 is a schematic process diagram showing a method for producing an ohmic electrode according to the first embodiment of the present invention. First, a photoresist 601 is applied on the AlGaN layer 107 formed on the n-type or non-doped GaN layer 108, and the resist pattern is removed from the electrode pattern portion by photolithography where an ohmic electrode is to be produced ( (See FIG. 6 (a)). Next, the adhesion layer 102, the ohmic layer 103, the interdiffusion prevention layer 104, and the first antioxidant layer 105 are laminated in this order by sputtering (see FIG. 6B). The material and thickness of each layer are, for example, adhesion layer 102: Hf 2.5 nm, ohmic layer 103: Al 50 nm, interdiffusion prevention layer 104: 10 nm, and first antioxidant layer 105: Au 60 nm. Next, a second antioxidant layer 106 (for example, tungsten (W), layer thickness of 100 nm or more) is laminated on the first antioxidant layer 105, and the metal adhering to other than the electrode portion is removed by a lift-off method ( (Refer FIG.6 (c)).

  In the subsequent process, annealing is performed using a RTA (Rapid Thermal Annealing) furnace at a substrate temperature of 800 ° C. or higher, typically about 900 ° C., and alloyed. By performing annealing using an RTA furnace, annealing with good controllability can be performed in a short time. Although each layer diffuses and mixes with each other by annealing, it is not completely mixed but basically the structure of each layer is maintained. W constituting the second antioxidant layer 106 hardly diffuses because the melting point is very high. The RTA furnace is a device that heats by radiation without using a heat insulating material such as glass wool having a large heat capacity so that the temperature can be raised and lowered quickly. The temperature of the substrate is measured by, for example, a radiation thermometer or by bringing a thermocouple into contact with the substrate.

  In the present invention, the annealing temperature is preferably 800 ° C. or higher. This is because if it is less than 800 ° C., ohmic characteristics cannot be imparted to the electrode (IV characteristics do not become a straight line). Further, the annealing time is not particularly limited, and the optimum annealing time depends on the thickness of each layer in the ohmic electrode 101 as described above, but when the annealing temperature is, for example, 900 ° C. An ohmic electrode having a sufficiently low contact resistance Rc can be obtained within about 1 minute.

<Second Embodiment>
(Structure of ohmic electrode)
FIG. 7 is a schematic cross-sectional view of the ohmic electrode according to the second embodiment of the present invention. Hereinafter, only the characteristic part of the present embodiment will be described, but the points not described are the same as in the first embodiment. As shown in FIG. 7, in the ohmic electrode 701 of the present embodiment, the second antioxidant layer 706 is not formed only on the upper surface of the electrode, but the second antioxidant layer 706 constituting the ohmic electrode 701. It forms so that the side surface of each layer other than may be covered. Here, the layers other than the second antioxidant layer 706 constituting the ohmic electrode 701 are at least the adhesion layer 702 and the ohmic layer 703, and the first antioxidant layer 705 and the mutual diffusion preventing layer 704 are formed. In some cases, these are included. The thickness of the second antioxidant layer 706 in the portion covering the side surface of each layer is not particularly limited, but is, for example, about 60 nm.

  By covering the side surface of the electrode with the second antioxidant layer 706 in this way, the lateral expansion of the ohmic electrode during annealing can be prevented. Thereby, the size of the ohmic electrode can be precisely controlled, and an element having stable characteristics can be manufactured. For example, when a plurality of ohmic electrodes are produced close to each other, it is possible to prevent an accident that they are in contact with each other during annealing.

(Method for producing ohmic electrode)
Next, with reference to FIG. 8, a method for producing the ohmic electrode of the present embodiment will be described. FIG. 8 is a schematic process diagram showing a method for producing an ohmic electrode according to the second embodiment of the present invention. First, a photoresist 801 is applied on a layer 707 made of AlGaN formed on an n-type or non-doped GaN layer 708, and the resist pattern is removed from the electrode pattern portion by photolithography at a location where an ohmic electrode is to be produced ( (See FIG. 8 (a)). Next, an adhesion layer 702, an ohmic layer 703, an interdiffusion prevention layer 704, and a first antioxidant layer 705 are stacked in this order by sputtering (see FIG. 8B). The material and layer thickness of each layer are, for example, adhesion layer 702: Hf 2.5 nm, ohmic layer 703: Al 50 nm, mutual diffusion prevention layer 704: 10 nm, and first antioxidant layer 705: Au 60 nm. Next, after removing the photoresist (see FIG. 8C), the photoresist 802 is applied again on the AlGaN layer 707, and a portion where the second antioxidant layer is to be formed is patterned (FIG. 8D). reference). Next, a metal (for example, W) constituting the second antioxidant layer is deposited by sputtering to form the second antioxidant layer 706 (see FIG. 8E), and then the photoresist is peeled off (see FIG. 8E). (Refer FIG.8 (f)). The electrode thus obtained is annealed and alloyed by the same method as in the first embodiment.

<Third Embodiment>
The ohmic electrode of the present embodiment is characterized by using a tungsten (W) layer in which a compressive stress is applied to the second antioxidant layer, and the electrode structure itself is the same as that of the first embodiment. Referring to FIG. 1, a layer 107 made of AlGaN, which is a wide bandgap compound semiconductor, is formed on an n-type or non-doped GaN layer 108, but between the AlGaN layer 107 and the GaN layer 108. There is a two-dimensional electron gas layer. By applying compressive stress to the second antioxidant layer, the AlGaN layer 107 is distorted and the concentration of the two-dimensional electron gas is increased. Such an increase in the two-dimensional electron gas concentration results in a reduction in the series resistance of the element, and it is possible to reduce heat generation when applied to a high-power element. Here, the reason why compressive stress is applied to the second antioxidant layer is that the second antioxidant layer made of tungsten is the hardest and hardly broken in the electrode.

  As a method for forming a tungsten layer to which a compressive stress is applied, the pressure of a gas (for example, argon gas) at the time of sputter deposition is reduced to, for example, about 4 mmTorr or less, and the discharge power is increased to, for example, about 100 W or more. And vapor deposition.

<Fourth Embodiment>
FIG. 9 is a schematic cross-sectional view of an ohmic electrode according to a fourth embodiment of the present invention. Hereinafter, only the characteristic part of the present embodiment will be described, but the points not described are the same as in the first embodiment. 9 are the same as 102 to 110 in FIG. As shown in FIG. 9, the ohmic electrode 901 of the present embodiment is formed on a layer portion made of AlGaN, which is a wide band gap compound semiconductor having a smaller thickness than the thickness of the portion where the ohmic electrode is not formed. It is characterized by being. That is, the thickness of the portion where the ohmic electrode is formed in the layer made of the wide band gap compound semiconductor is smaller than the thickness of the portion where the ohmic electrode is not formed. With such a configuration, the contact resistance Rc can be further reduced.

  Here, FIG. 10 is a graph showing the relationship between the thickness of the AlGaN layer (layer made of a wide band gap compound semiconductor) where the ohmic electrode is formed and the contact resistance Rc of the ohmic electrode. As can be seen from FIG. 10, it can be seen that the contact resistance Rc of the ohmic electrode decreases as the thickness of the AlGaN layer in the portion where the ohmic electrode is formed is reduced. Therefore, it is preferable that the thickness of the AlGaN layer (a layer made of a wide band gap compound semiconductor) where the ohmic electrode is formed be as thin as possible within the range that does not impair the characteristics of the device. The configuration of the present embodiment is realized, for example, by etching a part of the AlGaN layer where the ohmic electrode is formed to the vicinity of the underlying GaN layer.

(Electronic device)
The electronic device of the present invention has at least one or a plurality of electrodes, and at least one of the electrodes is an ohmic electrode having the above-described configuration. Here, the electronic device is not particularly limited as long as it has an ohmic electrode having the above-described configuration, and examples thereof include a transistor such as a field effect transistor (FET) and a high electron mobility transistor (HEMT). . Since the electronic device of the present invention has an ohmic electrode with sufficiently low contact resistance, a large current (for example, a large current density of several A / mm ² or more) can flow. Hereinafter, the electronic device of the present invention will be described by taking an FET as an example.

  FIG. 11 is a schematic view showing a preferred example of the electronic device of the present invention. The FET of FIG. 11 includes a source electrode 1104 and a drain electrode 1105 that are ohmic electrodes according to the present invention formed on a layer 1103 made of a wide band gap compound semiconductor such as an AlGaN layer, and is also made of a wide band gap compound semiconductor. A gate electrode 1106 is formed over the layer. As described above, the layer 1103 made of the wide band gap compound semiconductor is stacked on the GaN layer 1102 formed on the silicon substrate 1101, for example. Although not shown, a buffer layer such as an AlN layer, an AlGaN layer, or a GaN-based superlattice layer is provided between the silicon substrate 1101 and the GaN layer 1102 as necessary. Moreover, it has the dielectric material layer 1107 formed so that these electrodes might be covered, and the two surface pad electrodes 1108 and 1109 are provided in the surface. The surface pad electrodes 1108 and 1109 are electrically connected to the gate electrode 1106 and the drain electrode 1105 through first via holes 1110 and 1111 that penetrate the dielectric layer 1107, respectively.

  On the other hand, a back surface pad electrode 1112 is formed on the surface of the silicon substrate 1101 opposite to the side on which the layer 1103 made of the wide band gap compound semiconductor is formed, and the back surface pad electrode 1112 includes the silicon substrate 1101, The source electrode 1104 is electrically connected through a second via hole 1113 that penetrates the GaN layer 1102 and the layer 1103 made of a wide band gap compound semiconductor. Since the FET having such a structure includes the ohmic electrode according to the present invention, it can be manufactured in a very short time while maintaining the low contact resistance of the conventional ohmic electrode, and the time of the production process Improvements can be made.

Here, although the dielectric layer 1107 is provided to increase the electric field strength, a material having a relative dielectric constant of about 2 or more is used as the material thereof in order to further enhance the effect. preferable. Examples thereof include TiO ₂ (dielectric constant 80), HfO ₂ (dielectric constant 25), SiN ₂ (dielectric constant 7.5), and the like.

  Next, a method for manufacturing the FET shown in FIG. 11 will be described. First, a GaN layer 1102 and a layer 1103 made of a wide band gap compound semiconductor are sequentially formed on a silicon substrate 1101, and then a source electrode 1104 and a drain electrode 1105, which are ohmic electrodes, are formed thereon by the method described above. Next, a gate electrode 1106 is formed on the layer 1103 made of a wide band gap compound semiconductor. The gate electrode 1106 is preferably a Schottky electrode. For example, a metal such as Ti, W, Ag, WN, Pt, Ni, Pd, and Au is directly deposited on the layer 1103 made of a wide band gap compound semiconductor. Can do. The type of metal to be used is selected in consideration of the required Schottky barrier height and the like.

  Next, the silicon substrate 1101 is polished and thinned to about 100 μm, and then a second via hole 1113 is formed from the surface side of the silicon substrate 1101. A technique for forming a via hole in a silicon substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-363563, Japanese Patent Application Laid-Open No. 2001-16054, and Japanese Patent Application Laid-Open No. 11-150127, and particularly a silicon substrate on which a GaN-based semiconductor conductive layer is formed. Is disclosed in JP-T-2004-530289, but the methods described in these documents can also be preferably used in the present invention. After forming the second via hole 1113, Ti, Ni, Au or the like is vapor-deposited on the back surface of the silicon substrate 1101, and the back surface pad electrode 1112 for connecting to an external circuit is formed by annealing at a low temperature. Ni is for preventing Au from peeling off. Further, as the back pad electrode 1112, a thick Au film may be formed by plating. If formed by plating, the via hole can be filled with Au, and the heat dissipation effect can be enhanced. Note that the back surface pad electrode 1112 is connected to an external circuit using Au wire, die bond paste, or the like. Thus, by forming a via hole and forming one electrode on the back surface, the area of the electrode can be increased without increasing the element, so that a high heat dissipation effect can be obtained. It is important to reduce the size of the element using a wide band gap semiconductor in which it is difficult to obtain a good crystal with a large area. Such a configuration is very suitable for an element using a wide band gap semiconductor. is there.

  In the subsequent step, an Al electrode pattern is formed on the source electrode 1104, the drain electrode 1105, and the gate electrode 1106 by using a normal vacuum deposition method, a photolithography method, or the like. At this time, the source electrode 1104 and the back pad electrode 1112 are electrically connected at the tip of the through hole.

  Next, a dielectric layer 1107 is formed over the layer 1103 made of a wide band gap compound semiconductor so as to cover the source electrode 1104, the drain electrode 1105, and the gate electrode 1106 by a sputtering method or the like. Next, first via holes 1110 and 1111 penetrating the dielectric layer 1107 are formed on the gate electrode 1106 and the drain electrode 1105 by using a normal photolithography method, a wet etching method, or the like. A surface electrode is formed by depositing Al from above. Finally, a portion connected to the gate electrode 1106 and a portion connected to the drain electrode 1105 are separated by a normal photolithography method, a wet etching method, or the like to form two surface pad electrodes 1108 and 1109 to complete the device. To do. The surface pad electrodes 1108 and 1109 are connected to an external circuit using Al wires.

  Here, the silicon substrate 1101, the source electrode 1104, and the drain electrode 1105 are electrically separated by the GaN layer 1102. That is, a valley of an electron potential is formed on the interface between the GaN layer 1102 and the layer 1103 made of a wide band gap compound semiconductor such as an AlGaN layer, and the source electrode is formed by electrons confined in the valley (two-dimensional electron gas: 2DEG). A current flows from 1104 to the drain electrode 1105, but no current flows on the silicon substrate 1101 side.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic sectional drawing of the ohmic electrode of 1st Embodiment which concerns on this invention. It is a graph which shows the relationship between the thickness of an ohmic layer (Al layer) and the optimal annealing time in which the lowest contact resistance Rc is obtained on condition of 900 degreeC annealing temperature. It is a graph which shows the relationship between the thickness of an ohmic layer (Al layer), and the minimum value of contact resistance Rc. It is a graph which shows the relationship between the thickness of an adhesion layer (Hf layer), and contact resistance Rc. It is a graph which shows the relationship between annealing time and the electrode surface flatness (size of the unevenness | corrugation of an electrode surface) when changing the thickness of a 2nd antioxidant layer (W layer). It is a schematic process drawing which shows the preparation methods of the ohmic electrode of 1st Embodiment which concerns on this invention. It is a schematic sectional drawing of the ohmic electrode of 2nd Embodiment which concerns on this invention. It is a schematic process drawing which shows the preparation methods of the ohmic electrode of 2nd Embodiment which concerns on this invention. It is a schematic sectional drawing of the ohmic electrode of 4th Embodiment which concerns on this invention. It is a graph which shows the relationship between the thickness of the AlGaN layer of the part in which an ohmic electrode is formed, and the contact resistance Rc of an ohmic electrode. It is the schematic which shows a preferable example of the electronic device of this invention.

Explanation of symbols

  101, 701, 901 Ohmic electrode, 102, 702, 902 Adhesion layer, 103, 703, 903 Ohmic layer, 104, 704, 904 Interdiffusion prevention layer, 105, 705, 905 First antioxidant layer, 106, 706 906 Second antioxidant layer, 107,707,907 AlGaN layer, 108,708,907 n-type or non-doped GaN layer, 109,709,909 buffer layer, 110,710,910 silicon (Si) substrate, 1101 Silicon substrate, 1102 GaN layer, 1103 Wide band gap compound semiconductor layer, 1104 Source electrode, 1105 Drain electrode, 1106 Gate electrode, 1107 Dielectric layer, 1108, 1109 Surface pad electrode, 1110, 1111 First via-ho , 1112 backside pad electrode, 1113 a second via hole.

Claims (19)

  An electrode formed on a layer made of a wide bandgap compound semiconductor formed on a substrate and including at least an adhesion layer, an ohmic layer, and an antioxidant layer in this order from the side of the layer made of the wide bandgap compound semiconductor An electronic device having at least one.   The electronic device according to claim 1, wherein the layer made of the wide band gap compound semiconductor is formed on a silicon substrate. 2. The compound semiconductor according to claim 1, wherein the wide band gap compound semiconductor is a compound semiconductor made of In _a Al _b Ga _c B _d N (a + b + c + d = 1, 0 ≦ a, b, c, d ≦ 1). The electronic device described.   The adhesion layer is made of Hf or Ti, the ohmic layer is made of Al, and the antioxidant layer has a single layer structure made of Au, a single layer structure made of W, or a layer made of Au. The electronic device according to claim 1, wherein the electronic device has a two-layer structure with a layer made of W.   2. The electronic device according to claim 1, further comprising an interdiffusion prevention layer made of Hf, Ti, Mo, Ni, Nb, or Pt between the ohmic layer and the antioxidant layer.   The electronic device according to claim 5, wherein a thickness of the adhesion layer is smaller than a thickness of the mutual diffusion prevention layer.   The electronic device according to claim 5, wherein a thickness of the ohmic layer is greater than a thickness of the interdiffusion prevention layer.   The electronic device according to claim 5, wherein a thickness of the antioxidant layer made of Au is larger than a thickness of the mutual diffusion preventing layer.   In the layer made of the wide band gap compound semiconductor, the thickness of the portion where the electrode including at least the adhesion layer, the ohmic layer, and the antioxidant layer in this order is formed is smaller than the thickness of the portion where the electrode is not formed The electronic device according to claim 1. The wide band gap compound semiconductor is a compound semiconductor made of Al _x Ga _1-x N (0 <x ≦ 1), and the layer made of the wide band gap compound semiconductor is a GaN layer formed on a silicon substrate. The electronic device according to claim 3, wherein the electronic device is formed thereon.   When the antioxidant layer has a two-layer structure of a layer made of Au and a layer made of W, the layer made of Au and the layer made of W are from the side of the layer made of the wide band gap compound semiconductor, The electronic device according to claim 4, wherein the electronic devices are stacked in this order.   The electronic device according to claim 4, wherein the antioxidant layer includes a layer made of W, and the antioxidant layer made of W is a layer to which a compressive stress is applied.   The electronic device according to claim 1, wherein the antioxidant layer is formed so as to cover at least side surfaces of the adhesion layer and the ohmic layer. An electronic device having a plurality of electrodes,
A dielectric layer covering the plurality of electrodes, and one or more surface pad electrodes formed on the surface of the dielectric layer,
2. The electronic device according to claim 1, wherein each of the surface pad electrodes is electrically connected to at least one of the plurality of electrodes through a first via hole.   The electronic device according to claim 14, wherein the dielectric layer is made of a dielectric having a relative dielectric constant of 2 or more.   The electronic device according to claim 14, wherein the surface pad electrode is made of Al. One or more backside pad electrodes formed on the surface of the substrate opposite to the side on which the layer made of the wide band gap compound semiconductor is formed;
The electronic device according to claim 14, wherein each of the back surface pad electrodes is electrically connected to at least one of the plurality of electrodes through a second via hole.   The electronic device according to claim 17, wherein a main component constituting the back electrode is Au.   The electronic device according to claim 17, wherein the substrate is a silicon substrate, the front surface pad electrode is made of Al, and a main component constituting the rear surface pad electrode is Au.

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