JP4379305B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a nitride compound semiconductor region, and more particularly to a semiconductor device having a nitride compound semiconductor region having excellent leakage current (leakage current) characteristics.

In recent years, a semiconductor device having a nitride-based compound semiconductor region has attracted attention as a high-frequency / high-power electronic device because of its extremely high breakdown voltage and high saturation drift velocity and mobility.
In particular, in a semiconductor device having a structure in which two types of nitride compound semiconductors having different compositions are stacked, polarization charges (carriers) generated by spontaneous polarization of the nitride compound semiconductor constituting these nitride compound semiconductor regions. Occurs near the interface of these nitride-based compound semiconductor regions.
In addition, when the upper nitride compound semiconductor region is continuously crystal-grown in a form in which lattice strain is generated between these nitride compound semiconductor regions, the nitride compound compound semiconductor region is near the interface between these nitride compound semiconductor regions. , Carriers based on piezoelectric polarization (or piezoelectric field polarization) are generated. Furthermore, since these nitride compound semiconductor regions have a large band gap energy difference, carriers tend to accumulate in the vicinity of the interface.
As described above, high-concentration two-dimensional carriers are generated in the vicinity of the interface of these nitride-based compound semiconductor regions, and further device performance can be improved.

FIG. 10 is a cross-sectional view showing a conventional heterojunction field effect transistor (HFET) using a nitride compound semiconductor. In FIG. 10, 101 is a sapphire substrate, 102 is a GaN buffer layer grown at low temperature, and 103 is GaN. An electron transit layer 104 is an AlGaN spacer layer having a thickness of 5 nm, 105 is an AlGaN electron supply layer having a thickness of 20 nm and a carrier concentration of 1 × 10 18 cm −3, and 107 is formed on the AlGaN electron supply layer 105. The source electrode 105 and the low-resistance contact source electrode 108 are formed on the AlGaN electron supply layer 105, and the AlGaN electron supply layer 105 and the low-resistance contact drain electrode 109 are formed on the AlGaN electron supply layer 105. This is a gate electrode of the AlGaN electron supply layer 105 and a Schottky junction.
Generally, an electrode material used for a gate electrode formed on an n-type semiconductor is a metal having a large work function such as nickel (Ni), platinum (Pt), gold (Au) described in Patent Document 1 described later. It has been known. Since these metals are electrode materials having low resistance to p-type semiconductors, they are Schottky junction electrode materials for n-type semiconductors.
US Pat. No. 5,192,987

  However, the gate electrode material having a Schottky junction with the AlGaN electron supply layer 105 such as nickel or gold reacts with the AlGaN electron supply layer 105 when heat-treated at a high temperature (400 ° C. or higher), and leaks when a reverse bias is applied. Since the current increases, the characteristics of the semiconductor device are extremely deteriorated. In addition, there is a problem that the characteristics of the semiconductor device during high temperature operation are likely to deteriorate.

  The present invention has been made in view of the above circumstances, and has a relatively low leakage current, and does not increase the leakage current even when high-temperature heat treatment is performed, and a nitride-based compound that operates stably even at high temperatures. An object is to provide a semiconductor device having a semiconductor region.

In order to solve the above problems, the present invention provides the following semiconductor device.
That is, the semiconductor device according to claim 1 is formed on a surface of the main semiconductor region, a main semiconductor region made of a nitride-based compound semiconductor formed on the main surface of the substrate, and the main semiconductor region. And an electrode having a Schottky junction made of rhodium .

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect , further comprising: a resistance film formed on a surface of the main semiconductor region and around the electrode having the Schottky junction. The film has a sheet resistance higher than that of the electrode having the Schottky junction, and has a Schottky junction with the main semiconductor region.

The semiconductor device according to claim 3 is the semiconductor device according to claim 1, having a high sheet resistance than the electrode having the Schottky junction, and a third electrode having a thickness resulting tunneling, It is formed between the electrode having the Schottky junction and the main surface of the main semiconductor region.

The semiconductor device according to claim 4 is the semiconductor device according to any one of claims 1 to 3 , wherein the electrode having the Schottky junction is heat-treated after rhodium is formed on a surface of the main semiconductor region. It is characterized by.

According to the semiconductor device having the nitride compound semiconductor layer of the present invention, the electrode having the main semiconductor region and the Schottky junction is formed of Rh on the main semiconductor region made of the n-type nitride compound semiconductor layer. Rh is a metal having a high work function, and the melting point of Rh is higher than that of Ni or Au, and higher than that of Pt or Pd of the same family. In general, self-surface diffusion of a metal starts at a temperature of about 1/10 of the melting point, and alloying starts at a temperature of about 1/3 of the melting point. Therefore, when the electrode having the Schottky junction is formed using the Rh, there is a feature that a reaction is hardly caused when heat treatment is performed at a high temperature at the interface between the electrode having the Schottky junction and the main semiconductor region.

Therefore, the interface between the electrode and the main semiconductor region can be stabilized, and leakage current generated when a reverse voltage is applied can be suppressed. Further, even when this semiconductor device is operated at a high temperature, it is difficult for a reaction to occur at the interface between the electrode and the main semiconductor region, and the operation of the semiconductor device at a high temperature can be stabilized. Further, by heat-treating the Rh, the adhesion with the main semiconductor region can be improved and the leakage current can be further suppressed.

Embodiments of the nitride-based semiconductor device of the present invention will be described with reference to the drawings.
Note that these embodiments are described in detail for better understanding of the gist of the invention, and thus do not limit the present invention unless otherwise specified.

“First Embodiment”
The first embodiment of the nitride-based semiconductor device of the present invention will be described by taking a lateral heterojunction field effect transistor (HFET) as an example.
FIG. 1 is a cross-sectional view showing an HFET of this embodiment. This HFET includes a substrate 1 made of silicon (Si), a buffer layer 2 having a multilayer structure made of AlN / GaN on the main surface of the substrate 1, and undoped GaN. The main semiconductor region composed of the layer 3 and the n-type AlGaN layer 4 is formed, and the surface of the n-type AlGaN layer 4 has a low resistance contact with the n-type AlGaN layer 4 composed of a two-layer structure of Ti / Al. A source electrode 5, an n-type AlGaN layer 4 having a Ti / Al two-layer structure, a drain electrode 6 having a low resistance contact, an n-type AlGaN layer 4 made of rhodium (Rh), and a gate electrode 7 having a Schottky junction It has.
In the vicinity of the AlGaN layer 4 above the GaN layer 3, a two-dimensional carrier (two-dimensional electron gas layer) 3a is generated.

The gate electrode 7 may be a single layer electrode made of only Rh, or may be made of an alloy containing Rh. Here, the alloy containing Rh is an alloy containing Rh as a constituent element of the electrode, and includes a state of a mixture in which a part of Rh of the electrode material is not alloyed.
Further, for example, when considering adhesion with wire bonding, as shown in FIG. 2, a metal layer such as a Ti layer 7b and a gold (Au) layer 7c is sequentially laminated on Rh or its alloy layer 7a. In addition, an electrode material having good adhesion to the wire bonding may be provided between the wire bonding and the Rh or its alloy layer 7a. Moreover, it is good also as an Al layer instead of the Au layer 7c.

Next, a method for manufacturing the HFET of this embodiment will be described.
First, a multilayer buffer layer 2 made of AlN / GaN, an undoped GaN layer 3, and an n-type AlGaN layer 4 are sequentially stacked on a clean Si substrate 1 by chemical vapor deposition (CVD). Next, Ti and Al are sequentially stacked on the AlGaN layer 4 by sputtering, and then patterned by etching to form the source electrode 5 and the drain electrode 6. Next, the source electrode 5 and the drain electrode 6 are heat-treated at, for example, 650 ° C. for 10 minutes. Next, Rh is deposited on the AlGaN layer 4 by sputtering and patterned by the lift-off method to form the gate electrode 7 having a Schottky junction with the AlGaN layer 4. Next, the gate electrode 7, that is, Rh is heat-treated at a temperature range of 300 to 600 ° C. for 20 to 60 minutes. For example, 30 minutes at 550 ° C.

  Here, the melting point of Rh constituting the gate electrode 7 is 1966 ° C., which is higher than that of nickel (Ni: 1455 ° C.) or gold (Au: 1063 ° C.) conventionally used as a Schottky electrode material. It is higher than platinum (Pt: 1769 ° C.) and palladium (Pd: 1552 ° C.). In general, self-surface diffusion of a metal starts at a temperature of about 1/10 of the melting point, and alloying starts at a temperature of about 1/3 of the melting point. Therefore, even if the gate electrode 7 is heat-treated in the above temperature range, conventional Ni, Au, or similar Pt and Pd electrodes at the interface where the gate electrode 7 made of Rh or an alloy thereof and the AlGaN layer 4 are in contact with each other. Alloying is less likely to occur than the material. Therefore, a good Schottky barrier can be formed in the gate electrode 7 and the AlGaN layer 4, and leakage current can be suppressed when a reverse voltage is applied.

  Furthermore, when the gate electrode 7 is formed by laminating Rh, which is a gate electrode material, and heat treatment is performed on the gate electrode, the adhesion between the gate electrode 7 and the AlGaN layer 4 is improved, and leakage current is reduced as compared with that before the heat treatment. Can be reduced.

  As described above, according to the HFET of the first embodiment, the leakage current can be suppressed by configuring the AlGaN layer 4 and the gate electrode 7 made of Schottky junction Rh or an alloy thereof.

Although the Si substrate 1 is used here, a sapphire substrate, a GaN substrate, a GaAs substrate, or a SiC substrate may be used.
The n-type AlGaN layer 4 that is an epitaxial layer is a nitride formed by combining N with one or more selected from the group of B, Al, In, and Ga, such as BN, AlBN, and GaInN. Also good.
Further, although the buffer layer 2 has a multilayer structure made of AlN / GaN, any layer having a function as a buffer layer may be used. For example, an AlN layer alone may be used.
Further, the GaN layer 3 and the AlGaN layer 4 having a two-layer structure that generate two-dimensional carriers may be replaced with a GaN layer having a single-layer structure that does not generate two-dimensional carriers.
Further, although the drain electrode 6 and the source electrode 7 have a Ti / Al two-layer structure, they may be replaced with an electrode made of a metal material having a low resistance contact with the AlGaN layer 4.

“Second Embodiment”
FIG. 3 is a cross-sectional view showing a Schottky barrier diode (SBD) according to the second embodiment of the present invention. A cathode 31 having a low resistance contact with the AlGaN layer 4 on the AlGaN layer 4, and the AlGaN layer 4. An anode 32 made of rhodium or an alloy thereof having an AlGaN layer 4 and a Schottky junction is provided thereon.

  As shown in FIG. 4, the planar structure of the cathode 31 and the anode 32 may be configured such that a disc-shaped anode 32a (or cathode 31a) is disposed at the center of the annular cathode 31a (or anode 32a). Further, as shown in FIG. 5, an anode 32b (or cathode 31b) having a comb-shaped electrode may be disposed so as to surround the comb-shaped cathode 31b (or anode 32b).

In the present embodiment, a horizontal Schottky barrier diode (SBD) is shown as an example, but a vertical Schottky barrier diode (SBD) may be used.
The effect similar to 1st Embodiment can be acquired by making the anode of vertical SBD into the electrode which consists of rhodium or its alloy.

“Third Embodiment”
FIG. 6 is a cross-sectional view showing an HFET according to a third embodiment of the present invention, which is an example of a gate electrode 51 having a field plate structure in which only the upper portion of the gate electrode 7 made of rhodium or an alloy thereof is expanded in the surface direction. The gate electrode 51 is formed in a T shape on the AlGaN layer 4.
In a region surrounded by the gate electrode 51, the source electrode 5 and the drain electrode 6, a passivation film 41 made of SiNx or the like for improving the reliability of the semiconductor device is formed.

“Fourth Embodiment”
FIG. 7 is a cross-sectional view showing an HFET according to a fourth embodiment of the present invention, in which rhodium having a Schottky junction formed on the surface of a main semiconductor region made of a nitride compound semiconductor formed on the main surface of the substrate. Or it is the example which has the resistance film 61 which adjoins the circumference | surroundings of the gate electrode 7 which consists of the alloy, and surrounds it.
The resistance film 61 has a sheet resistance higher than the sheet resistance of the gate electrode 7 and forms a Schottky junction with the surface of the main semiconductor region. Since this resistance film 61 has a higher resistance than the gate electrode 7, it functions as a high resistance Schottky barrier type field plate and widens the depletion layer so that the electric field is not concentrated on the periphery of the gate electrode 7 (the curvature of the depletion layer). Has a function to alleviate).

  The resistance film 61 is preferably made of titanium oxide (TiOx), nickel oxide (NiOx), palladium oxide (PdOx), platinum oxide (PtOx), rhodium oxide (RhOx), or the like. However, the sheet resistance of the resistance film 61 is 10 kΩ / □ or more, and the material constituting the resistance film 61 is a high resistance material composed of a material having a smaller oxidation number (less X) than a general oxide. It is not an insulator. For example, titanium oxide (TiOx) has less oxygen than titanium dioxide (TiO2) which can be regarded as a perfect insulator, so-called oxygen-deficient titanium oxide (X is less than 2, 1.8, 1.9, etc.) Conceivable. Here, the thickness of the resistance film 61 may be a thickness that provides a predetermined sheet resistance. However, the thickness of the resistance film 61 is determined based on the film thickness control at the time of forming the resistance film 61 and the temperature of the film. Is preferably 20 angstroms or more, and the thickness of the resistance film 61 is desirably 300 angstroms or less, judging from the film formation temperature and the formation time when the resistance film 61 is formed.

  In the HFET of this embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, when the depletion layer generated by the gate electrode 7 and the depletion layer generated by the resistance film 61 are continuously formed in the AlGaN layer 4, electric field concentration does not occur in the peripheral portion of the gate electrode 7. Further breakdown voltage can be improved.

“Fifth Embodiment”
FIG. 8 is a cross-sectional view showing an HFET according to a fifth embodiment of the present invention, which is an example of a MIS structure HFET.
A film 71 made of silicon oxide (SiO 2), silicon nitride (Si 3 N 4), aluminum oxide (Al 2 O 3) or the like is interposed between the AlGaN layer 4 and the gate electrode 7 made of rhodium or an alloy thereof formed on the AlGaN layer 4. Have. The film 71 may be an insulating film, but the film 71 may be changed to the resistance film 61 of the fourth embodiment, and silicon oxide (SiOx), silicon nitride (Si3Nx), aluminum oxide (Al2Ox), or the like may be used. Like the resistance film 61, the film 71 is a high-resistance material made of a material having a smaller oxidation number (less X) than a general oxide, and is not an insulator. For example, silicon oxide (SiOx) has less oxygen than silicon dioxide (SiO2), which can be regarded as a perfect insulator, so-called oxygen-deficient silicon oxide (X is less than 2, 1.8, 1.9, etc.) )it is conceivable that.
The film 71 preferably has a thickness capable of generating a tunnel effect between the gate electrode 7 and the AlGaN layer 4, and is preferably 20 angstroms or more and 80 angstroms or less.

  In the HFET of this embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, if the depletion layer generated by the gate electrode 7 and the depletion layer generated by the film 71 are continuously formed in the AlGaN layer 4, electric field concentration in the peripheral portion of the gate electrode 7 does not occur. The breakdown voltage can be improved.

“Sixth Embodiment”
FIG. 9 is a cross-sectional view showing an HFET according to a sixth embodiment of the present invention. A gate electrode 7 made of rhodium or an alloy thereof formed on the AlGaN layer 4 and an AlGaN layer on the AlGaN layer 4 are shown. In this example, a semiconductor layer 81 different from the layer 4 is formed, and the source electrode 5 or the drain electrode 6 is formed on the semiconductor layer 81.
Note that the source electrode 5 and the drain electrode 6 are only required to be electrically connected to the gate electrode 7, so the source electrode 5 or the drain electrode 6 may be formed on a semiconductor layer different from the gate electrode 7.

It is sectional drawing which shows HFET of the 1st Embodiment of this invention. It is sectional drawing which shows the modification of the gate electrode of HFET of the 1st Embodiment of this invention. It is sectional drawing which shows SBD of the 2nd Embodiment of this invention. It is a top view which shows the electrode structure of SBD of the 2nd Embodiment of this invention. It is a top view which shows the modification of the electrode structure of SBD of the 2nd Embodiment of this invention. It is sectional drawing which shows HFET of the 3rd Embodiment of this invention. It is sectional drawing which shows HFET of the 4th Embodiment of this invention. It is sectional drawing which shows HFET of the 5th Embodiment of this invention. It is sectional drawing which shows HFET of the 6th Embodiment of this invention. It is sectional drawing which shows the conventional HFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Buffer layer 3 GaN layer 3a Two-dimensional carrier 4 AlGaN layer 5 Source electrode 6 Drain electrode 7 Gate electrode 7a Rh or its alloy layer 7b Ti layer 7c Au layer 31, 31a, 31b Cathode 32, 32a, 32b Anode 41 Passivation film 51 Gate electrode 61 Resistance film 71 Film 81 Semiconductor region

Claims (4)

A substrate,
A main semiconductor region made of a nitride compound semiconductor formed on the main surface of the substrate;
A semiconductor device comprising an electrode formed on a surface of the main semiconductor region and having a Schottky junction made of rhodium at an interface with the main semiconductor region. A resistance film formed on a surface of the main semiconductor region and around the electrode having the Schottky junction , and the resistance film has a higher sheet resistance than the electrode having the Schottky junction; 2. The semiconductor device according to claim 1 , further comprising a Schottky junction between the main semiconductor region.   A third electrode having a sheet resistance higher than that of the electrode having the Schottky junction and having a thickness causing a tunnel effect is formed between the electrode having the Schottky junction and the main surface of the main semiconductor region. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 4. The semiconductor device according to claim 1 , wherein the electrode having a Schottky junction is formed by heating after forming rhodium on the surface of the main semiconductor region . 5.

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