JP6179445B2 - Vertical Schottky Barrier Diode, Manufacturing Method for Vertical Schottky Barrier Diode - Google Patents

Description

  The present invention relates to a semiconductor device.

  As a semiconductor device (semiconductor device, semiconductor element), a GaN-based semiconductor device including one or more semiconductor layers mainly formed from gallium nitride (GaN) is known. Some GaN-based semiconductor devices function as Schottky Barrier Diodes (SBDs) (for example, Patent Document 1).

JP 2009-59912 A

  In a vertical Schottky barrier diode using a GaN substrate, for example, the technique of Patent Document 1 is disclosed for the purpose of avoiding a problem that the Schottky electrode and the insulating layer are easily separated.

  FIG. 12 is a diagram showing a Schottky barrier diode 900 disclosed in Patent Document 1. In FIG. In Patent Document 1, a Schottky barrier diode 900 includes an electrode 7 that forms an insulating layer 4 adjacent to a Schottky electrode 5, is connected to the Schottky electrode 5, and is in contact with the insulating layer 4.

  However, when the structure described in Patent Document 1 is actually fabricated, the electrode in the gap between the Schottky electrode 5 and the insulating layer 4 is avoided, although the problem that the Schottky electrode 5 and the insulating layer 4 easily peel off is avoided. As a result of the contact between the electrode 7 and the semiconductor layer 3, the leakage current increases and the breakdown voltage decreases.

  For this reason, a method for improving the problem that the Schottky electrode and the insulating layer easily separate from the above method has been desired. In addition, for semiconductor devices, there have been demands for cost reduction, miniaturization, ease of manufacture, resource saving, improved usability, and improved durability.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
The first aspect of the present invention is:
A vertical Schottky barrier diode,
A semiconductor layer formed of a semiconductor;
An insulating layer having electrical insulation and covering a part of the semiconductor layer;
A shot that is formed so as to be Schottky bonded to the semiconductor layer, has a value obtained by subtracting the electron affinity of the semiconductor layer from a work function of 0.5 eV or more, and forms a field plate structure by extending to the surface of the insulating layer. A key electrode;
A wiring layer covering the outer peripheral end of the Schottky electrode and connected to the surface of the insulating layer in contact with the outer peripheral end of the Schottky electrode, and having a resistance lower than that of the Schottky electrode;
Including
In the vertical Schottky barrier diode, the distance between the end of the Schottky electrode and the end of the wiring layer is 3 μm or more and 1 mm or less.
The second aspect of the present invention is:
A method of manufacturing a vertical Schottky barrier diode comprising a Schottky electrode as a field plate electrode,
Forming a semiconductor layer;
Forming an insulating layer having electrical insulation and covering a part of the semiconductor layer;
A step wherein the formed to Schottky junction to the semiconductor layer, a value obtained by subtracting the electron affinity of the semiconductor layer from the work function of more than 0.5 eV,
Forming a wiring layer that covers an outer peripheral end of the Schottky electrode and is connected to a surface of the insulating layer in contact with the outer peripheral end of the Schottky electrode, and has a resistance lower than that of the Schottky electrode;
Performing a heat treatment in a nitrogen atmosphere after forming the Schottky electrode;
Including
In this method, the distance between the end of the Schottky electrode and the end of the wiring layer is 3 μm or more and 1 mm or less. The present invention can also be realized as the following forms.

(1) According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a semiconductor layer formed of a semiconductor, an insulating layer having electrical insulation and covering a part of the semiconductor layer, an electron affinity of the semiconductor layer, and 0.5 eV. A first electrode layer having the above work function and extending to the surface of the insulating layer to form a field plate structure; covers the first electrode layer; and at least a part of the insulating layer And covering a second electrode layer. According to this aspect, the second electrode layer covers the first electrode layer, covers at least a part of the insulating layer, and is connected to the insulating layer around the first electrode layer. The problem that the electrode layer and the insulating layer easily peel off can be avoided. In addition, by providing the first electrode layer as a field plate electrode, it is possible to suppress the second electrode layer from entering the gap between the first electrode layer and the insulating layer and contacting the semiconductor layer and the second electrode layer. Can do. For this reason, it is possible to avoid the problem that the withstand voltage decreases due to the contact between the semiconductor layer and the second electrode layer.

(2) In the semiconductor device described above, it is preferable that a distance between an end portion of the first electrode layer and an end portion of the second electrode layer is 3 μm or more. By doing so, the first electrode layer can be further prevented from peeling from the insulating layer.

(3) In the semiconductor device described above, the insulating layer has an opening that penetrates the insulating layer, the first electrode layer covers the semiconductor layer exposed in the opening, and the first layer The distance between the end of the electrode layer and the end of the opening of the insulating layer is preferably 2 μm or more. By doing so, it is possible to further suppress the second electrode layer from entering the gap between the first electrode layer and the insulating layer and contacting the semiconductor layer and the second electrode layer.

(4) In the semiconductor device described above, the first electrode layer may be formed of nickel.

(5) In the semiconductor device described above, the first electrode layer may be composed of a plurality of layers.

(6) In the semiconductor device described above, the first electrode layer in contact with the semiconductor layer may be formed of nickel.

(7) In the semiconductor device described above, the second electrode layer may include a third electrode layer on the first electrode layer side.

(8) In the semiconductor device described above, the third electrode layer may be composed of a plurality of layers.

(9) In the semiconductor device described above, the semiconductor layer may be mainly formed of gallium nitride.

(10) According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided. A method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including a first electrode layer as a field plate electrode, the method for forming a semiconductor layer, and having electrical insulation, and a part of the semiconductor layer is formed. A step of forming an insulating layer to cover, a step of forming a first electrode layer having an electron affinity of the semiconductor layer and a work function of 0.5 eV or more on the semiconductor layer, and covering the first electrode layer, And forming a second electrode layer covering at least a part of the insulating layer. According to the semiconductor device manufactured by this manufacturing method, the second electrode layer covers the first electrode layer and covers at least a part of the insulating layer and is connected to the insulating layer around the first electrode layer. Therefore, the problem that the first electrode layer and the insulating layer are easily separated can be avoided. In addition, by providing the first electrode layer as a field plate electrode, it is possible to suppress the second electrode layer from entering the gap between the first electrode layer and the insulating layer and contacting the semiconductor layer and the second electrode layer. Can do. For this reason, it is possible to avoid the problem that the withstand voltage decreases due to the contact between the semiconductor layer and the second electrode layer.

  The present invention can be realized in various forms other than the semiconductor device and the manufacturing method thereof. For example, it is realizable with forms, such as an electric equipment provided with the above-mentioned semiconductor device, a manufacturing apparatus which manufactures the above-mentioned semiconductor device.

  According to the present invention, the second electrode layer covers the first electrode layer, covers at least part of the insulating layer, and is connected to the insulating layer around the first electrode layer. The problem that the electrode layer and the insulating layer easily peel off can be avoided. In addition, by providing the first electrode layer as a field plate electrode, it is possible to suppress the second electrode layer from entering the gap between the first electrode layer and the insulating layer and contacting the semiconductor layer and the second electrode layer. Can do. For this reason, it is possible to avoid the problem that the withstand voltage decreases due to the contact between the semiconductor layer and the second electrode layer.

1 is a cross-sectional view schematically showing a configuration of a semiconductor device 10 in a first embodiment. 4 is a process diagram illustrating a method for manufacturing the semiconductor device 10. FIG. FIG. 3 is a schematic diagram showing a configuration in which a semiconductor layer 120 is formed on a substrate 110. FIG. 3 is a schematic diagram showing a configuration in which an insulating layer 180 is formed on a semiconductor layer 120. It is a schematic diagram which shows the structure in which the opening part 185 was formed. It is a schematic diagram which shows the structure in which the Schottky electrode 192 was formed. It is a schematic diagram which shows the structure in which the barrier metal layer 170 and the wiring layer 160 were formed. FIG. 3 is a schematic view of the semiconductor device 10 as viewed from the + Z-axis direction. It is sectional drawing which shows typically the structure of the semiconductor device 20 in 2nd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device 30 in 3rd Embodiment. It is sectional drawing which shows typically the structure of the semiconductor device 40 in 4th Embodiment. It is a figure which shows the Schottky barrier diode of patent document 1. FIG.

A. First embodiment:
A-1. Semiconductor device configuration:
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device 10 in the first embodiment. FIG. 1 shows XYZ axes orthogonal to each other.

  Of the XYZ axes in FIG. 1, the X axis is an axis from the left side of FIG. 1 toward the right side of the page, the + X axis direction is a direction toward the right side of the page, and the −X axis direction is a direction toward the left side of the page. It is. Of the XYZ axes in FIG. 1, the Y axis is an axis from the front of the paper to the back of the paper in FIG. 1, the + Y axis direction is a direction toward the back of the paper, and the −Y axis direction is a direction toward the front of the paper. It is. Among the XYZ axes in FIG. 1, the Z axis is an axis that goes from the bottom of FIG. 1 to the top of the paper, the + Z axis direction is a direction that goes on the paper, and the −Z axis direction is a direction that goes down the paper. It is.

  The semiconductor device 10 is a GaN-based semiconductor device formed using gallium nitride (GaN). In the present embodiment, the semiconductor device 10 is a vertical Schottky barrier diode. The semiconductor device 10 includes a substrate 110, a semiconductor layer 120, a wiring layer 160, an insulating layer 180, a Schottky electrode 192, and a back electrode 198. Note that the “Schottky electrode” in the “DETAILED DESCRIPTION OF THE INVENTION” corresponds to the “first electrode layer” in “Means for Solving the Problems”. Similarly, the “wiring layer” corresponds to the “second electrode layer”.

  The substrate 110 of the semiconductor device 10 is a semiconductor layer having a plate shape extending along the X axis and the Y axis. In the present embodiment, the substrate 110 is an n-type semiconductor layer that is mainly formed of gallium nitride (GaN) and contains silicon (Si) as a donor. Being mainly formed from gallium nitride (GaN) indicates that 90% or more of gallium nitride (GaN) is contained in the molar fraction.

The semiconductor layer 120 of the semiconductor device 10 is an n-type semiconductor layer that extends along the X axis and the Y axis. In the present embodiment, the semiconductor layer 120 is mainly formed of gallium nitride (GaN) and contains silicon (Si) as a donor. The semiconductor layer 120 is stacked on the + Z axis direction side of the substrate 110. The semiconductor layer 120 has an interface 121. The interface 121 is a surface along the XY plane in which the semiconductor layer 120 extends and facing the + Z-axis direction. At least a part of the interface 121 may be a curved surface or may have undulations. In this embodiment, the semiconductor layer 120 has a thickness of 10 μm and a donor concentration of 1 × 10 ¹⁶ cm ⁻³ .

  The insulating layer 180 of the semiconductor device 10 has electrical insulation and covers the interface 121 of the semiconductor layer 120. The insulating layer 180 includes a first insulating layer 181 and a second insulating layer 182.

The first insulating layer 181 in the insulating layer 180 is a layer formed from aluminum oxide (Al ₂ O ₃ ) and in contact with the interface 121 of the semiconductor layer 120. In the present embodiment, the thickness of the first insulating layer 181 is 100 nm. The second insulating layer 182 in the insulating layer 180 is made of silicon dioxide (SiO ₂ ). In the present embodiment, the thickness of the second insulating layer 182 is 500 nm.

  In the insulating layer 180, an opening 185 that penetrates the first insulating layer 181 and the second insulating layer 182 is formed. The opening 185 is formed by wet etching.

  The Schottky electrode 192 of the semiconductor device 10 is a conductive electrode and is a Schottky junction with the interface 121 of the semiconductor layer 120. In the present embodiment, the Schottky electrode 192 is formed from nickel (Ni). In this specification, a Schottky electrode refers to an electrode in which the difference between the electron affinity of the semiconductor layer 120 and the work function of a metal used as the Schottky electrode is 0.5 eV or more.

  In this embodiment, the Schottky electrode 192 includes the interface 121 of the semiconductor layer 120 that occupies a part of the opening 185, the side surface of the insulating layer 180 that occupies a part of the opening 185, and the surface on the + Z-axis direction side of the insulating layer 180. It is a conductor layer which covers a part of. Thus, the Schottky electrode 192 forms a field plate structure with the insulating layer 180 interposed between the semiconductor layer 120 and the Schottky electrode 192. In the field plate structure, one or a plurality of electrodes are connected and arranged from the surface of the semiconductor layer to the surface of the insulating layer provided on the semiconductor layer, so that the electrode and the semiconductor layer are in contact with each other. The structure provided in order to relieve the electric field in the edge part of a part. In this embodiment, the Schottky electrode is formed in the semiconductor layer, and has a field plate structure that functions as a field plate electrode by extending to the surface of the insulating layer. In the present embodiment, the thickness of the Schottky electrode 192 is 100 nm.

  The wiring layer 160 of the semiconductor device 10 includes a pad electrode for forming a bonding wire and a Schottky electrode as an electrode for lead wiring when a Schottky barrier diode is mounted on a printed board or used as a circuit component. In many cases, the electrode layer is formed thick so as to include a metal material having a relatively low resistivity such as Al, Au, or Cu so that the resistance is lower than that of the Schottky electrode layer. The wiring layer 160 of the semiconductor device 10 is composed of two layers of a layer 170 and a layer 161. Note that the layer 161 is also referred to as an upper layer 161 of the wiring layer.

  Of the wiring layer 160 of the semiconductor device 10, the layer 170 formed on the Schottky electrode 192 side is also referred to as a barrier metal layer, and diffusion of metal between the Schottky electrode 192 and the layer 161 that is an upper layer of the wiring layer. It is a layer provided to suppress adhesion and to improve the adhesion between the insulating layer and the wiring layer. The “barrier metal layer” in the present embodiment corresponds to the “third electrode layer” in the “means for solving the problems”. That is, the barrier metal layer may be considered as a layer included in the wiring layer.

  The barrier metal layer 170 is mainly formed from molybdenum (Mo). Note that “mainly formed of molybdenum (Mo)” means that 90% or more of molybdenum (Mo) is contained in the molar fraction. In the present embodiment, the thickness of the barrier metal layer 170 is 50 nm. The layer 161 formed on the barrier metal layer 170 is a layer mainly formed of aluminum (Al). Being mainly made of aluminum (Al) indicates that 90% or more of aluminum (Al) is contained in the molar fraction. In the present embodiment, the layer 161 is made of aluminum silicon (AlSi) in which 1% of silicon (Si) is added to aluminum (Al). In the present embodiment, the film thickness of the upper layer 161 of the wiring layer is 4 μm. The wiring layer 160 and the Schottky electrode 192 serve as the anode electrode of the Schottky barrier diode.

  The back electrode 198 of the semiconductor device 10 is an electrode that is ohmic-bonded to the −Z axis direction side of the substrate 110. In the present embodiment, the back electrode 198 is an electrode obtained by laminating a layer made of aluminum (AlSi) on a layer made of titanium (Ti) (Ti is the substrate side) and then alloying by heat treatment.

A-2. Semiconductor device manufacturing method:
FIG. 2 is a process diagram illustrating a method for manufacturing the semiconductor device 10. When manufacturing the semiconductor device 10, the manufacturer forms the semiconductor layer 120 on the substrate 110 by epitaxial growth in Step P <b> 110.

  FIG. 3 is a schematic diagram showing a configuration in which the semiconductor layer 120 is formed on the substrate 110. In this embodiment, the manufacturer forms the semiconductor layer 120 on the substrate 110 by epitaxial growth using an MOCVD apparatus that realizes a metal organic chemical vapor deposition (MOCVD) method.

  After forming the semiconductor layer 120 (process P110), the manufacturer forms the insulating layer 180 on the interface 121 of the semiconductor layer 120 in the process P120.

  FIG. 4 is a schematic diagram showing a configuration in which an insulating layer 180 is formed on the semiconductor layer 120.

The manufacturer first forms the first insulating layer 181 formed of aluminum oxide (Al ₂ O ₃ ) as the insulating layer 180 on the interface 121 of the semiconductor layer 120. In the present embodiment, the manufacturer forms the first insulating layer 181 by an ALD (Atomic Layer Deposition) method.

Next, the manufacturer forms the second insulating layer 182. The second insulating layer 182 is formed from silicon dioxide (SiO ₂ ). In this embodiment, the manufacturer forms the second insulating layer 182 by a chemical vapor deposition (CVD) method.

  After forming the insulating layer 180 (process P120), the manufacturer forms the opening 185 in the insulating layer 180 using wet etching in the process P130. In this embodiment, the manufacturer forms a mask on the insulating layer 180 by photolithography, and then removes part of the insulating layer 180 by wet etching to form the opening 185.

  FIG. 5 is a schematic diagram showing a configuration in which the opening 185 is formed. In the present embodiment, the side surface of the opening 185 is inclined so as to have an obtuse angle with respect to the semiconductor layer 120. This is preferable because concentration of an electric field at an end portion of the semiconductor layer 120 can be reduced in a portion where the semiconductor layer 120 and the insulating layer 180 are in contact with each other. Note that the side surface of the opening 185 may be perpendicular to the semiconductor layer 120.

  After forming the opening 185 (process P130), the manufacturer forms the Schottky electrode 192 at the interface 121 of the semiconductor layer 120 exposed from the opening 185 of the insulating layer 180 in process P140. The Schottky electrode 192 is made of nickel (Ni).

  FIG. 6 is a schematic diagram showing a configuration in which the Schottky electrode 192 is formed. In this embodiment, the manufacturer forms the Schottky electrode 192 by a lift-off method. Specifically, the manufacturer forms a mask on the insulating layer 180 other than the portion where the Schottky electrode 192 is stacked by photolithography, and then deposits nickel on the insulating layer 180 and the opening 185 with EB (Electron After that, the mask is removed from the insulating layer 180, leaving the Schottky electrode 192. In this embodiment, the interface 121 of the semiconductor layer 120 occupying a part of the opening 185, the side surface of the insulating layer 180 occupying a part of the opening 185, and a part of the surface of the insulating layer 180 on the + Z-axis direction side are covered. Thus, the Schottky electrode 192 is formed.

  The distance r between the end of the Schottky electrode 192 and the opening end of the opening 185 is shown in FIG. From the viewpoint of sufficiently obtaining an electric field relaxation effect due to the field plate structure and suppressing the deterioration of the characteristics of the semiconductor device 10 as an element due to the diffusion of the wiring layer 160 to be formed later into the semiconductor layer 120, the distance r Is preferably 2 μm or more, more preferably 5 μm or more, and even more preferably 10 μm or more. On the other hand, when the distance r is too long, the size of the semiconductor device 10 increases and the manufacturing cost increases. For this reason, the upper limit of the distance r is preferably 1 mm or less. In the present embodiment, the distance r is 10 μm.

  Thereafter, heat treatment is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere in order to stabilize the interface between the Schottky electrode 192 and the insulating layer 180. Although this heat treatment is not essential, it is preferable to perform the heat treatment from the viewpoint of stabilizing the interface between the Schottky electrode 192 and the insulating layer 180.

  After forming the Schottky electrode 192 (process P140), in step P150, the manufacturer laminates the barrier metal layer 170 and the layer 161, which is the upper layer of the wiring layer, on the Schottky electrode 192 by sputtering. The barrier metal layer 170 is made of molybdenum (Mo). The barrier metal layer is not limited to molybdenum (Mo), but may be other materials such as vanadium (V), titanium (Ti), titanium nitride (TiN), and the like. Further, the barrier metal layer is not a single layer. For example, titanium nitride (TiN) / titanium (Ti) (Ti is a Schottky electrode side), titanium (Ti) / titanium nitride (TiN), molybdenum (Mo) / vanadium ( A laminated structure of V), vanadium (V) / molybdenum (Mo), titanium (Ti) / titanium nitride (TiN) / titanium (Ti), or the like may be used. The layer 161, which is the upper layer of the wiring layer, is formed from aluminum silicon (AlSi). The material of the layer 161 is not limited to aluminum silicon (AlSi), but aluminum (Al), aluminum copper (AlCu) mainly formed from aluminum (Al), aluminum silicon copper (AlSiCu), or gold ( Materials other than aluminum (Al) such as Au) and copper (Cu) may be used. Further, the layer 161 which is an upper layer of the wiring layer may have a stacked structure instead of a single layer.

  In this embodiment mode, the layer 161 is formed continuously after the barrier metal layer 170 is formed. That is, a molybdenum (Mo) layer and an aluminum silicon (AlSi) layer are continuously formed by sputtering.

  After the wiring layer 160 is stacked by the sputtering method, a mask pattern is formed using a photoresist. At this time, the mask pattern is formed so as to cover the entire Schottky electrode 192 formed in the process P140. Thereafter, portions other than the portion covered with the photoresist are removed by chlorine-based dry etching, and the wiring layer 160 is formed. As a method for forming the wiring layer 160, for example, a method using an EB vapor deposition method instead of a sputtering method, a mask pattern is formed using a photoresist without using etching, and an electrode material is stacked and a lift-off method is used. Other methods such as a forming method may be adopted.

  FIG. 7 is a schematic diagram showing a configuration in which the wiring layer 160 is formed. A distance s between the end of the Schottky electrode 192 and the end of the wiring layer 160 is shown in FIG. In light of sufficiently suppressing peeling of the Schottky electrode 192 from the insulating layer 180, the lower limit of the distance s is preferably 3 μm or more, more preferably 5 μm or more, and even more preferably 10 μm or more. On the other hand, when the distance s is too long, the size of the semiconductor device 10 increases and the manufacturing cost increases. For this reason, the upper limit of the distance s is preferably 1 mm or less. In the present embodiment, the distance s is 10 μm.

  After forming the wiring layer 160 (process P160), the manufacturer forms the back electrode 198 on the −Z-axis direction side of the substrate 110 in process P170. In this embodiment, the manufacturer forms a layer made of titanium (Ti) on the −Z-axis direction side of the substrate 110 by vapor deposition, and further forms a layer made of aluminum silicon (AlSi) thereon by vapor deposition. The back electrode 198 is formed by alloying this layer by heat treatment. The contact resistance of the back electrode 198 can be reduced by the heat treatment. In the present embodiment, the heat treatment is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere. Note that the back electrode may be formed by sputtering.

  Through these steps, the semiconductor device 10 is completed.

  FIG. 8 is a schematic view of the semiconductor device 10 as viewed from the + Z-axis direction. The insulating layer 180 includes an inclined surface that is inclined with respect to the semiconductor layer 120 (see also FIG. 7), an end portion 183 indicates an end portion of the insulating layer 180 on the semiconductor layer 120 side, and an end portion 184 includes The end of the insulating layer 180 on the wiring layer 160 side is shown. The semiconductor device 10 has a configuration in which at least a part of the insulating layer 180 is covered with the Schottky electrode 192 and the Schottky electrode 192 is covered with the wiring layer 160.

  The semiconductor device 10 employs a field plate structure, and a wiring layer 160 is formed on the Schottky electrode 192 so as to cover at least a part of the insulating layer and to be connected to the insulating layer around the Schottky electrode. I have. For this reason, the surface of the semiconductor layer 120 is not exposed from the gap between the Schottky electrode 192 and the insulating layer 180. As a result, contact between the wiring layer 160 and the semiconductor layer 120 can be avoided, so that leakage current can be suppressed and breakdown voltage can be improved.

  In addition, since the semiconductor device 10 uses the barrier metal layer 170 having excellent adhesion, the Schottky electrode 192 and the insulating layer 180 are peeled even when the adhesion between the Schottky electrode 192 and the insulating layer 180 is weak. This can be suppressed.

B. Second embodiment:
FIG. 9 is a cross-sectional view schematically showing the configuration of the semiconductor device 20 in the second embodiment. The semiconductor device 20 according to the second embodiment is different from the semiconductor device 10 according to the first embodiment in that the semiconductor device 20 includes a Schottky electrode 292 and a Schottky electrode 293 instead of the Schottky electrode 192. The same.

  In this embodiment, a Schottky electrode 292 and a Schottky electrode 293 are stacked in this order from the semiconductor layer 120 side. In this embodiment, the Schottky electrode 292 is a nickel layer having a thickness of 100 nm, and the Schottky electrode 293 is a palladium layer having a thickness of 100 nm. The present invention may have such a form.

C. Third embodiment:
FIG. 10 is a cross-sectional view schematically showing the configuration of the semiconductor device 30 in the third embodiment. Compared to the semiconductor device 20 in the second embodiment, the barrier metal layer and the Schottky electrode are different, but the rest are the same. The semiconductor device 30 includes a barrier metal layer 370 only on the Schottky electrode 293, and the wiring layer 360 is directly connected to the insulating layer 180 without passing through the barrier metal layer 370.

  In this embodiment, the wiring layer 360 is formed of aluminum silicon copper (AlSiCu) in which 0.5% of silicon (Si) and copper (Cu) are added to aluminum (Al), and the film thickness is 4 μm. The barrier metal layer 370 is made of molybdenum (Mo) and has a thickness of 10 nm. In the semiconductor device 30, by using the wiring layer 360 having excellent adhesion, it is possible to prevent the Schottky electrode 292 and the insulating layer 180 from being peeled even when the adhesion between the Schottky electrode 292 and the insulating layer 180 is weak. . The present invention may have such a form.

D. Fourth embodiment:
FIG. 11 is a cross-sectional view schematically showing the structure of the semiconductor device 40 in the fourth embodiment. Compared to the semiconductor device 30 in the third embodiment, the barrier metal layer and the wiring layer are different, but the others are the same. As for the barrier metal layer, not only the barrier metal layer 370 formed on the Schottky electrode 293 but also the barrier metal layer 470 is laminated below the wiring layer.

  In this embodiment, as the barrier metal layer 470, a titanium layer 471 (thickness: 10 nm) formed from titanium (Ti) and a titanium nitride layer 472 (formed from titanium nitride (TiN)) in this order from the barrier metal layer 370 side. Thickness: 200 nm), a titanium layer 473 (thickness: 10 nm) formed from titanium (Ti) is laminated, and an aluminum silicon layer (thickness: formed from aluminum silicon (AlSi) which becomes the upper layer 461 of the wiring layer thereon. 4 μm) is laminated. The present invention may have such a form.

E. Other Embodiments The present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments, examples, and modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above-described effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

  In the above-described embodiment, the method of forming each layer of the insulating layer is not limited to the ALD method or the CVD method, but may be a sputtering method or a coating method.

  In the above-described embodiment, the Schottky electrode and the wiring layer are formed by continuously forming the upper layer of the barrier metal layer and the wiring layer after forming the Schottky electrode, or by continuously forming the Schottky electrode and the barrier metal layer. However, the present invention is not limited to this method. For example, the Schottky electrode, the barrier metal layer, the upper layer of the wiring layer, and the wiring layer are described. Etc. may be formed individually.

  In the above-described embodiment, the semiconductor device includes the barrier metal layer, but may not include the barrier metal layer. Further, the wiring layer may be a single layer such as an aluminum layer, or may have a laminated structure including a barrier metal layer.

  The combination of the insulating layer, the wiring layer, and the Schottky electrode in the above-described embodiment is a preferable combination from the viewpoint of avoiding the problem that the Schottky electrode and the insulating layer are easily peeled off, but may be other combinations.

In the above-described embodiment, silicon oxide (SiO ₂ ) / aluminum oxide (Al ₂ O ₃ ) is used for the insulating layer. However, the insulating layer is not limited to this, and may be a single layer or a laminated structure other than the above. As the insulating layer, silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), aluminum oxynitride (AlON), zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), oxynitride Examples thereof include silicon (SiON).

In the above-described embodiment, the material of the substrate is not limited to gallium nitride (GaN), but may be silicon (Si), sapphire (Al ₂ O ₃ ), silicon carbide (SiC), or the like.

  In the above-described embodiment, the donor included in the n-type semiconductor layer is not limited to silicon (Si), but may be germanium (Ge), oxygen (O), or the like.

  In the above-described embodiment, the material of the Schottky electrode is not limited to nickel (Ni), but may be palladium (Pd), platinum (Pt), gold (Au), or the like. Further, the Schottky electrode may have a laminated structure instead of a single layer. Examples of the laminated structure include palladium (Pd) / nickel (Ni), platinum (Pt) / nickel (Ni) (nickel is a semiconductor layer side), and the like.

  In the above embodiment, a Schottky barrier diode is used as a semiconductor device. However, the present invention is not limited to this, and a field plate structure is formed by a Schottky electrode such as a MESFET (Metal-Semiconductor Field Effect Transistor) or an HFET (hetero-FET). You may use for the semiconductor device using the Schottky electrode made.

  In the above-described embodiment, the material of the back electrode is not limited to an alloy of titanium (Ti) and aluminum silicon (AlSi), but is other metal such as aluminum (Al), vanadium (V), hafnium (Hf), and the like. Also good.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 20 ... Semiconductor device 30 ... Semiconductor device 40 ... Semiconductor device 50 ... Semiconductor device 100 ... Atsuga 110 ... Substrate 120 ... Semiconductor layer 121 ... Interface 160 ... Wiring layer 161 ... Upper layer of wiring layer 170 ... Barrier metal layer 180 ... Insulating layer 181 ... First insulating layer 182 ... Second insulating layer 183 ... End 184 ... End 185 ... Opening 192 ... Schottky electrode 198 ... Back electrode 292 ... Schottky electrode 293 ... Schottky electrode 360 ... Wiring Layer 370: Barrier metal layer 460 ... Wiring layer 461 ... Upper layer of wiring layer 470 ... Barrier metal layer 471 ... Titanium layer 472 ... Titanium nitride layer 473 ... Titanium layer 900 ... Schottky barrier diode r ... Distance s ... Distance

Claims (10)

A vertical Schottky barrier diode,
A semiconductor layer formed of a semiconductor;
An insulating layer having electrical insulation and covering a part of the semiconductor layer;
A shot that is formed so as to be Schottky bonded to the semiconductor layer, has a value obtained by subtracting the electron affinity of the semiconductor layer from a work function of 0.5 eV or more, and forms a field plate structure by extending to the surface of the insulating layer. A key electrode;
A wiring layer covering the outer peripheral end of the Schottky electrode and connected to the surface of the insulating layer in contact with the outer peripheral end of the Schottky electrode, and having a resistance lower than that of the Schottky electrode;
Including
A vertical Schottky barrier diode, wherein a distance between an end of the Schottky electrode and an end of the wiring layer is 3 μm or more and 1 mm or less. The vertical Schottky barrier diode according to claim 1,
The wiring layer is a vertical Schottky barrier diode containing aluminum. The vertical Schottky barrier diode according to claim 1 or 2,
The insulating layer has an opening that penetrates the insulating layer;
The Schottky electrode covers the semiconductor layer exposed in the opening,
A vertical Schottky barrier diode, wherein a distance between an end of the Schottky electrode and an end of the opening of the insulating layer is 2 μm or more and 1 mm or less. The vertical Schottky barrier diode according to any one of claims 1 to 3,
The Schottky electrode is a vertical Schottky barrier diode formed of nickel. The vertical Schottky barrier diode according to any one of claims 1 to 3,
The Schottky electrode is a vertical Schottky barrier diode composed of a plurality of layers. The vertical Schottky barrier diode according to claim 5,
The Schottky electrode in contact with the semiconductor layer is a vertical Schottky barrier diode formed of nickel. The vertical Schottky barrier diode according to any one of claims 1 to 6,
The wiring layer includes a barrier Schottky barrier diode that includes a barrier metal layer that is in close contact with the insulating layer on the Schottky electrode side and has higher adhesion to the insulating layer than the wiring layer. The vertical Schottky barrier diode according to claim 7,
The barrier metal layer is a vertical Schottky barrier diode composed of a plurality of layers. The vertical Schottky barrier diode according to any one of claims 1 to 8,
The semiconductor layer is a vertical Schottky barrier diode formed mainly of gallium nitride. A method of manufacturing a vertical Schottky barrier diode comprising a Schottky electrode as a field plate electrode,
Forming a semiconductor layer;
Forming an insulating layer having electrical insulation and covering a part of the semiconductor layer;
A step of forming the formed to Schottky junction with the semiconductor layer, the Schottky electrode minus the electron affinity of the semiconductor layer is not less than 0.5eV work function,
Forming a wiring layer that covers an outer peripheral end of the Schottky electrode and is connected to a surface of the insulating layer in contact with the outer peripheral end of the Schottky electrode, and has a resistance lower than that of the Schottky electrode;
Performing a heat treatment in a nitrogen atmosphere after forming the Schottky electrode;
Including
A method of manufacturing a vertical Schottky barrier diode, wherein a distance between an end of the Schottky electrode and an end of the wiring layer is 3 μm or more and 1 mm or less.

Images