JP6176131B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  As a technique for satisfactorily contacting the electrode with the n-type group III nitride semiconductor layer, an electrode made of an alloy containing titanium (Ti) and aluminum (Al) on a silicon (Si) -doped gallium nitride (GaN) layer, A technique for forming an electrode composed of a multilayer film in which Ti and Al are laminated is known (Patent Document 1).

JP-A-7-221103 JP 2010-192633 A

  However, in order to satisfactorily make ohmic contact with the electrode, if the electrode is etched with a structure containing Al, there may be a problem that the electrode is damaged by the etching. For example, after forming at least one of a source electrode and a drain electrode on an n-type group III nitride semiconductor layer, the inventors of the present application apply an Al-based gate electrode material to the entire surface of the wafer so as to directly contact the electrode. It was considered to form a fine gate pattern by performing vapor deposition and then patterning with a photoresist and processing the vapor deposited gate electrode material by dry etching. However, in this method, the contact resistance increases due to the source electrode or the drain electrode being scraped during the dry etching in the gate pattern forming step. This problem can be avoided by, for example, forming a protective electrode or protective insulating film on the source or drain electrode, then depositing a gate electrode material on the entire surface, and performing patterning by dry etching. is there. However, this method has a problem that the manufacturing process of the semiconductor device is increased and a manufacturing cost is increased. Therefore, there has been a demand for a technique for forming an electrode in a semiconductor device without increasing contact resistance and suppressing an increase in process and manufacturing cost. In addition, in semiconductor devices, further miniaturization and improved durability have been desired.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.
A first aspect of the present invention is a method for manufacturing a semiconductor device including a first electrode and a second electrode on a semiconductor layer. This method
(A) forming the first electrode so that the semiconductor layer on which the insulating film is formed is in contact with the semiconductor layer and has an end located on the semiconductor layer via the insulating film;
(B) The first electrode and the region where the second electrode is formed so that the first electrode and the second electrode material that is the material of the second electrode are in contact with each other. A step of covering and simultaneously covering the second electrode material;
(C) A first mask pattern covering the first electrode covered with the second electrode material and the second electrode are formed so that an end of the first electrode is exposed. A step of simultaneously forming a second mask pattern covering a region to be formed;
(D) By etching the second electrode material exposed from the first mask pattern and the second mask pattern, an end portion of the first electrode is exposed from the second electrode material; And a step of forming a structure in which the second electrode material covers the first electrode, and the second electrode;
Is provided.
A second aspect of the present invention is a method for manufacturing a semiconductor device comprising a first electrode and a second electrode on a semiconductor layer. This method
(A) forming the first electrode so as to be in ohmic contact with the semiconductor layer with respect to the semiconductor layer on which the insulating film is formed;
(B) the first electrode that is in ohmic contact with the semiconductor layer, the insulating film, and a region where the second electrode on the insulating film is formed; the first electrode and the insulating film; A step of collectively covering with the second electrode material so that the second electrode material that is the material of the second electrode is in contact with the second electrode material;
(C) The first electrode in ohmic contact with the semiconductor layer covered with the second electrode material and the peripheral edge of the first electrode covered with the second electrode material via the insulating film Simultaneously forming a first mask pattern covering the semiconductor layer and a second mask pattern covering a region where the second electrode is formed;
(D) The first electrode in which the second electrode material is in ohmic contact with the semiconductor layer by etching the second electrode material exposed from the first mask pattern and the second mask pattern. A structure that integrally covers the top and the semiconductor layer on the periphery of the first electrode via the insulating film, and the second electrode whose end is located on the semiconductor layer via the insulating film; Forming a
Is provided.
The present invention can also be realized as the following forms.

(1) According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a first electrode and a second electrode on a semiconductor layer. The manufacturing method includes (A) a step of preparing a semiconductor layer on which the first electrode is formed; (B) a region on which the first electrode and the second electrode are formed; A step of simultaneously covering the second electrode material together with the second electrode material so that the first electrode and the second electrode material that is the material of the second electrode are in contact with each other; and (C) covering the second electrode material Forming simultaneously a first mask pattern covering at least a part of the first electrode and a second mask pattern covering a region where the second electrode is formed; (D And (b) forming the second electrode by etching the second electrode material exposed from the first mask pattern and the second mask pattern. According to the manufacturing method of this aspect, in the step (C), the first mask pattern that covers the first electrode and the second mask pattern that covers the region where the second electrode is formed are formed. Therefore, in the step (D), the first electrode can be prevented from being damaged by etching. Therefore, a semiconductor device can be manufactured without increasing the contact resistance of the first electrode. Further, since at least a part of the first electrode is covered with the second electrode material, the electrode on the semiconductor layer on which the first electrode is formed can be formed thick, and as a result, the first electrode The resistance from the semiconductor layer in which the electrode is formed to the contact hole for the wiring electrode on the first electrode can be reduced. In addition, since the first mask pattern and the second mask pattern are formed at the same time, a semiconductor device with improved electrical characteristics can be manufactured without increasing manufacturing steps and manufacturing costs.

(2) In the method of manufacturing a semiconductor device according to the above aspect, the first electrode and the second electrode may include the same metal material. According to the manufacturing method of this aspect, in the step (C), the mask pattern is formed to cover the first electrode and the region where the second electrode is formed. Even if the second electrode includes the same metal material, the first electrode can be prevented from being damaged by etching in the step (D).

(3) In the method of manufacturing a semiconductor device according to the above aspect, the same metal material may be aluminum (Al). According to the manufacturing method of this aspect, even if the first electrode and the second electrode are configured to include aluminum (Al) that is the same metal material, the first electrode is etched in the step (D). Damage can be suppressed.

(4) In the semiconductor device manufacturing method of the above aspect, a gallium nitride (GaN) based semiconductor layer may be used as the semiconductor layer. According to this method of manufacturing a semiconductor device, the electrical characteristics of the GaN-based semiconductor device can be improved without increasing the number of manufacturing steps and increasing the manufacturing cost.

(5) In the method of manufacturing a semiconductor device according to the above aspect, the semiconductor device is a transistor; the first electrode is at least one of a source electrode and a drain electrode; and the second electrode is a gate electrode. Good. According to the manufacturing method of this embodiment, in the step (C), the first mask pattern that covers at least one of the source electrode and the drain electrode, and the second mask pattern that covers the region where the gate electrode is formed are: Since it is formed, in step (D), at least one of the source electrode and the drain electrode can be prevented from being damaged by etching. Therefore, a semiconductor device can be manufactured without increasing the contact resistance of at least one of the source electrode and the drain electrode. Furthermore, since at least part of the source electrode and the drain electrode is covered with the gate electrode material, the electrode on the semiconductor layer on which at least one of the source electrode and the drain electrode is formed can be formed thick, and as a result, The resistance from the semiconductor layer in which at least one of the source electrode and the drain electrode is formed to the contact hole for the wiring electrode on at least one of the source electrode and the drain electrode can be reduced. In addition, since the first mask pattern and the second mask pattern are formed at the same time, a transistor with improved electrical characteristics can be manufactured without increasing manufacturing steps and manufacturing costs.

(6) According to another aspect of the present invention, there is provided a semiconductor device manufactured by the semiconductor device method of the above aspect. According to the semiconductor device of this embodiment, it is possible to suppress an increase in contact resistance of the first electrode and improve electrical characteristics.

(7) In the semiconductor device of the above aspect, the second electrode material on the first electrode may cover a wider range than the first electrode. In the semiconductor device of this embodiment, the second electrode material on the first electrode covers a wider area than the first electrode, so that damage to the semiconductor layer due to etching can be suppressed. Moreover, it can suppress reliably that a 1st electrode is damaged by an etching.

(8) In the semiconductor device of the above aspect, the second electrode material covers the first electrode so that the end of the first electrode is exposed; the end of the first electrode May be formed on the semiconductor layer via a protective film. According to the semiconductor device of this aspect, since the second electrode material covers the first electrode so that the end portion of the first electrode is exposed, the first electrode and the first electrode in the first electrode are etched and etched. It is possible to prevent the region where the two electrode materials are stacked from being damaged, and to further miniaturize the semiconductor device. In addition, since the exposed end portion of the first electrode is formed over the semiconductor layer via the protective film, the semiconductor layer can be prevented from being damaged by etching.

  A plurality of constituent elements of each aspect of the present invention described above are not indispensable, and some or all of the effects described in the present specification are to be solved to solve part or all of the above-described problems. In order to achieve the above, it is possible to appropriately change, delete, replace with another new component, and partially delete the limited contents of some of the plurality of components. In order to solve part or all of the above-described problems or to achieve part or all of the effects described in this specification, technical features included in one embodiment of the present invention described above. A part or all of the technical features included in the other aspects of the present invention described above may be combined to form an independent form of the present invention.

  The present invention can be realized in various forms other than the semiconductor device manufacturing method and the semiconductor device described above. For example, power semiconductor devices used in applications that increase power efficiency, such as server power supplies and air conditioners equipped with semiconductor devices, power conditioners for solar power generation systems, quick chargers for electric vehicles (EVs), and power converters for railways Can be realized. Moreover, it is realizable with forms, such as a manufacturing apparatus which manufactures a semiconductor device.

  According to the present invention, in the step (C), the first mask pattern that covers the first electrode and the second mask pattern that covers the region where the second electrode is formed are formed. In the step (D), the first electrode can be prevented from being damaged by etching. Therefore, a semiconductor device can be manufactured without increasing the contact resistance of the first electrode. Further, since at least a part of the first electrode is covered with the second electrode material, the electrode on the semiconductor layer on which the first electrode is formed can be formed thick, and as a result, the first electrode The resistance from the semiconductor layer in which the electrode is formed to the contact hole for the wiring electrode on the first electrode can be reduced. In addition, since the first mask pattern and the second mask pattern are formed at the same time, a semiconductor device with improved electrical characteristics can be manufactured without increasing manufacturing steps and manufacturing costs.

It is a figure which shows typically the structure of the semiconductor device in 1st Embodiment. 3 is a flowchart showing a method for manufacturing a semiconductor device. It is a figure which shows a laminated body. It is a figure which shows the semiconductor device in a manufacturing process in which the recess was formed. It is a figure which shows the semiconductor device in a manufacture process in which the recess and the trench were formed. It is a figure which shows the semiconductor device in a manufacture process in which the insulating film was formed. It is a figure which shows the semiconductor device in a manufacture process in which the 1st electrode was formed. It is a figure which shows the semiconductor device in a manufacture process in which the gate electrode material was deposited. It is a figure which shows the semiconductor device in a manufacture process in which the mask pattern was formed. It is a figure which shows the semiconductor device in a manufacture process in which the gate electrode was formed. It is a figure which shows the semiconductor device manufactured by the manufacturing method of this embodiment. It is a figure which shows the semiconductor device from which the location in which the contact hole for the wiring electrode on a 1st electrode was formed differs. It is a figure which shows the semiconductor device for the evaluation test in a manufacture process. It is a figure which shows the semiconductor device for evaluation tests in which the dry etching was performed. It is a figure which shows the result of having evaluated contact resistance. It is a figure which shows the result of having evaluated on-resistance. It is a figure which shows typically the structure of the semiconductor device in the 1st modification of 1st Embodiment. It is a figure which shows typically the structure of the semiconductor device in the 2nd modification of 1st Embodiment. It is a figure which shows typically the structure of the semiconductor device in the 3rd modification of 1st Embodiment. It is a figure which shows typically the structure of the semiconductor device in 2nd Embodiment. It is a figure which shows typically the structure of the semiconductor device in the 1st modification of 2nd Embodiment. It is a figure which shows typically the structure of the semiconductor device in the 2nd modification of 2nd Embodiment. It is a figure which shows typically the structure of the semiconductor device in the 3rd modification of 2nd Embodiment.

A. First embodiment:
A1. Semiconductor device configuration:
FIG. 1 is a diagram schematically showing the configuration of the semiconductor device 18 in the first embodiment. In FIG. 1, a part of the cross section of the semiconductor device 18 in this embodiment is simplified and shown. FIG. 1 is a diagram for clearly showing the technical features of the semiconductor device 18 and does not accurately show the dimensions of each part. FIG. 1 also shows XYZ axes orthogonal to each other for ease of explanation. FIG. 1 shows a state where a region between the region (a) and the region (b) of the semiconductor device 18 in this embodiment is omitted by using double wavy lines. The same applies to the subsequent drawings.

  The semiconductor device 18 in the present embodiment is a GaN-based trench gate type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 18 is used for power control, for example, and is also called a power device.

  The semiconductor device 18 includes a substrate 110, a first semiconductor layer 120, a second semiconductor layer 130, a third semiconductor layer 140, a recess 220, a trench 250, an insulating film 260, a gate electrode 275, and a body electrode. 230, a source electrode 240, and a gate electrode material 270. The semiconductor device 18 is an NPN-type semiconductor device in which an N-type semiconductor first semiconductor layer 120, a P-type semiconductor second semiconductor layer 130, and an N-type semiconductor third semiconductor layer 140 are sequentially stacked. It has a structure.

  In the present embodiment, the structure in which the body electrode 230 and the source electrode 240 are stacked corresponds to the “first electrode (hereinafter also referred to as the first electrode 245)” of the present application, and the gate electrode 275 is the same as that of the present application. This corresponds to “second electrode”. The gate electrode material 270 corresponds to the “second electrode material” of the present application. The structure in which the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140 are stacked is also referred to as “stacked body 11”, and the + Z direction (the direction in which each layer is stacked) is “upward”. The −Z direction is also referred to as “downward”. Of the surfaces of the respective configurations included in the semiconductor device 10, the upper surface is also referred to as “upper surface” and the lower surface is also referred to as “lower surface”.

The substrate 110 of the semiconductor device 10 has a plate shape that extends along the XY plane. The substrate 110 is a GaN-based substrate and contains Si as a dopant (donor). In the present embodiment, the average concentration of silicon in the entire region of the substrate 110 is 1.0 · 10 ¹⁸ cm ⁻³ .

The first semiconductor layer 120 is formed in a state of being stacked on the upper surface of the substrate 110. The first semiconductor layer 120 is a GaN-based semiconductor and contains Si as a dopant (donor) at a concentration lower than that of the substrate 110. In the present embodiment, the average concentration of silicon in the entire area of the first semiconductor layer 120 is 1.0 · 10 ¹⁶ cm ⁻³ . The thickness of the first semiconductor layer 120 in the + Z direction is 10 μm (micrometer).

The second semiconductor layer 130 is formed in a state of being stacked on the upper surface of the first semiconductor layer 120. The second semiconductor layer 130 is a GaN-based semiconductor and contains magnesium (Mg) as a dopant (acceptor). In the present embodiment, the average concentration of magnesium in the entire area of the second semiconductor layer 130 is 1.0 · 10 ¹⁸ cm ⁻³ . The thickness of the second semiconductor layer 130 in the + Z direction is 1.0 μm.

The third semiconductor layer 140 is formed in a state of being stacked on the upper surface of the second semiconductor layer 130. The third semiconductor layer 140 is a GaN-based semiconductor, and contains Si as a dopant (donor) at a higher concentration than the first semiconductor layer 120. In the present embodiment, the average concentration of silicon in the entire region of the third semiconductor layer 140 is 3.0 · 10 ¹⁸ cm ⁻³ . The thickness of the third semiconductor layer 140 in the + Z direction is 0.3 μm.

  The trench 250 is formed so as to reach the first semiconductor layer 120 from the upper surface of the third semiconductor layer 140 through the second semiconductor layer 130 by dry etching the stacked body 11. The recess 220 is formed so as to reach the second semiconductor layer 130 from the upper surface of the third semiconductor layer 140 by dry etching the stacked body 11. The side surfaces of the trench 250 and the recess 220 do not need to be perpendicular to the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140, and the side surfaces may be inclined. Good.

The insulating film 260 is a film formed so as to continuously cover the trench 250 and the upper surface of the third semiconductor layer 140 other than the region where the first electrode 245 is formed. In the present embodiment, the insulating film 260 is formed of silicon oxide (SiO ₂ ).

  The gate electrode 275 is an electrode formed so as to continuously cover the trench 250 and the upper surface of the third semiconductor layer 140 at the periphery of the trench 250 with the insulating film 260 interposed therebetween. In the present embodiment, the gate electrode 275 is made of Al. Although FIG. 1 shows an example in which a part of the gate electrode is extended in the Y direction, a part of the gate electrode may be extended in the X direction (+ X direction or −X direction). . A contact hole 331 for the wiring electrode 330 (see FIG. 11) is formed in the extended portion.

  The body electrode 230 is an electrode formed in the recess 220 so as to be in contact with the second semiconductor layer 130. The body electrode 230 is formed by laminating a layer made of molybdenum (Mo) and a layer made of palladium (Pd) and then performing heat treatment, and the layer made of Pd is positioned below (on the second semiconductor layer 130 side). It has the structure to do.

  The source electrode 240 is an electrode formed so as to cover the third semiconductor layer 140 and the body electrode 230. The source electrode 240 is formed by laminating a layer made of Al and a layer made of Ti and then heat-treating, and has a structure in which the layer made of Ti is located below (the third semiconductor layer 140 side). The upper surface of the first electrode 245 including the body electrode 230 and the source electrode 240 is covered with a gate electrode material 270 made of the same material as the gate electrode 275. In the present embodiment, the gate electrode material 270 on the first electrode 245 covers a wider area than the first electrode 245. Specifically, as shown in FIG. 1, the gate electrode material 270 is continuously formed on the first electrode 245 and on the third semiconductor layer 140 via the insulating film 260 around the periphery of the first electrode 245. Covering.

A2. Manufacturing method of semiconductor device:
FIG. 2 is a flowchart illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a view showing the laminated body 11. In order to manufacture the semiconductor device, first, the stacked body 11 is prepared in which the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140 are stacked on the substrate 110 (step S10). The stacked body 11 is manufactured by sequentially stacking the first semiconductor layer 120, the second semiconductor layer 130, and the third semiconductor layer 140 on the substrate 110 by crystal growth by MOCVD (Metal Organic Chemical Vapor Deposition) method. Is done.

Next, by performing dry etching on the stacked body 11, a recess 220 is formed as shown in FIG. 4, and a trench 250 is formed as shown in FIG. 5 (step S20). In this embodiment, in step S20, dry etching using a chlorine-based gas (for example, a mixed gas of BCl ₃ and Cl ₂ ) is performed. Further, in step S20, after dry etching is performed, heat treatment for recovering damage due to dry etching and activating the acceptor is performed. FIG. 4 is a diagram showing the semiconductor device 12 in the manufacturing process in which the recess 220 is formed. FIG. 5 is a diagram illustrating the semiconductor device 13 in the manufacturing process in which the recess 220 and the trench 250 are formed.

  Next, with respect to the semiconductor device 13 in the manufacturing process in which the recess 220 and the trench 250 are formed, an insulating film 260 is formed so as to cover the recess 220, the trench 250, and the upper surface of the third semiconductor layer 140 as shown in FIG. It is formed (step S30). FIG. 6 is a diagram illustrating the semiconductor device 14 in the manufacturing process in which the insulating film 260 is formed.

  Next, as shown in FIG. 7, the first electrode 245 is formed (step S40). Specifically, first, after the insulating film 260 in the region for forming the first electrode 245 on the semiconductor layer is removed, the body electrode 230 is formed in the recess 220 so as to be connected to the second semiconductor layer 130. Then, the source electrode 240 is formed so as to be connected to the third semiconductor layer 140 (step S44). In step S44, heat treatment for reducing contact resistance is performed. This heat treatment may be performed in step S42 and step S44, respectively. That is, heat treatment for the body electrode 230 may be performed after the formation of the body electrode 230, and heat treatment for the source electrode 240 may be performed after the formation of the source electrode 240.

  FIG. 7 is a diagram showing the semiconductor device 15 in the manufacturing process in which the first electrode 245 is formed. In FIG. 7, the source electrode 240 and the insulating film 260 formed on the third semiconductor layer 140 are in contact with each other, but the source electrode 240 and the insulating film 260 are not necessarily in contact with each other.

  When the first electrode 245 is formed, a gate electrode that is a second electrode material is formed on the entire upper surface of the semiconductor device 15 in the manufacturing process in which the first electrode 245 is formed by sputtering as shown in FIG. Material 270 is deposited (step S50). That is, by performing step S50, the gate electrode material 270 is deposited simultaneously on the first electrode 245 and the region where the gate electrode 275 is formed, including regions other than those regions. The FIG. 8 is a diagram showing the semiconductor device 16 in the manufacturing process in which the gate electrode material 270 is deposited. In the present specification, “simultaneous” means “by the same process”, and the times do not necessarily coincide completely. In the present embodiment, the gate electrode material 270 is simultaneously deposited on the first electrode 245 and the region where the gate electrode 275 is formed. However, the gate electrode material 270 is the first electrode. It may be deposited separately on 245 and on the region where the gate electrode 275 is formed.

  Next, as shown in FIG. 9, mask patterns 311 and 312 made of photoresist are simultaneously formed on the first electrode 245 and on the region where the gate electrode 275 that is the second electrode is formed (see FIG. 9). Step S60). In the present embodiment, the mask pattern 311 formed on the first electrode 245 covers a wider range than the first electrode. The mask pattern 311 formed on the first electrode 245 corresponds to the “first mask pattern” of the present application, and the mask pattern 312 formed on the region where the gate electrode 275 is formed is the “second mask pattern” of the present application. It corresponds to a “mask pattern”. FIG. 9 is a diagram showing the semiconductor device 17 in the manufacturing process in which the mask patterns 311 and 312 are formed.

  When the mask patterns 311 and 312 are formed, the gate electrode material 270 other than the region covered with the mask patterns 311 and 312 is etched by dry etching using a chlorine-based gas (step S70). After the gate electrode material 270 is etched, the mask patterns 311 and 312 are removed (step S80). Thus, the gate electrode 275 is formed.

  FIG. 10 is a diagram showing the semiconductor device 18 in the manufacturing process in which the gate electrode 275 is formed. When the dry etching is performed and the mask patterns 311 and 312 are removed, as shown in FIG. 10, the first semiconductor 140 and the third semiconductor layer 140 on the periphery of the first electrode 245 are interposed. In this state, the gate electrode material 270 is left.

Next, after the interlayer insulating film 320 formed of, for example, SiO ₂ is deposited and the contact hole 331 is formed on the semiconductor device 18 in the manufacturing process in which the gate electrode 275 is formed, as shown in FIG. Then, the wiring electrode 330 is formed (step S90). The contact hole 331 is formed by removing a part of the interlayer insulating film 320 on the upper surface of the source electrode 240 and a part of the interlayer insulating film 320 on the upper surface of the gate electrode 275. The wiring electrode 330 is formed on the body electrode 230 and the source electrode 240 in the contact hole 331, on the gate electrode 275 in the contact hole 331, the side wall of the contact hole 331, and a part on the interlayer insulating film 320. Is done. Thereafter, the drain electrode 210 is formed on the lower surface of the substrate 110, and a heat treatment for reducing contact resistance is performed, whereby the semiconductor device 10 is manufactured. In this embodiment, the drain electrode 210 is formed by laminating a layer made of Ti and a layer made of Al and then heat-treating, and has a structure in which the layer made of Ti is located above (the lower surface side of the substrate 110). Have. FIG. 11 is a diagram illustrating the semiconductor device 10 manufactured by the manufacturing method of the present embodiment.

  Note that the contact hole 331 for the wiring electrode 330 on the gate electrode 275 shown in FIG. 11 is formed offset from the trench 250 in the lateral direction. On the other hand, the contact hole 331 for the wiring electrode 330 on the gate electrode 275 may be formed immediately above the trench 250. Further, the contact hole 331 for the wiring electrode 330 on the first electrode 245 shown in FIG. 11 is directly above the first electrode 245 (in FIG. 11, just above the recess 220 via the first electrode 245). ). On the other hand, the contact hole 331 for the wiring electrode 330 on the first electrode 245 may be formed offset from the position directly above the first electrode 245.

  FIG. 12 is a diagram showing a semiconductor device 20 in which a contact hole 331 for the wiring electrode 330 on the first electrode 245 is different from the above-described semiconductor device 10 (FIG. 11). In the semiconductor device 20, a contact hole 331 for the wiring electrode 330 on the first electrode 245 is formed offset from right above the first electrode 245. Further, the distance L1 between the contact hole 331 for the wiring electrode 330 on the first electrode 245 and the gate (in FIG. 12, the portion where the gate trench 250 is formed) is the distance between the first electrode 245 and the gate. Greater than L2. Such a semiconductor device 20 may be formed by the manufacturing method described above. In FIG. 12, a region (A) in which the first electrode 245 is formed and the gate electrode 275 is formed in the gate trench 250 and a contact hole 331 for the wiring electrode 330 on the first electrode 245 are formed. The formed region (B) and the region (C) in which the contact hole 331 for the wiring electrode 330 on the gate electrode 275 is formed are shown. The region (A), the region (B), and the region A portion between (B) and region (C) is omitted. In the regions (A), (B), and (C), XYZ axes corresponding to the respective regions are shown. As shown in FIG. 12, in the regions (B) and (C), the wiring electrode 330 may be pulled out in the + X direction, or may be pulled out in the −X direction.

A3. Evaluation test:
Next, a test for evaluating the on-resistance of the semiconductor device manufactured by the above-described method and the contact resistance of the source electrode 240 portion was performed. For comparison, a semiconductor device for evaluation test, which was manufactured by changing the mask pattern forming step (FIG. 2, step S60) among the above-described manufacturing methods, was prepared.

  FIG. 13 is a diagram showing a semiconductor device 27 for an evaluation test in the manufacturing process. In the manufacture of the semiconductor device of the above-described embodiment, the first mask pattern 311 and the second mask pattern 312 are simultaneously formed. However, in the manufacture of the semiconductor device for evaluation test, first, as shown in FIG. A mask pattern 312 covering only a region where the gate electrode 275 as the second electrode is formed was formed.

  Next, similarly to the above-described manufacturing method, dry etching (FIG. 2, step S70) was performed on the semiconductor device 27 for the evaluation test in the manufacturing process. Thereafter, as shown in FIG. 14, the mask pattern 312 was removed from the semiconductor device 27 subjected to the dry etching (FIG. 2, step S80). In this way, a semiconductor device 28 for evaluation test was prepared. FIG. 14 is a view showing the semiconductor device 28 for evaluation test in which the dry etching is performed and the mask pattern 312 is removed. The semiconductor device 28 is formed by performing dry etching in a state where the mask pattern 312 covering only the region where the gate electrode 275 is formed is formed and the mask pattern 311 is not formed on the source electrode 240. Therefore, as shown in FIG. 14, a part of the source electrode 240 and the body electrode 230 is damaged by dry etching.

FIG. 15 is a diagram showing the results of evaluating the contact resistance (contact resistance) of the source electrode 240 portion. FIG. 15 shows a contact resistance evaluation test element (hereinafter referred to as sample 1) manufactured by the method of this embodiment, and a contact made without forming a mask pattern 311 on the first electrode 245. A contact resistance with an element for resistance evaluation test (hereinafter, sample 2) is shown. As shown in FIG. 15, the average value of the contact resistance of the source electrode 240 portion of sample 1 was 4.8 × 10 ⁻⁶ (Ω · cm ² ), whereas the contact of the source electrode portion of sample 2 was The average value of the resistance was as high as 2.9 × 10 ⁻⁴ (Ω · cm ² ). Further, the variation in the contact resistance value in the sample 2 was larger than the variation in the contact resistance value in the sample 1.

  FIG. 16 is a diagram illustrating a result of evaluating the on-resistance. FIG. 16 shows an element in which a wiring electrode is formed on the semiconductor device 18 manufactured by the method of this embodiment, that is, the semiconductor device 10 of this embodiment (hereinafter referred to as sample 3), and a mask pattern forming process (FIG. 2, The on-resistance measured using the element (hereinafter, sample 4) in which the wiring electrode is formed in the semiconductor device for evaluation test 28 manufactured by varying step S60) is measured using sample 3. It is shown as a relative ratio when the on-resistance is 1. As shown in FIG. 16, the on-resistance of sample 4 was about 1.5 to 4 times the on-resistance of sample 3. Further, as shown in FIG. 16, the value of the on-resistance of Sample 4 was varied.

A4. effect:
A4-1. Effect 1:
According to the first embodiment described above, the mask patterns 311 and 312 covering the first electrode 245 and the region where the gate electrode 275 (second electrode) is formed in the manufacture of the semiconductor device. Is formed. Therefore, damage to the first electrode 245 can be suppressed in etching for forming the gate electrode 275. Therefore, as in the present embodiment, even when the first electrode 245 and the second electrode 275 include the same material (Al), the semiconductor device without increasing the contact resistance of the first electrode 245 Can be manufactured.

A4-2. Effect 2:
Furthermore, since the first electrode 245 is covered with the gate electrode material 270 (second electrode material), the electrode on the semiconductor layer on which the first electrode 245 is formed can be formed thick, and as a result. The resistance from the semiconductor layer in which the first electrode 245 is formed to the contact hole 331 for the wiring electrode 330 formed on the first electrode 245 can be reduced. 12, the distance L1 between the contact hole 331 for the wiring electrode 330 on the first electrode 245 and the gate is the distance between the semiconductor layer on which the first electrode 245 is formed and the gate. When it is larger than L2, the resistance from the semiconductor layer in which the first electrode 245 is formed to the contact hole 331 for the wiring electrode 330 formed on the first electrode 245 can be further reduced. it can.

A4-3. Effect 3:
Furthermore, according to the manufacturing method of the present embodiment, the gate electrode material 270 is in a wider range than the first electrode 245, that is, via the insulating film 260 on the first electrode 245 and the periphery of the first electrode 245. Since the semiconductor layer (semiconductor device) is integrally covered, it is possible to prevent the semiconductor layer from being damaged by etching. In addition, since the gate electrode material 270 covers all over the first electrode 245, the first electrode 245 can be reliably prevented from being damaged.

A4-4. Effect 4:
In the manufacturing method of this embodiment, mask patterns 311 and 312 are simultaneously formed on the first electrode 245 and the region where the gate electrode 275 (second electrode) is formed, and then etching is performed. After performing, the mask patterns 311 and 312 are removed. Therefore, in order to protect the first electrode 245, the wiring electrode 330 is formed in step S90 in FIG. 2 rather than the method of forming a protective film (insulating film) instead of the mask pattern 311 on the first electrode 245. Therefore, a contact hole can be easily formed. When the protective film is formed on the first electrode 245, the interlayer insulating film 320 (FIG. 9) is deposited on the protective film (insulating film) prior to the formation of the wiring electrode 330. In this embodiment, the first mask pattern 312 is removed at the same time as the first mask pattern 312 is removed, whereas the protective film and the deposited interlayer insulating film 320 must be etched. This is because the first mask pattern 311 on the electrode 245 is also removed, so that only the interlayer insulating film 320 needs to be etched when the contact hole is formed. Therefore, according to the present embodiment, since the contact hole can be easily formed, the manufacturing process can be shortened.

A5. First modification of the first embodiment:
FIG. 17 is a diagram schematically showing the configuration of the semiconductor device 19 in the first modification of the first embodiment. A semiconductor device 19 shown in FIG. 17 is a semiconductor device manufactured by the method for manufacturing a semiconductor device of the above-described embodiment (FIG. 2), and the mask pattern is removed in step S80. The difference between the semiconductor device 19 and the semiconductor device 18 of the above-described embodiment is that the end portion 247 of the source electrode 240 of the first electrode 245 is not covered with the gate electrode material 270 and is exposed. The end portion 247 is formed on the third semiconductor layer 140 with the insulating film 260 interposed therebetween. Even such a semiconductor device 19 has the same effects as the effects 1, 2, and 4 of the above-described embodiment. Even if the end portion 247 of the source electrode 240 is exposed, the other region of the first electrode 245 is covered with the gate electrode material 270, so that the body electrode 230 in the first electrode 245 and the other region of the first electrode 245 are etched. Damage to the region where the source electrode 240 is stacked can be suppressed. Furthermore, since the stacked structure of the first electrode 245 and the gate electrode material 270 can be reduced as compared with the above-described embodiment, the semiconductor device can be miniaturized. Further, since the exposed end portion 247 of the source electrode 240 is formed over the third semiconductor layer 140 with the insulating film 260 interposed therebetween, it is possible to suppress damage to the semiconductor layer (third semiconductor layer 140) due to etching. be able to.

A6. Second modification of the first embodiment:
FIG. 18 is a diagram schematically illustrating the configuration of the semiconductor device 30 according to the second modification of the first embodiment. A semiconductor device 30 shown in FIG. 18 is a semiconductor device manufactured by the method for manufacturing a semiconductor device of the above-described embodiment (FIG. 2), and the mask pattern is removed in step S80. The difference between the semiconductor device 30 and the semiconductor device 10 of the above-described embodiment is that the end surface 279 of the gate electrode material 270 formed on the source electrode 240 and the end surface 249 of the source electrode 240 are aligned. . Even such a semiconductor device 30 has the same effect as the above-described embodiment. Further, since the stacked structure of the first electrode 245 and the gate electrode material 270 can be made smaller than that in the above embodiment, the semiconductor device can be miniaturized.

A7. Third modification of the first embodiment:
FIG. 19 is a diagram schematically illustrating a configuration of the semiconductor device 40 according to the third modification of the first embodiment. A semiconductor device 40 shown in FIG. 19 is a semiconductor device manufactured by the method for manufacturing a semiconductor device of the above-described embodiment (FIG. 2), and the mask pattern is removed in step S80. The difference between the semiconductor device 40 and the semiconductor device 10 of the above-described embodiment is that the end portion 247 of the source electrode 240 is not covered with the gate electrode material 270 and is exposed. Even such a semiconductor device has the same effects as the effects 1, 2, and 4 of the above-described embodiment. Even if the end portion 247 of the source electrode 240 is exposed, the other region of the source electrode 240 is covered with the gate electrode material 270. Therefore, the body electrode 230 and the source electrode 240 in the first electrode 245 are etched. It is possible to suppress damage to the region where the layers are stacked. Furthermore, since the stacked structure of the first electrode 245 and the gate electrode material 270 can be reduced as compared with the above-described embodiment, the semiconductor device can be miniaturized.

A8. Fourth modification of the first embodiment:
In the above-described embodiment, the first electrode 245 is formed by laminating a layer made of Al and a layer made of Ti and then heat-treating, and the layer made of Ti is below (the third semiconductor layer 140 side). A source electrode 240 having a structure located at a position. On the other hand, the stacked structure of the source electrode 240 may be formed using titanium nitride (TiN), vanadium (V), hafnium (Hf), zirconium (Zr), or the like instead of Ti. The stacked structure of the source electrode 240 may be formed using AlSi, AlCu, AlSiCu, AlSiTa, or the like containing 90% or more of Al instead of Al in the above-described embodiment. Furthermore, these laminated structures, for example, a laminated structure of three or more layers such as V / AlSi / Ti may be used. In the above-described embodiment, the gate electrode 275 and the gate electrode material 270 are made of Al. On the other hand, the gate electrode 275 and the gate electrode material 270 may be formed using AlSi, AlCu, AlSiCu, AlSiTa, or the like containing 90% or more of Al instead of Al in the above-described embodiment. Further, Ni may be used instead of Al in the above-described embodiment. Furthermore, a laminated structure of Al, AlSi or Ni and Ti, TiN, V, Hf, Zr or the like, for example, a laminated structure of TiN / AlSi / TiN or the like may be used. Even with such a structure, the same effects as those of the above-described embodiment can be obtained.

A9. Fifth modification of the first embodiment:
In the above-described embodiment, the first electrode 245, the second electrode (gate electrode 275), and the gate electrode material 270 may be made of a material that is highly reactive with the same etching gas or wet etching solution. Good. For example, the first electrode 245, the second electrode (gate electrode 275), and the gate electrode material 270 are made of 90% Al, AlSi, and other Al that are highly reactive to chlorine-based gas and hydrofluoric acid-based wet etching. % Si or AlCu, AlSiCu, AlSiTa, Ti, TiN, V, Hf, Zr, or the like. Also, highly reactive Al, AlSi, AlSi, AlSiCu, AlSiTa containing 90% or more Al, and Ni, Ti, TiN, V, Hf, etc. It may be composed of Zr or the like. With such a structure, the effect of the above-described embodiment can be further improved.

B. Second embodiment:
B1. Semiconductor device configuration:
In the first embodiment described above, the configuration of the vertical MOSFET has been described. In contrast, in the second embodiment, a configuration of a lateral MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) will be described.

  FIG. 20 is a diagram schematically illustrating the configuration of the semiconductor device 50 according to the second embodiment. The semiconductor device 50 is a MISFET made of a GaN-based semiconductor having a recess structure.

  The semiconductor device 50 includes a substrate 112, a buffer layer 122, a carrier traveling layer 132, a barrier layer 142, a source electrode 242, a drain electrode 212, a recess 252, an insulating film 262, a gate electrode 272, and a gate. An electrode material 274. The semiconductor device 50 has a structure in which a substrate 112, a buffer layer 122, a carrier traveling layer 132, and a barrier layer 142 are sequentially stacked.

  In the present embodiment, the source electrode 242 and the drain electrode 212 respectively correspond to the “first electrode” of the present application. The gate electrode material 274 corresponds to the “second electrode material” of the present application. The structure in which the substrate 112, the buffer layer 122, the carrier traveling layer 132, and the barrier layer 142 are sequentially stacked is also referred to as a “stacked body”, and the + Z direction (the direction in which each layer is stacked) is “upward”. , −Z direction is also referred to as “downward”. Of the surfaces of the respective configurations included in the semiconductor device 10, the upper surface is also referred to as “upper surface” and the lower surface is also referred to as “lower surface”.

The substrate 112 of the semiconductor device 50 has a plate shape extending along the XY plane. The substrate 112 is made of Si. The buffer layer 122 is formed in a state of being stacked on the upper surface of the substrate 112. The buffer layer 122 is a multilayer nitride semiconductor layer in which a thick undoped GaN layer is stacked on a thin undoped AlN layer. The carrier traveling layer 132 is made of undoped GaN. The barrier layer 142 is formed of a nitride semiconductor layer having a wider forbidden band than the carrier traveling layer 132 and supplies carriers to the carrier traveling layer 132. The barrier layer 142 is made of undoped Al _0.25 Ga _0.75 N. At the heterojunction interface between the carrier traveling layer 132 and the barrier layer 142, two-dimensional electron gas is generated on the carrier traveling layer 132 side due to the influence of positive polarization charges.

  In the present embodiment, the barrier layer 142 is formed of one undoped layer AlGaN, but in other embodiments, the barrier layer 142 is composed of multiple layers such as GaN / AlGaN, InGaN / AlGaN, InGaN / AlGaN / AlN. It may be formed of a nitride semiconductor layer. The barrier layer 142 is a single layer or multiple layers such as a nitride semiconductor layer made of one layer such as doped AlGaN, AlInN, AlGaInN, or a multi-layer AlGaN layer containing a plurality of AlGaN layers having different Al compositions and doping concentrations. Other semiconductor layers comprising undoped or doped layers may be used. Further, each of the carrier traveling layer 132 and the barrier layer 142 is only one layer, but one or more carrier traveling layer / barrier layer pairs may be provided on the barrier layer 142.

  The recess 252 is formed by digging from the upper surface of the barrier layer 142 to a partial depth of the carrier traveling layer 132 by dry etching. The depth of the recess 252 is such that the source electrode 242 and the gate are formed in order to suppress the current between the source electrode 242 and the drain electrode 212 and realize normally-off in a state where no gate voltage is applied to the gate electrode 272. The two-dimensional electron gas between the electrodes 272 and the two-dimensional electron gas between the gate and the drain are formed so as to be sufficiently separated without applying a gate voltage. The side surface of the recess 252 does not need to be perpendicular to the carrier traveling layer 132 and the barrier layer 142, and the side surface may be formed to be inclined.

The insulating film 262 is a film formed to continuously cover the recess 252 and the upper surface of the barrier layer 142 other than the region where the source electrode 242 and the drain electrode 212 are formed. In the present embodiment, the insulating film 262 is formed of SiO ₂ .

  The gate electrode 272 is an electrode formed to continuously cover the recess 252 and the upper surface of the barrier layer 142 at the periphery of the recess 252 with the insulating film 262 interposed therebetween. In the present embodiment, the gate electrode 272 is made of Al.

  The source electrode 242 and the drain electrode 212 are formed so as to be in contact with the barrier layer 142 as shown in FIG. The source electrode 242 and the drain electrode 212 are formed by laminating a layer made of Al and a layer made of Ti and then heat-treating, and have a structure in which the layer made of Ti is located below (the barrier layer 142 side). . The source electrode 242 and the drain electrode 212 are in ohmic contact with the carrier traveling layer 132 by a tunnel current mechanism through the barrier layer 142.

  The upper surface of the source electrode 242 and the upper surface of the drain electrode 212 are covered with a gate electrode material 274 made of the same material as the gate electrode 272. In the present embodiment, the gate electrode material 274 on the source electrode 242 covers a wider range than the source electrode 242. The gate electrode material 274 on the drain electrode 212 also covers a wider area than the drain electrode 212. Specifically, as illustrated in FIG. 20, the gate electrode material 274 continuously covers the upper surface of the source electrode 242 and the barrier layer 142 via the insulating film 262 around the source electrode 242. The gate electrode material 274 continuously covers the upper surface of the drain electrode 212 and the barrier layer 142 with the insulating film 262 around the drain electrode 212 interposed therebetween.

B2. Manufacturing method of semiconductor device:
The difference between the manufacturing method of the semiconductor device in the present embodiment and the manufacturing method of the semiconductor device in the first embodiment described above is that the recess 220 and the trench 250 are formed in step S20 (FIG. 2) of the first embodiment. On the other hand, in the present embodiment, the recess 252 is formed. In step S40 (FIG. 2) of the first embodiment, the body electrode 230 and the source electrode 240 are formed as the first electrode, whereas in the present embodiment, the source electrode 242 and the source electrode 242 are formed as the first electrode. The drain electrode 212 is formed. Note that the source electrode 242 and the drain electrode 212 may be formed simultaneously or separately. Other points of the manufacturing method of the semiconductor device in the present embodiment are the same as those of the manufacturing method of the first embodiment described above.

  That is, also in this embodiment, the gate electrode material 274 that is the second electrode material is deposited on the entire surface of the semiconductor layer (FIG. 2, step S50), and the source electrode 242 and the drain electrode 212 that are the first electrodes are formed. The covering first mask pattern 311 and the second mask pattern 312 covering the region where the gate electrode 272 is formed are formed simultaneously (FIG. 2, step S60). Thereafter, the gate electrode material 274 in a portion other than the region covered with the mask patterns 311 and 312 is etched by dry etching using a chlorine-based gas (FIG. 2, step S70), and the mask patterns 311 and 312 are removed. (FIG. 2, step S80), the gate electrode 272 is formed. 20 is the semiconductor device 50 in which the gate electrode 272 is formed in step S80.

B3. effect:
According to 2nd Embodiment demonstrated above, there exists an effect similar to the above-mentioned 1st Embodiment.

B4. First modification of the second embodiment:
FIG. 21 is a diagram schematically illustrating the configuration of the semiconductor device 60 according to the first modification of the second embodiment. A semiconductor device 60 shown in FIG. 21 is a lateral MISHFET (Metal-Insulator-Semiconductor Field-Effect Transistor) made of an AlGaN / GaN-based semiconductor. A semiconductor device 60 shown in FIG. 21 is manufactured by the same method as that of the semiconductor device of the second embodiment described above, except that the gate electrode 272 is not formed in the recess 252, and the first mask pattern 311 and the second mask pattern 211 are formed. This is a semiconductor device from which the mask pattern 312 has been removed. Even such a semiconductor device has the same effect as the above-described embodiment.

B5. Second modification of the second embodiment:
FIG. 22 is a diagram schematically illustrating the configuration of the semiconductor device 70 according to the second modification of the second embodiment. A semiconductor device 70 shown in FIG. 22 is a lateral HFET (Heterostructure Field-Effect Transistor) made of an AlGaN / GaN-based semiconductor. The semiconductor device 70 shown in FIG. 22 is manufactured by the same method as the semiconductor device of the second embodiment described above except that the gate electrode 272 is formed so as to be in contact with the barrier layer 142, and the first mask is formed. In this semiconductor device, the pattern 311 and the second mask pattern 312 are removed. Even such a semiconductor device has the same effect as the above-described embodiment.

B6. Third modification of the second embodiment:
FIG. 23 is a diagram schematically illustrating a configuration of a semiconductor device 80 according to a third modification of the second embodiment. A semiconductor device 80 shown in FIG. 23 is a lateral MISFET made of a GaN-based semiconductor. The semiconductor device 80 includes a substrate 113, a buffer layer 123, a p-GaN layer 133, a source electrode 242, a drain electrode 212, an insulating film 262, a gate electrode 272, and a gate electrode material 274.

The substrate 113 is made of Si. The buffer layer 123 is formed in a state of being stacked on the upper surface of the substrate 112. The buffer layer 123 is a multilayer nitride semiconductor layer in which a thick undoped GaN layer is stacked on a thin undoped AlN layer. A high concentration n ⁺ GaN region 280 and a low concentration n ⁻ GaN region 290 are formed in the p-GaN layer 133 by ion implantation. The n ⁺ GaN region 280 and the n ⁻ GaN region 290 are not limited to ion implantation, and may be formed by other methods such as impurity diffusion and selective regrowth.

  A semiconductor device 80 shown in FIG. 23 is also a semiconductor device manufactured by the same method as that of the semiconductor device of the second embodiment described above, in which the first mask pattern 311 and the second mask pattern 312 are removed. Even such a semiconductor device has the same effect as the above-described embodiment.

B7. Fourth modification of the second embodiment:
In the second embodiment described above, the gate electrode material 274 on the source electrode 242 covers a wider area than the source electrode 242. Further, the gate electrode material 274 on the drain electrode 212 covers a wider area than the drain electrode 212. On the other hand, at least one of the end portion of the source electrode 242 and the end portion of the drain electrode 212 is exposed without being covered with the gate electrode material 274 as in the first modification of the first embodiment described above, and The end portion may be formed on the barrier layer 142 with the insulating film 262 interposed therebetween. Even such a semiconductor device has the same effect as the first modification of the first embodiment described above.

B8. Fifth modification of the second embodiment:
In the second embodiment described above, the gate electrode material 274 on the source electrode 242 covers a wider area than the source electrode 242. Further, the gate electrode material 274 on the drain electrode 212 covers a wider area than the drain electrode 212. On the other hand, at least one of the end face of the source electrode 242 and the end face of the drain electrode 212 may be aligned with the end face of the gate electrode material 274 as in the second modification of the first embodiment described above. Even such a semiconductor device has the same effect as the second modification of the first embodiment described above.

B9. Sixth modification of the second embodiment:
In the second embodiment described above, the gate electrode material 274 on the source electrode 242 covers a wider area than the source electrode 242. Further, the gate electrode material 274 on the drain electrode 212 covers a wider area than the drain electrode 212. On the other hand, even if at least one of the end portion of the source electrode 242 and the end portion of the drain electrode 212 is not covered with the gate electrode material 274 and exposed as in the third modification of the first embodiment described above. Good. Even such a semiconductor device has the same effect as the third modification of the first embodiment described above.

B10. Seventh modification of the second embodiment:
In the above-described embodiment, the first electrode (the source electrode 242 and the drain electrode 212) is formed by laminating a layer made of Al and a layer made of Ti, and then heat-treating, and the layer made of Ti is formed below. It has the structure located in. On the other hand, the laminated structure of the first electrodes (the source electrode 242 and the drain electrode 212) may be a structure as in the fourth modification of the first embodiment. In addition, the first electrode, the second electrode (gate electrode), and the gate electrode material are reactive to the same etching gas or wet etching solution as in the fifth modification of the first embodiment described above. You may be comprised with the high material.

C. Other variations:
C1. Modification 1:
In the various embodiments and modifications described above, a mixed gas of BCl ₃ and Cl ₂ that is a chlorine-based gas is used in the dry etching in step S80. On the other hand, dry etching may use, for example, any one of chlorine-based gases such as BCl ₃ , Cl ₂ , CCl ₄ , and SiCl ₄ , and chlorine other than a mixed gas of BCl ₃ and Cl _2. A mixed gas of a series of gases may be used, or a mixed gas of a chlorine-based gas and another gas (for example, argon gas) may be used.

C2. Modification 2:
In the various embodiments described above, the insulating films 260 and 262 are made of SiO ₂ . In contrast, the insulating films 260 and 262 may be formed of other materials such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN), hafnium oxide (HfO ₂ ), and zirconium oxide (ZrO ₂ ). Good. The insulating films 260 and 262 may have a multi-layer structure. For example, a ZrO ₂ / SiO ₂ structure in which ZrO ₂ is provided on SiO _2, a two-layer structure such as a HfO ₂ / SiO ₂ structure, an Al ₂ O ₃ / SiO ₂ structure, a SiO ₂ / SiN structure, A three-layer structure such as a ZrO ₂ / SiO ₂ / SiN structure in which SiO ₂ is provided thereon and further ZrO ₂ is provided thereon, and a HfO ₂ / Al ₂ O ₃ / SiO ₂ structure may be employed.

C3. Modification 3:
The material for forming each semiconductor layer in the various embodiments and modifications described above is merely an example, and other materials can be used. For example, in the above-described embodiment, each semiconductor layer is mainly composed of GaN. On the other hand, each semiconductor layer may be made of other materials such as aluminum nitride (AlN) and indium nitride (InN).

C4. Modification 4:
The semiconductor devices in the above-described various embodiments and modifications are not limited to power devices, and may be used in other devices such as high-frequency devices for communication such as a microwave band, and high-speed devices for logic ICs.

  The present invention is not limited to the above-described embodiments and modifications, and can be realized with various configurations without departing from the spirit thereof. For example, the technical features in the embodiments and the modifications corresponding to the technical features in each embodiment described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.

10, 12, 13, 14, 15, 16, 17, 18, 19, 20, 30, 40, 50, 60, 70, 80 ... Semiconductor device 27, 28 ... Semiconductor device for evaluation test 11 ... Laminated body 110, 112, 113 ... substrate 120 ... first semiconductor layer 122, 123 ... buffer layer 130 ... second semiconductor layer 132 ... carrier traveling layer 133 ... p-GaN layer 140 ... third semiconductor layer 142 ... barrier layer 210, 212 ... drain electrode 220, 252 ... recess 230 ... body electrode 240, 242 ... source electrode 245 ... first electrode 247 ... end of first electrode 249 ... end face of first electrode 250 ... trench 260, 262 ... insulating film 270, 274 ... Gate electrode material 272, 275 ... Gate electrode 279 ... End face of gate electrode material 280 ... n ⁺ GaN region 290 ... n ^- GaN region 3 DESCRIPTION OF SYMBOLS 11 ... 1st mask pattern 312 ... 2nd mask pattern 320 ... Interlayer insulation film 330 ... Wiring electrode 331 ... Contact hole

Claims (6)

A method of manufacturing a semiconductor device comprising a first electrode and a second electrode on a semiconductor layer,
(A) A step of forming the first electrode so that the semiconductor layer on which the insulating film is formed is in ohmic contact with the semiconductor layer and an end portion is located on the semiconductor layer through the insulating film. When,
(B) The first electrode and the region where the second electrode is formed so that the first electrode and the second electrode material that is the material of the second electrode are in contact with each other. A step of covering and simultaneously covering the second electrode material;
(C) A first mask pattern covering the first electrode covered with the second electrode material and the second electrode are formed so that an end of the first electrode is exposed. A step of simultaneously forming a second mask pattern covering a region to be formed;
(D) By etching the second electrode material exposed from the first mask pattern and the second mask pattern, an end portion of the first electrode is exposed from the second electrode material; And a step of forming a structure in which the second electrode material covers the first electrode, and the second electrode;
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device comprising a first electrode and a second electrode on a semiconductor layer,
(A) forming the first electrode so as to be in ohmic contact with the semiconductor layer with respect to the semiconductor layer on which the insulating film is formed;
(B) the first electrode that is in ohmic contact with the semiconductor layer, the insulating film, and a region where the second electrode on the insulating film is formed; the first electrode and the insulating film; A step of collectively covering with the second electrode material so that the second electrode material that is the material of the second electrode is in contact with the second electrode material;
(C) The first electrode in ohmic contact with the semiconductor layer covered with the second electrode material and the peripheral edge of the first electrode covered with the second electrode material via the insulating film Simultaneously forming a first mask pattern covering the semiconductor layer and a second mask pattern covering a region where the second electrode is formed;
(D) The first electrode in which the second electrode material is in ohmic contact with the semiconductor layer by etching the second electrode material exposed from the first mask pattern and the second mask pattern. A structure that integrally covers the top and the semiconductor layer on the periphery of the first electrode via the insulating film, and the second electrode whose end is located on the semiconductor layer via the insulating film; Forming a
Comprising
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the first electrode and the second electrode include the same metal material. A method of manufacturing a semiconductor device according to claim 3,
The method for manufacturing a semiconductor device, wherein the same metal material is aluminum (Al). It is a manufacturing method of the semiconductor device according to any one of claims 1 to 4,
A method for manufacturing a semiconductor device, wherein a gallium nitride (GaN) based semiconductor layer is used as the semiconductor layer. A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
The semiconductor device is a transistor;
The first electrode is at least one of a source electrode and a drain electrode;
The method for manufacturing a semiconductor device, wherein the second electrode is a gate electrode.

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