JP2018157222A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being miniaturized.SOLUTION: A semiconductor device comprises: a semiconductor element 200; a main lead 300 on which the semiconductor element 200 is arranged; a first sub-lead 400; and a resin package 800. The main lead 300 has a first part. The first sub-lead 400 has a second part. Dimensions in a thickness direction of the first and second parts are different from each other.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

  For example, a semiconductor device in which a semiconductor element such as a transistor is sealed with a resin package has been proposed. Patent Document 1 discloses a semiconductor device including a semiconductor element having three electrodes, three leads conducting to these electrodes, and a resin package covering each of the semiconductor element and each of the three leads. The three electrodes are formed on the same surface of the semiconductor element. The semiconductor element is bonded to one of the three leads. The three electrodes are electrically connected to the three leads through three wires. The resin package covers the entire semiconductor element, all of the three wires, and part of the three leads. Of the three leads, a portion protruding from the resin package serves as a terminal portion for mounting the semiconductor device.

  In the conventional semiconductor device, the lead for arranging the semiconductor element is larger than the semiconductor element in plan view. The size of the resin package is determined by this large lead. Therefore, a large lead hinders miniaturization of the semiconductor device.

  The three wires generally have a loop shape. For this reason, in order to cover the three wires appropriately, the resin package needs to have a corresponding height. This increases the height of the semiconductor device. At the same time, in order to properly bond the three wires, it is necessary to secure a certain distance between the so-called first bonding portion and the second bonding portion. Further, the terminal portions of the three leads protrude from the resin package. These increase the size in plan view of the semiconductor device. Thus, the semiconductor device has a problem that it is difficult to reduce the size.

JP 2012-190936 A

  The present invention has been conceived under the circumstances described above, and its main object is to provide a semiconductor device that can be miniaturized.

  According to a first aspect of the present invention, the semiconductor device includes: a semiconductor element; a main lead on which the semiconductor element is disposed; and a resin package that covers the semiconductor element and the main lead. The main lead is formed from the resin package. A semiconductor device is provided that is exposed and has a portion that does not overlap the main lead when viewed in the thickness direction of the semiconductor element.

  Preferably, the main lead has a main lead main surface and a main lead back surface facing opposite to each other, and the semiconductor element is disposed on the main lead main surface, and the main lead back surface is formed of the resin. Exposed from the package.

  Preferably, the main lead includes a main full thickness portion and a main eaves portion, and the main full thickness portion is a portion extending from the main lead main surface to the main lead back surface, and the main eave portion is the semiconductor The main full thickness portion protrudes in a direction perpendicular to the thickness direction of the element.

  Preferably, the semiconductor element entirely overlaps the main full thickness portion in the thickness direction view of the semiconductor element.

  Preferably, the semiconductor device further includes a first sub lead that conducts to the semiconductor element, the first sub lead being separated from the main lead and exposed from the resin package.

Preferably, the main eaves portion has a main front portion, and the main front portion protrudes from the main full thickness portion toward the first sub lead.

  Preferably, the main eaves portion has a main side portion, and the main side portion protrudes from the main full thickness portion in a direction perpendicular to a direction in which the main front portion protrudes. .

  Preferably, the main lead includes a main side connecting portion protruding from the main side portion, and the main side connecting portion has an end surface exposed from the resin package.

  Preferably, the main eaves portion has a main rear portion, and the main rear portion protrudes from the main full thickness portion in a direction opposite to a direction in which the main front portion protrudes.

  Preferably, the main lead includes a main rear connecting portion protruding from the main rear portion, and the main rear connecting portion has an end surface exposed from the resin package.

  Preferably, the main total thickness portion is entirely surrounded by the main eaves portion as viewed in the thickness direction of the semiconductor element.

  Preferably, the main eaves part entirely overlaps the semiconductor element when viewed in the thickness direction of the semiconductor element.

  Preferably, a main surface plating layer formed on the main lead and interposed between the semiconductor element and the main lead is further provided.

  Preferably, the main surface plating layer overlaps the entire main eaves part.

  Preferably, the semiconductor device further includes a first sub lead conducting to the semiconductor element, the first sub lead being spaced apart from the main lead, and an outer side of the resin package in the thickness direction of the semiconductor element Further, it is exposed from the resin package.

  Preferably, the first sub lead includes a first sub full thickness portion and a first sub eaves portion, and the first sub lead has a first sub lead main surface and a first sub lead back surface facing opposite to each other. And the first sub lead back surface is exposed from the resin package, and the first sub full thickness portion is a portion extending from the first sub lead main surface to the first sub lead back surface, The one sub eaves portion protrudes from the first sub full thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and constitutes the first sub lead main surface.

  Preferably, the first sub eaves portion has a first sub front portion, and the first sub front portion protrudes from the first sub full thickness portion toward the main lead.

  Preferably, the first sub full thickness portion is exposed from the resin package toward the outside of the resin package in the thickness direction view of the semiconductor element.

  Preferably, the first sub lead includes a first sub extension portion, extends from the first sub full thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and The back surface of the first sub lead is configured, and the first sub extension portion is exposed from the resin package toward the outside of the resin package in the thickness direction of the semiconductor element.

  Preferably, the first sub lead has a first sub lead main surface and a first sub lead back surface facing opposite sides, and the first sub lead back surface is exposed from the resin package.

  Preferably, the resin package has a resin back surface facing in the same direction as the first sub lead back surface, and the resin back surface is flush with the first sub lead back surface.

  Preferably, the first sub lead has a first sub lead end surface connected to the back surface of the first sub lead, and the first sub lead end surface faces the side opposite to the side where the main lead is located. .

  Preferably, the end face of the first sub lead is exposed from the resin package.

  Preferably, the resin package has a first resin end face facing in the same direction as a direction of the first sub lead end face, and the first resin end face is flush with the first sub lead end face. .

  Preferably, the first sub-lead has a first sub-lead side surface connected to the back surface of the first sub-lead, and the first sub-lead side surface corresponds to a direction of the first sub-lead end surface and a thickness of the semiconductor element. It faces in a direction that is perpendicular to any of the vertical directions.

  Preferably, the side surface of the first sub lead is exposed from the resin package.

  Preferably, the resin package has a first resin side surface facing in the same direction as the first sub lead side surface, and the first sub lead side surface is flush with the first resin side surface. .

  Preferably, the semiconductor device further includes a first wire that is directly connected to the semiconductor element and electrically connects the semiconductor element and the first sub lead.

  Preferably, a first sub plating layer interposed between the first sub lead and the first wire is further provided.

  Preferably, the semiconductor device further includes a second sub lead conducting to the semiconductor element, the second sub lead being separated from the main lead and the first sub lead, and in the thickness direction of the semiconductor element. The resin package is exposed outside the resin package.

  Preferably, the semiconductor device further includes a second wire that is directly connected to the semiconductor element and that electrically connects the semiconductor element and the second sub lead.

  Preferably, a second subplating layer interposed between the second sublead and the second wire is further provided.

  Preferably, the semiconductor element has a semiconductor layer stacked on each other, a eutectic layer of a semiconductor and a metal, and a single metal layer constituting the back electrode, and the single metal layer is directly bonded to the main lead. Has been.

  Preferably, the eutectic layer is made of a eutectic of Si and Au.

  Preferably, the single metal layer is thinner than the eutectic layer.

  Preferably, the semiconductor device further includes a first wire, and the semiconductor element includes a first surface electrode to which the first wire is bonded, and the first surface electrode has the main surface in the thickness direction of the semiconductor element. It overlaps the thick part.

  Preferably, the semiconductor device further includes a second wire, and the semiconductor element includes a second surface electrode to which the second wire is joined, and the second surface electrode is the main surface in the thickness direction of the semiconductor element. It overlaps the thick part.

  Preferably, the semiconductor device further includes a first wire and a second wire, and the semiconductor element includes a first surface electrode to which the first wire is bonded, a second surface electrode to which the second wire is bonded, And at least one of the first surface electrode and the second surface electrode overlaps the main full thickness portion in the thickness direction of the semiconductor element.

  According to the second aspect of the present invention, there are a front surface and a back surface facing in opposite directions in the thickness direction, a first surface electrode and a second surface electrode formed on the surface, and a back electrode formed on the back surface. A semiconductor element, a main lead having a die pad portion to which the back electrode is conductively connected, a main back terminal portion facing the opposite side of the die pad portion, and a first lead connected to the first surface electrode through a first wire A first sub-lead having a first wire bonding portion and a first sub-back terminal portion facing away from the first wire bonding portion; and a second wire bonding connected to the second surface electrode via a second wire A second sub lead having a second sub back terminal portion facing away from the second wire bonding portion, the semiconductor element, the main lead, the first sub lead, and And a resin package that covers each of the second sub-leads and exposes the main back terminal portion, the first sub back terminal portion, and the second sub back terminal portion on the same side, The main lead includes a main full thickness portion extending from the die pad portion to the main back surface terminal portion, and a main eaves portion protruding in a direction perpendicular to the thickness direction from the die pad portion side portion of the main full thickness portion. The die pad portion and the semiconductor element overlap both the main full thickness portion and the main eaves portion in a thickness direction view, and at least one of the first surface electrode and the second surface electrode. Is overlapped with the main eaves part, and the first wire is joined to the first bonding part joined to the first wire bonding part and the first surface electrode via the first bump. A second bonding portion, wherein the second wire is bonded to the second wire bonding portion, and the second bonding is bonded to the second surface electrode via a second bump. And a semiconductor device characterized by comprising:

  Preferably, the first surface electrode is a gate electrode, the second surface electrode is a source electrode, the back electrode is a drain electrode, the semiconductor element is configured as a transistor, and the first surface The electrode is further away from the first sub lead and the second sub lead than the second surface electrode.

  Preferably, the first surface electrode overlaps the main full thickness portion in the thickness direction view, and the second surface electrode overlaps the main eaves portion in the thickness direction view.

  Preferably, the first surface electrode overlaps both the main full thickness part and the main eaves part in the thickness direction view.

  Preferably, the first bump of the first wire and the second bonding portion of the first wire overlap both the main full thickness portion and the main eaves portion in the thickness direction view.

  Preferably, the main eaves portion has a main front portion protruding from the main full thickness portion toward the first sub lead and the second sub lead.

  Preferably, the main eaves portion has a main side portion protruding in a direction perpendicular to a direction in which the main front portion protrudes.

  Preferably, the main lead has a main side connecting portion protruding from the main side portion and having one end surface exposed from the resin package.

  Preferably, the main eaves part has a main rear part protruding on the opposite side to the main front part.

  Preferably, the main lead has a main rear connecting portion protruding from the main rear portion and having one end surface exposed from the resin package.

  Preferably, all of the main full thickness part is surrounded by the main eaves part.

  Preferably, a main surface plating layer is formed on the die pad portion.

  Preferably, the main surface plating layer overlaps all of the main eaves portions.

  Preferably, the first sub lead has a first sub full thickness portion extending from the first wire bonding portion to the first sub back terminal portion, and from the first wire bonding portion side portion of the first sub full thickness portion. And a first auxiliary eaves part protruding in a direction perpendicular to the thickness direction.

  Preferably, the first sub eaves portion has a first sub front portion protruding from the first sub full thickness portion toward the main lead.

  Preferably, the first sub eaves portion has a first sub side portion projecting in a direction perpendicular to a direction in which the first sub front portion projects.

  Preferably, the first sub-lead has a first sub-side connecting portion protruding from the first sub-side portion and having one end surface exposed from the resin package.

  Preferably, the first sub eaves portion has a first sub rear portion projecting on the opposite side to the first sub front portion.

  Preferably, the first sub-lead has a first sub-rear connecting portion protruding from the first sub-rear portion and having one end surface exposed from the resin package.

  Preferably, all of the first sub full thickness part is surrounded by the first sub eaves part.

  Preferably, a first subsurface plating layer is formed on the first wire bonding portion.

  Preferably, the first sub surface plating layer overlaps all of the first sub eaves portions.

  Preferably, the second sub lead includes a second sub full thickness portion extending from the second wire bonding portion to the second sub back terminal portion, and from the second wire bonding portion side portion of the second sub full thickness portion. And a second auxiliary eaves part protruding in a direction perpendicular to the thickness direction.

  Preferably, the second sub eaves portion has a second sub front portion protruding from the second sub full thickness portion toward the main lead.

  Preferably, the second sub eaves portion has a second sub side portion projecting in a direction perpendicular to a direction in which the second sub front portion projects.

  Preferably, the second sub-lead has a second sub-side connecting portion protruding from the second sub-side portion and having one end surface exposed from the resin package.

  Preferably, the second sub eaves portion has a second sub rear portion protruding to the opposite side to the second sub front portion.

  Preferably, the second sub lead has a second sub rear connecting portion protruding from the second sub rear portion and having one end surface exposed from the resin package.

  Preferably, all of the second sub full thickness portion is surrounded by the second sub eaves portion.

  Preferably, a second subsurface plating layer is formed on the second wire bonding portion.

  Preferably, the second sub surface plating layer overlaps all of the second sub eaves.

  Preferably, the semiconductor element includes a semiconductor layer stacked on each other, a eutectic layer of a semiconductor and a metal, and a single metal layer constituting the back electrode, and the single metal layer is directly bonded to the die pad portion. Has been.

  Preferably, the eutectic layer is made of a eutectic of Si and Au.

  Preferably, the single metal layer is thinner than the eutectic layer.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. FIG. 2 is a partial enlarged cross-sectional view of the semiconductor device shown in FIG. 1. It is sectional drawing which follows the VII-VII line of FIG. It is sectional drawing which follows the VIII-VIII line of FIG. It is sectional drawing which follows the IX-IX line of FIG. It is an enlarged image which shows the 2nd bonding part of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view showing a step in the method for manufacturing the semiconductor device shown in FIG. 1. It is a perspective view of the semiconductor device concerning 2nd Embodiment of this invention. FIG. 13 is a plan view of the semiconductor device shown in FIG. 12. FIG. 2 is an enlarged plan view of a main part showing a semiconductor element of the semiconductor device of FIG. 1. It is a top view of the modification of the semiconductor device of this invention. It is a perspective view which shows an example of the semiconductor device based on 3rd Embodiment of this invention. FIG. 17 is a perspective view showing the semiconductor device of FIG. 16. FIG. 17 is a plan view showing the semiconductor device of FIG. 16. It is sectional drawing which follows the XIX-XIX line | wire of FIG. It is sectional drawing which follows the XX-XX line of FIG. FIG. 17 is an enlarged cross-sectional view of a main part showing the semiconductor device of FIG. 16. It is sectional drawing which follows the XXII-XXII line | wire of FIG. It is sectional drawing which follows the XXIII-XXIII line | wire of FIG. It is sectional drawing which follows the XXIV-XXIV line | wire of FIG. FIG. 17 is an essential part enlarged plan view showing a semiconductor element of the semiconductor device of FIG. 16; FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is a cross-sectional view showing an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is an enlarged image showing a second bonding portion formed in an example of a manufacturing process of the semiconductor device of FIG. 16. FIG. 17 is a plan view of relevant parts showing a cutting process in an example of a manufacturing process of the semiconductor device of FIG. 16; 17 is an X-ray image showing the semiconductor device of FIG. It is a top view which shows an example of the semiconductor device based on 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

  1st Embodiment of this invention is described using FIGS.

  FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view of the semiconductor device shown in FIG. 3 is a bottom view of the semiconductor device shown in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view taken along line VV in FIG. 6 is a partial enlarged cross-sectional view of the semiconductor device shown in FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG.

  The semiconductor device 101 of this embodiment includes a semiconductor element 200, a main lead 300, a first sub lead 400, a second sub lead 500, a first wire 600, a second wire 700, and a resin package 800. 1 and 2, the resin package 800 is indicated by a two-dot chain line. The semiconductor device 101 is configured as a relatively small semiconductor device capable of so-called surface mounting. As an example of the size of the semiconductor device 101, the x direction dimension is about 0.4 to 0.8 mm, the y direction dimension is about 0.2 to 0.6 mm, and the thickness direction z dimension is 0.3 to 0. It is about 4 mm.

  In the present embodiment, the semiconductor element 200 is configured as a so-called transistor. The semiconductor element 200 has a front surface 201 and a back surface 202, and a first surface electrode 211, a second surface electrode 212, and a back electrode 220 are formed. The front surface 201 and the back surface 202 face in opposite directions in the z direction. As an example of the size of the semiconductor element 200, the dimension in the x direction is about 300 μm and the dimension in the y direction is about 300 μm.

  As shown in FIG. 14, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are configured by a part of each electrode layer 213 made of, for example, an Au plating layer. In the present embodiment, the first surface electrode 211 is a gate electrode, and the second surface electrode 212 is a source electrode. In the present embodiment, in FIG. 14, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Further, the first surface electrode 211 is located on the lower side in the y direction diagram, and the second surface electrode 212 is located on the upper side in the y direction diagram. The back electrode 220 is formed on the back surface 202. In the present embodiment, the back electrode 220 is a drain electrode.

  The removal region 214 is formed by removing a part of the electrode layer 231. The removal region 214 has a shape surrounding the first surface electrode 211. More specifically, the removal region 214 includes a portion that extends in parallel with each other along the four sides of the semiconductor element 200 and a portion that is located across a relatively large area so as to surround the first surface electrode 211. Yes. The first surface electrode 211 and the second surface electrode 212 are insulated by such an annular removal region 214.

  The peripheral area of the second surface electrode 212 is an active area 216. In the active region 216, a MOSFET 217 is formed at a site inward in the z direction from the surface 201. The MOSFET 217 includes a plurality of unit cells 218 arranged in a matrix. The arrangement form of the plurality of unit cells 218 is not limited to the matrix form, and may be, for example, a stripe form or a staggered form.

  In the present embodiment, one second surface electrode 212 is provided as a source electrode. However, the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

  The semiconductor element 200 is disposed on the main lead 300. As shown in FIGS. 2 and 3, in the present embodiment, the semiconductor element 200 has a portion that does not overlap the main lead 300 when viewed in the thickness direction z. That is, the semiconductor element 200 has a portion that protrudes outside the main lead 300 in the thickness direction z view. As will be described in detail later, the main lead 300 is exposed from the resin package 800. The main lead 300 is derived from the lead frame. The main lead 300 is formed by patterning such as etching on a metal plate made of Cu, for example.

  As shown in FIG. 4, FIG. 5, etc., the main lead 300 has a main lead main surface 310 and a main lead back surface 320 that face opposite sides. Both the main lead main surface 310 and the main lead back surface 320 are flat.

  The main lead main surface 310 faces upward in the thickness direction z. The semiconductor element 200 is disposed on the main lead main surface 310. In the present embodiment, the main surface plating layer 311 is formed on the main lead main surface 310 of the main lead 300. The main surface plating layer 311 is interposed between the semiconductor element 200 and the main lead 300. Main surface plating layer 311 is formed over the entire area of main lead main surface 310. The main surface plating layer 311 is made of Ag having a thickness of about 2 μm, for example.

  In FIG. 3, the main lead back surface 320 is indicated by hatching. The main lead back surface 320 faces downward in the thickness direction z opposite to the main lead main surface 310, and is used for surface mounting the semiconductor device 101. The main lead back surface 320 has a rectangular shape. The main lead back surface 320 entirely overlaps the main lead main surface 310 in the thickness direction z view and is included in the main lead main surface 310.

  The main lead 300 includes a main full thickness portion 330 and a main eaves portion 340.

  The main full thickness portion 330 is a portion extending from the main lead main surface 310 to the main lead back surface 320 in the thickness direction z. In the present embodiment, the main full thickness portion 330 is entirely overlapped with the semiconductor element 200 in the thickness direction z view. At least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main full thickness portion 330 in the thickness direction view z. In the present embodiment, both the first surface electrode 211 and the second surface electrode 212 overlap the main full thickness portion 330 in the thickness direction view z. That is, the first surface electrode 211 and the second surface electrode 212 are disposed near the center of the semiconductor element 200 in the thickness direction view z. Unlike the present embodiment, only the first surface electrode 211 overlaps the main full thickness portion 330 in the thickness direction view z, and the second surface electrode 212 overlaps the main full thickness portion 330 in the thickness direction view z. It is not necessary. Similarly, unlike the present embodiment, only the second surface electrode 212 overlaps the main full thickness portion 330 in the thickness direction view z, and the first surface electrode 211 overlaps the main full thickness portion 330 in the thickness direction view z. It is not necessary to overlap. In the present embodiment, the thickness of the main full thickness portion 330 is about 0.9 to 1.1 mm. The main full thickness portion 330 constitutes the main lead back surface 320.

  The main eaves part 340 protrudes from the main full thickness part 330 in a direction perpendicular to the thickness direction z. In the present embodiment, the main eaves part 340 protrudes from the main full thickness part 330 in the x and y directions perpendicular to the thickness direction z. In the present embodiment, the main eaves portion 340 further protrudes from the main lead main surface 310 side portion of the main full thickness portion 330 in the x and y directions perpendicular to the thickness direction z. The thickness of the main eaves part 340 is, for example, half of the main full thickness part 330 and is about 0.05 mm. The main eaves part 340 and the main full thickness part 330 constitute the main lead main surface 310 described above. On the other hand, the main eaves part 340 does not constitute the main lead back surface 320. The main eaves part 340 surrounds the main full thickness part 330 when viewed in the thickness direction z. Furthermore, in the present embodiment, the main eaves part 340 overlaps the semiconductor element 200 in the thickness direction z as a whole.

  In the present embodiment, the main eaves part 340 has a main front part 341, a main side part 342, and a main rear part 343.

  The main front portion 341 protrudes from the main full thickness portion 330 toward the first sub lead 400. Further, in the present embodiment, the main front portion 341 protrudes from the main full thickness portion 330 toward the second sub lead 500.

  The main side portion 342 protrudes from the main full thickness portion 330 in a direction perpendicular to the direction in which the main front portion 341 protrudes. Specifically, the main side portion 342 protrudes from the main full thickness portion 330 in the y direction. In the present embodiment, two main side portions 342 are formed. In the present embodiment, the main lead 300 has two main side connecting portions 351. The main side connection part 351 extends from the main side part 342 of the main eaves part 340 and has the same thickness as the main side part 342. An end surface in the y direction of the main side connecting portion 351 is exposed from the resin package 800.

  The main rear portion 343 protrudes from the main full thickness portion 330 in a direction opposite to the direction in which the main front portion 341 protrudes. In the present embodiment, the main lead 300 has a main rear connection part 352. The main rear connection part 352 extends from the main rear part 343 of the main eaves part 340 and has the same thickness as the main rear part 343. An end surface in the x direction of the main rear connecting portion 352 is exposed from the resin package 800.

  As shown in FIG. 6, in the semiconductor element 200, the back electrode 220 is bonded to the main lead main surface 310 (main surface plating layer 311). Specifically, back electrode 220 as a single metal layer is directly bonded to main lead main surface 310 (main surface plating layer 311) by, for example, a thermocompression bonding technique. In this thermocompression bonding, no vibration is applied, and only heat and pressure are applied.

  The first sub lead 400 is separated from the main lead 300. More specifically, the first sub lead 400 is arranged to be separated from the main lead 300 in the x direction. Further, the first sub lead 400 is separated from the second sub lead 500. The first sub lead 400 is exposed from the resin package 800 to the outside of the resin package 800 as viewed in the thickness direction z. In the present embodiment, the first sub lead 400 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. The first sub lead 400 is derived from the lead frame. The first sub lead 400 is formed by patterning such as etching on a metal plate made of Cu, for example.

  The first sub lead 400 has a first sub lead main surface 410, a first sub lead back surface 420, a first sub lead end surface 481, and a first sub lead side surface 482. The first sub lead main surface 410, the first sub lead back surface 420, the first sub lead end surface 481, and the first sub lead side surface 482 are all flat.

  The first sub lead main surface 410 faces upward in the thickness direction z. The first wire 600 is bonded to the first sub lead main surface 410. In the present embodiment, a first sub surface plating layer 411 is formed on the first sub lead main surface 410. The first sub surface plating layer 411 is interposed between the first sub lead main surface 410 and the first wire 600. The first sub surface plating layer 411 is formed over the entire area of the first sub lead main surface 410. The first subsurface plating layer 411 is made of Ag having a thickness of about 2 μm, for example. In FIG. 1, for convenience of understanding, the first subsurface plating layer 411 is halftone.

  The first sub-lead back surface 420 faces away from the direction in which the first sub-lead main surface 410 faces. Specifically, the first sub-lead back surface 420 faces downward in the thickness direction z on the opposite side of the first sub-lead main surface 410. The first sub-lead back surface 420 is exposed from the resin package 800. The first sub-lead back surface 420 is used for surface mounting the semiconductor device 101. In FIG. 3, the first sub-lead back surface 420 is indicated by hatching.

  The first sub lead end surface 481 faces the side opposite to the side where the main lead 300 is located. Specifically, the first sub lead end surface 481 faces the right side of FIG. The first sub lead end surface 481 is connected to the first sub lead back surface 420. The first sub lead end surface 481 is exposed from the resin package 800.

  The first sub lead side surface 482 faces the direction perpendicular to both the direction in which the first sub lead end surface 481 faces and the thickness direction z of the semiconductor element 200. Specifically, the first secondary lead side surface 482 faces the lower side of FIG. The first secondary lead side surface 482 is connected to the first secondary lead back surface 420. The first sub lead side 482 is exposed from the resin package 800.

  The first sub lead 400 includes a first sub full thickness portion 430 and a first sub eaves portion 440.

  The first sub full thickness portion 430 is a portion extending from the first sub lead main surface 410 to the first sub lead back surface 420 in the thickness direction z. In the present embodiment, the thickness of the first sub full thickness portion 430 is about 0.1 mm. The first sub full thickness portion 430 constitutes a first sub lead main surface 410 and a first sub lead back surface 420. In the present embodiment, the first sub full thickness portion 430 is exposed from the resin package 800. Therefore, the first sub full thickness portion 430 constitutes a first sub lead end surface 481 and a first sub lead side surface 482.

  The first secondary eaves part 440 protrudes from the first secondary full thickness part 430 in a direction perpendicular to the thickness direction z. In the present embodiment, the first sub eaves portion 440 protrudes in the x direction and the y direction. The thickness of the first auxiliary eaves part 440 is, for example, half of the first auxiliary full thickness part 430 and is about 0.05 mm. The first sub eaves portion 440 constitutes a first sub lead main surface 410. On the other hand, the first sub eaves portion 440 does not constitute the first sub lead back surface 420.

  In the present embodiment, the first sub eaves portion 440 has a first sub front portion 441 and a first sub inward portion 442.

  The first sub front part 441 protrudes from the first sub full thickness part 430 toward the main lead 300. The first secondary inner portion 442 protrudes from the first secondary full thickness portion 430 toward the second secondary lead 500.

  The second sub lead 500 is separated from the main lead 300. More specifically, the second sub lead 500 is arranged to be separated from the main lead 300 in the x direction. Further, the second sub lead 500 is separated from the first sub lead 400. The second sub lead 500 is exposed from the resin package 800 to the outside of the resin package 800 as viewed in the thickness direction z. In the present embodiment, the second sub lead 500 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. The second sub lead 500 is derived from the lead frame. The second sub lead 500 is formed by patterning such as etching on a metal plate made of Cu, for example.

  The second sub lead 500 has a second sub lead main surface 510, a second sub lead back surface 520, a second sub lead end surface 581, and a second sub lead side surface 582. The second sub lead main surface 510, the second sub lead back surface 520, the second sub lead end surface 581, and the second sub lead side surface 582 are all flat.

  The second secondary lead main surface 510 faces upward in the thickness direction z. A second wire 700 is bonded to the second sub lead main surface 510. In the present embodiment, a second secondary surface plating layer 511 is formed on the second secondary lead main surface 510. The second sub surface plating layer 511 is interposed between the second sub lead main surface 510 and the second wire 700. The second sub surface plating layer 511 is formed over the entire area of the second sub lead main surface 510. The second sub surface plating layer 511 is made of Ag having a thickness of about 2 μm, for example. In FIG. 1, for convenience of understanding, the second subsurface plating layer 511 is halftone.

  The second sub lead back surface 520 faces the side opposite to the direction in which the second sub lead main surface 510 faces. Specifically, the second sub-lead back surface 520 faces downward in the thickness direction z on the opposite side of the second sub-lead main surface 510. The second sub lead back surface 520 is exposed from the resin package 800. The second sub lead back surface 520 is used for surface mounting the semiconductor device 101. In FIG. 3, the second sub-lead back surface 520 is indicated by hatching.

  The second sub lead end surface 581 faces the side opposite to the side where the main lead 300 is located. Specifically, the second sub lead end surface 581 faces the right side of FIG. The second secondary lead end surface 581 is connected to the second secondary lead back surface 520. The second sub lead end face 581 is exposed from the resin package 800.

  The second sub lead side surface 582 faces a direction that is perpendicular to both the direction in which the second sub lead end surface 581 faces and the thickness direction z of the semiconductor element 200. Specifically, the second secondary lead side surface 582 faces the upper side in FIG. The second secondary lead side surface 582 is connected to the second secondary lead back surface 520. The second secondary lead side surface 582 is exposed from the resin package 800.

  The second sub lead 500 includes a second sub full thickness portion 530 and a second sub eaves portion 540.

  The second sub full thickness portion 530 is a portion extending from the second sub lead main surface 510 to the second sub lead back surface 520 in the thickness direction z. In the present embodiment, the thickness of the second sub full thickness part 530 is about 0.1 mm. The second sub full thickness portion 530 constitutes a second sub lead main surface 510 and a second sub lead back surface 520. In the present embodiment, the second sub full thickness portion 530 is exposed from the resin package 800. Therefore, the second sub full thickness portion 530 constitutes a second sub lead end surface 581 and a second sub lead side surface 582.

  The second secondary eaves part 540 protrudes from the second secondary full thickness part 530 in a direction perpendicular to the thickness direction z. In the present embodiment, the second auxiliary eaves part 540 protrudes in the x direction and the y direction. The thickness of the second auxiliary eaves part 540 is, for example, half of the second auxiliary full thickness part 530 and is about 0.05 mm. The second sub eaves portion 540 constitutes a second sub lead main surface 510. On the other hand, the second secondary eaves part 540 does not constitute the second secondary lead back surface 520.

  In the present embodiment, the second sub eaves part 540 has a second sub front part 541 and a second sub inner part 542.

  The second auxiliary front part 541 protrudes from the second auxiliary full thickness part 530 toward the main lead 300. The second secondary inner portion 542 protrudes from the second secondary full thickness portion 530 toward the first secondary lead 400.

  The first wire 600 is directly connected to the semiconductor element 200 and makes the semiconductor element 200 and the first sub lead 400 conductive. Specifically, the first wire 600 is bonded to the first surface electrode 211 of the semiconductor element 200 and the first subsurface plating layer 411.

  The first wire 600 has a first bonding part 610 and a second bonding part 620. The first wire 600 is made of Au having a diameter of about 20 μm.

  The first bonding portion 610 is bonded to the first subsurface plating layer 411 and has a crown-shaped lump portion.

  The second bonding part 620 is bonded to the first surface electrode 211 of the semiconductor element 200 via the first bump 630. The second bonding portion 620 has a tapered shape in which the thickness direction z thickness decreases toward the tip.

  The first bump 630 is a part similar to the lump part of the first bonding part 610. In the present embodiment, the first bump 630 has a slightly smaller volume than the above-mentioned lump portion of the first bonding portion 610. The first bump 630 overlaps the main full thickness portion 330 in the thickness direction z view. FIG. 10 shows an enlarged image of the second bonding portion 620 of the semiconductor device shown in FIG.

  The second wire 700 is directly connected to the semiconductor element 200 and electrically connects the semiconductor element 200 and the second sub lead 500. Specifically, the second wire 700 is bonded to the second surface electrode 212 of the semiconductor element 200 and the second subsurface plating layer 511.

  The second wire 700 has a first bonding part 710 and a second bonding part 720. The second wire 700 is made of Au having a diameter of about 20 μm.

  The first bonding portion 710 is bonded to the second subsurface plating layer 511 and has a crown-shaped lump portion.

  The second bonding part 720 is bonded to the second surface electrode 212 of the semiconductor element 200 via the second bump 730. The second bonding portion 720 has a tapered shape in which the thickness direction z thickness decreases toward the tip.

  The second bump 730 is a part similar to the lump part of the first bonding part 710. The second bump 730 overlaps the main full thickness portion 330 in the thickness direction z view. In the present embodiment, the volume of the second bump 730 is slightly smaller than the above-described lump portion of the first bonding portion 710.

  The resin package 800 covers the semiconductor element 200, the main lead 300, the first sub lead 400, the second sub lead 500, the first wire 600, and the second wire 700. The resin package 800 is made of, for example, a black epoxy resin. Also, the resin package 800 has the main lead back surface 320 of the main lead 300, the first sub lead back surface 420 of the first sub lead 400, and the second sub lead back surface 520 of the second sub lead 500 all in the thickness direction z downward. It is exposed to the side.

  The resin package 800 has a resin main surface 801, a resin back surface 802, a first resin side surface 803, a second resin side surface 804, a first resin end surface 805, and a second resin end surface 806.

  The resin main surface 801 faces the same direction as the main lead main surface 310 faces. In the present embodiment, the resin main surface 801 is flat.

  The resin back surface 802 faces the same direction as the main lead back surface 320 faces. That is, the resin back surface 802 faces in the direction opposite to the direction in which the resin main surface 801 faces. The resin back surface 802 is flat. From the resin back surface 802, the main lead 300, the first sub lead 400, and the second sub lead 500 are exposed. In this embodiment, the resin back surface 802 is flush with all of the main lead back surface 320, the first sub lead back surface 420, and the second sub lead back surface 520.

  The first resin side surface 803 faces the same direction as the direction of the first sub lead side surface 482 in the first sub lead 400. The first resin side surface 803 is flat. The first secondary lead 400 is exposed from the first resin side surface 803. In the present embodiment, the first sub full thickness portion 430 is exposed from the second resin side surface 804. The first resin side surface 803 is flush with the first sub lead side surface 482. In the present embodiment, the main resin 300 is exposed on the first resin side surface 803. Specifically, the first side surface 803 exposes the main side connecting portion 351 in the main lead 300. The first resin side surface 803 is flush with the end surface of the main side connecting portion 351.

  The second resin side surface 804 faces the same direction as the direction of the second sub lead side surface 582 in the second sub lead 500. The second resin side surface 804 is flat. The second secondary lead 500 is exposed from the second resin side surface 804. The second resin side surface 804 is flush with the second sub lead side surface 582. In the present embodiment, the second sub full thickness portion 530 is exposed from the second resin side surface 804. In the present embodiment, the main lead 300 is exposed on the second resin side surface 804. Specifically, the main side connecting portion 351 of the main lead 300 is exposed on the second resin side surface 804. The second resin side surface 804 is flush with the end surface of the main side connecting portion 351.

  The first resin end surface 805 faces the same direction as the direction of the first sub lead end surface 481 in the first sub lead 400. The first resin end surface 805 is flat. The first secondary lead 400 is exposed from the first resin end surface 805. The first resin end surface 805 is flush with the first sub lead end surface 481. In the present embodiment, the first sub full thickness portion 430 is exposed from the first resin end surface 805. Similarly, the first resin end surface 805 faces the same direction as the direction of the second sub lead end surface 581 in the second sub lead 500. The second sub lead 500 is exposed from the first resin end surface 805. The first resin end surface 805 is flush with the second sub lead end surface 581. In the present embodiment, the second sub full thickness portion 530 is exposed from the first resin end surface 805.

  The second resin end surface 806 faces in a direction opposite to the direction in which the first resin end surface 805 faces. The second resin end surface 806 is flat. The main lead 300 is exposed from the second resin end surface 806. In the present embodiment, the main rear connection portion 352 is exposed from the second resin end surface 806. The second resin end surface 806 is flush with the end surface of the main rear connecting portion 352.

  Note that the surface of the resin and the surface of the lead (the main lead 300, the first sub lead 400, or the second sub lead 500) are flush with the lead frame when the semiconductor device 101 is manufactured. This is because the resin member that becomes the resin package is diced together. FIG. 11 shows a cross-sectional view of one step in the method of manufacturing the semiconductor device shown in FIG. The figure shows the vicinity of the first sub lead 400. In the present embodiment, the lead and the resin member are diced along the line Ct1 in FIG.

  Next, the effect of this embodiment is demonstrated.

  In the present embodiment, the semiconductor element 200 has a portion that does not overlap the main lead 300 in the thickness direction z view of the semiconductor element 200. According to such a configuration, the size of the main lead 300 can be made relatively smaller than the size of the semiconductor element 200 in the thickness direction z view. Thereby, the size of the resin package 800 in the thickness direction z is determined by the semiconductor element 200 instead of the main lead 300. As a result, the size of the semiconductor device 101 in the thickness direction z can be reduced.

  In the present embodiment, the main lead 300 includes a main full thickness portion 330 and a main eaves portion 340. According to such a configuration, the junction area between the semiconductor element 200 and the main lead 300 can be increased. As a result, the semiconductor element 200 can be reliably bonded to the main lead 300.

The second bonding portion 620 of the first wire 600 is bonded to the first surface electrode 211 via the first bump 630, and the second bonding portion 720 of the second wire 700 is bonded to the second surface electrode 212 via the second bump 730. By adopting a configuration in which the first wire 600 and the second wire 700 are joined to each other, the height z in the thickness direction can be reduced. This contributes to lowering the height z of the semiconductor device 101 in the thickness direction. Therefore, according to the present embodiment, the semiconductor device 101 can be downsized.

  Since the first surface electrode 211 as the gate electrode is further away from the first sub lead 400 and the second sub lead 500 than the second surface electrode 212 as the source electrode, the length of the first wire 600 is increased. Can be longer than the second wire 700. The first wire 600 having a longer length is particularly easy to increase the bonding strength in the second bonding portion 620. In general, the first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of the semiconductor layer 231 via an insulating layer (not shown). Such a first surface electrode 211 is relatively difficult to improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as a source electrode is often connected to a metal portion filled in a plurality of trenches (pits) formed in the semiconductor layer 231. With such a configuration, the second surface electrode 212 is relatively easy to improve the bonding strength of wire bonding. Therefore, bonding the first wire 600 that easily increases the bonding strength to the first surface electrode 211 as the gate electrode, which is relatively concerned about the bonding strength, is advantageous in avoiding problems such as wire peeling. .

  Since the main eaves part 340 includes the main front part 341, the bonding strength between the main lead 300 and the resin package 800 can be increased. In addition, the main lead back surface 320, the first sub lead back surface 420, and the second sub lead back surface 520 are prevented from being unduly approached while bringing the semiconductor element 200 close to the first sub lead 400 and the second sub lead 500. can do.

  Since the main eaves part 340 includes the main side part 342 and the main rear part 343, the bonding strength between the main lead 300 and the resin package 800 can be increased. The configuration in which all of the main full thickness portion 330 is surrounded by the main eaves portion 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800.

  The main side connecting portion 351 and the main rear connecting portion 352 appropriately hold the main lead 300 in the manufacturing process of the semiconductor device 101. Although the end surface in the y direction of the main side connection portion 351 and the end surface in the x direction of the main rear connection portion 352 are exposed from the resin package 800, they are separated from the main lead back surface 320. For this reason, there is little possibility that the solder for surface mounting the semiconductor device 101 will accidentally spread on the y-direction end surface of the main side connection portion 351 and the x-direction end surface of the main rear connection portion 352.

  By forming the main surface plating layer 311 on the main lead main surface 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the main lead main surface 310 can be increased. When the main surface plating layer 311 overlaps all of the main eaves portions 340, the area that can be used as the main lead main surface 310 can be increased.

  Since the first sub lead 400 includes the first sub eaves portion 440, the bonding strength between the first sub lead 400 and the resin package 800 can be increased. Since the first sub eaves portion 440 includes the first sub front portion 441, the distance between the first sub lead back surface 420 and the main lead back surface 320 is unduly approached while increasing the bonding strength with the resin package 800. Can be avoided. This is because the first sub lead back surface 420 and the main lead back surface 320 are attached to the first sub lead back surface 420 and the main lead back surface 320 even when the entire semiconductor device 101 is downsized. This means that it is possible to prevent a problem of electrical conduction via the solder that is used.

  Since the first sub eaves portion 440 includes the first sub inward portion 442, the bonding strength between the first sub lead 400 and the resin package 800 can be increased. Since the first sub eaves portion 440 includes the first sub inward portion 442, the distance between the first sub lead back surface 420 and the second sub lead back surface 520 is inappropriate while increasing the bonding strength with the resin package 800. Can be avoided. This is because the first sub lead back surface 420 and the second sub lead back surface 520 adhere to the first sub lead back surface 420 and the second sub lead even when the entire semiconductor device 101 is downsized. This means that it is possible to prevent a problem of electrical conduction through the solder attached to the back surface 520.

  In the present embodiment, the first sub lead 400 has a first sub lead end surface 481 connected to the first sub lead back surface 420. The first sub lead end surface 481 is exposed from the resin package 800. Therefore, the first sub-lead back surface 420 can be made wider. As a result, the tape 901 (see FIG. 11) used in the resin molding for forming the resin package 800 and the first sub-lead back surface 420 can be bonded more firmly. Therefore, the resin material can be prevented from entering between the tape 901 and the first sub-lead back surface 420 during resin molding. Thereby, it is possible to prevent the occurrence of resin burrs on the first sub-lead back surface 420. Similarly, the same effect can be obtained when the first sub-lead side surface 482 is exposed from the resin package 800. In addition, the second sub lead end surface 581 of the second sub lead 500 is exposed from the resin package 800 and the second sub lead side surface 582 is also exposed. And the same effect as described above.

  By forming the first sub surface plating layer 411 on the first sub lead main surface 410, the bonding strength between the first wire 600 and the first sub lead main surface 410 can be increased.

  Since the second sub lead 500 includes the second sub eaves portion 540, the bonding strength between the second sub lead 500 and the resin package 800 can be increased. Since the second sub eaves part 540 includes the second sub front part 541, the bonding strength with the resin package 800 is increased, and the distance between the second sub lead back surface 520 and the main lead back surface 320 is unduly close. Can be avoided.

  Since the second sub eaves portion 540 includes the second sub inward portion 542, the bonding strength between the second sub lead 500 and the resin package 800 can be increased. Since the second sub eaves portion 540 has the second sub inner portion 542, the bonding strength with the resin package 800 is increased, and the distance between the second sub lead back surface 520 and the first sub lead back surface 420 is inappropriate. Can be avoided. This is because the first sub lead back surface 420 and the second sub lead back surface 520 adhere to the first sub lead back surface 420 and the second sub lead even when the entire semiconductor device 101 is downsized. This means that it is possible to prevent a problem of electrical conduction through the solder attached to the back surface 520.

  By forming the second sub surface plating layer 511 on the second sub lead main surface 510, the bonding strength between the second wire 700 and the second sub lead main surface 510 can be increased.

  In joining the semiconductor element 200 and the main lead main surface 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly joined to the main lead main surface 310, and vibration is applied at the time of joining. Absent. With such a configuration, it is not necessary to set a margin area in consideration of vibration in an area located around the semiconductor element 200 in the main lead 300. This is advantageous for miniaturization of the semiconductor device 101.

  A second embodiment of the present invention will be described with reference to FIGS.

  FIG. 12 is a perspective view of a semiconductor device according to the second embodiment of the present invention. FIG. 13 is a plan view of the semiconductor device shown in FIG.

  In the semiconductor device 102 shown in these drawings, the shapes of the first sub lead 400 and the second sub lead 500 are different from those of the semiconductor device 101. Since the configurations other than those described below are the same as those of the semiconductor device 101, the same reference numerals as those in the first embodiment are used, and the description thereof is omitted.

  In the present embodiment, the first sub lead 400 includes a first sub extended portion 460 in addition to the first sub full thickness portion 430 and the first sub eaves portion 440.

  In the present embodiment, the first sub full thickness portion 430 is not exposed from the resin package 800.

  The first sub extended portion 460 extends from the first sub full thickness portion 430 in a direction perpendicular to the thickness direction z. The thickness of the 1st sub extension part 460 is a half of the 1st sub full thickness part 430, for example, and is about 0.05 mm. The first secondary extension 460 constitutes the first secondary lead back surface 420. On the other hand, the first sub extended portion 460 does not constitute the first sub lead main surface 410. The first sub extension 460 is exposed from the resin package 800 toward the outside of the resin package 800 in the thickness direction z view. Specifically, the first sub extension 460 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. Therefore, the first sub extended portion 460 constitutes a first sub lead end surface 481 and a first sub lead side surface 482.

  In the present embodiment, the first secondary extension 460 includes a first secondary rear portion 461 and a first secondary side portion 462.

  The first secondary rear portion 461 protrudes from the first secondary full thickness portion 430 toward the side opposite to the side where the main lead 300 is located. The first secondary rear portion 461 constitutes a first secondary lead end surface 481. The first secondary side portion 462 protrudes from the first secondary full thickness portion 430 toward the side opposite to the side where the second secondary lead 500 is located. The first secondary side portion 462 constitutes a first secondary lead side surface 482.

  In the present embodiment, the second sub full thickness portion 530 is not exposed from the resin package 800.

  The second sub extended portion 560 extends from the second sub full thickness portion 530 in a direction perpendicular to the thickness direction z. The thickness of the second sub extended portion 560 is, for example, half of the second sub full thickness portion 530 and is about 0.05 mm. The second secondary extension 560 constitutes the second secondary lead back surface 520. On the other hand, the second sub extended portion 560 does not constitute the second sub lead main surface 510. The second sub extension 560 is exposed from the resin package 800 toward the outside of the resin package 800 as viewed in the thickness direction z. Specifically, the second secondary extension 560 is exposed from the resin package 800 in the direction x and the direction y from the resin package 800. Therefore, the second sub extended portion 560 constitutes a second sub lead end surface 581 and a second sub lead side surface 582.

  In the present embodiment, the second secondary extension 560 includes a second secondary rear portion 561 and a second secondary side portion 562.

  The second secondary rear portion 561 protrudes from the second secondary full thickness portion 530 toward the side opposite to the side where the main lead 300 is located. The second secondary rear portion 561 constitutes a second secondary lead end surface 581. The second secondary side portion 562 protrudes from the second secondary full thickness portion 530 toward the side opposite to the side where the first secondary lead 400 is located. The second secondary side portion 562 constitutes a second secondary lead side surface 582.

  When manufacturing the semiconductor device 102, the lead and the resin member are diced along the line Ct2 of FIG. 11 used in the description of the semiconductor device 101.

  Next, the effect of this embodiment is demonstrated.

  According to the present embodiment, in addition to the same functions and effects as described for the semiconductor device 101, the following functions and effects are achieved.

  According to the present embodiment, when cutting the first sub lead 400 in the lead frame, it is not necessary to dice the first sub full thickness portion 430, and a relatively thin portion may be diced. The generation of burrs is proportional to the thickness of the lead frame to be cut. Therefore, it is possible to suppress the occurrence of metal burrs that can be formed by cutting a portion of the lead frame that is to become the first sub lead 400. Similarly, the generation of metal burrs that can be formed by cutting a portion of the lead frame that is to become the second sub lead 500 can be suppressed.

  Actually, when the main lead 300, the first sub lead 400, and the second sub lead 500 are patterned by etching, the boundary between the main full thickness portion 330 and the main eaves portion 340 is as shown in FIGS. The clear corners shown in Fig. 5 are not formed and can be curved. Similarly, the boundary between the first sub full thickness part 430 and the first sub eaves part 440 in the first sub lead 400, the boundary between the first sub eaves part 440 and the first sub extension part 460, and the second sub lead 500. The boundary between the second sub full thickness part 530 and the second sub eaves part 540 and the boundary between the second sub eaves part 540 and the second sub extension part 560 can also be curved surfaces. Even if the design intended for the form shown in FIGS. 1 to 13 and the like is performed, if the semiconductor devices 101 and 102 have the above-described very small configuration, the above-described curved surface is unavoidable in the etching process. This is because it may occur.

  FIG. 15 shows a modification of the semiconductor device. As shown in the figure, the positions of the first surface electrode 211 as the gate electrode, the second surface electrode 212 as the source electrode, the second bonding portions 620 and 720, the first bump 630, and the second bump 730 are as follows. This is different from the semiconductor device shown in FIG. Descriptions other than these positions of the semiconductor device shown in FIG. 15 can be applied to those described with respect to the semiconductor device 101, and thus descriptions other than the positions are omitted. In FIG. 2, the first surface electrode 211 as a gate electrode is located on the left side in the semiconductor element 200, and the second surface electrode 212 as a source electrode is located on the right side in the semiconductor element 200. Further, the second bonding portion 620 and the first bump 630 are located on the left side of the second bonding portion 720 and the second bump 730. On the other hand, in FIG. 15, the first surface electrode 211 as a gate electrode is located on the right side in the semiconductor element 200, and the second surface electrode 212 as a source electrode is located on the left side in the semiconductor element 200. Further, the second bonding portion 620 and the first bump 630 are located on the right side of the second bonding portion 720 and the second bump 730. As described above, the positions of the first surface electrode 211 as a gate electrode and the second surface electrode 212 as a source electrode in a plan view can be freely changed.

  The present invention is not limited to the embodiment described above. The specific configuration of each part of the present invention can be changed in various ways. The semiconductor element is not limited to a transistor, and may be a diode, for example.

  16 to 24 show an example of a semiconductor device according to the third embodiment of the present invention.

  The semiconductor device 101 of this embodiment includes a semiconductor element 200, a main lead 300, a first sub lead 400, a second sub lead 500, a first wire 600, a second wire 700, and a resin package 800. The semiconductor device 101 is configured as a relatively small semiconductor device that can be so-called surface-mounted. For example, the semiconductor device 101 has an x-direction dimension of about 0.8 mm, a y-direction dimension of about 0.6 mm, and a z-direction. The direction dimension is about 0.36 mm. The z direction is the thickness direction of the semiconductor element, main lead, first sub lead, and second sub lead referred to in the present invention. FIG. 16 is a perspective view of the semiconductor device 101 as viewed from above in the z direction. FIG. 17 is a perspective view of the semiconductor device 101 as viewed from below in the z direction. FIG. 18 is a plan view of the semiconductor device 101. FIG. 19 is a cross-sectional view in the zx plane along the line XIX-XIX in FIG. 20 is a cross-sectional view in the zx plane along the line XX-XX in FIG. FIG. 21 is an enlarged cross-sectional view of a main part in a zx plane crossing the semiconductor element 200. 22 is a cross-sectional view in the yz plane along the line XXII-XXII in FIG. 23 is a cross-sectional view in the yz plane along the line XXIII-XXIII in FIG. FIG. 24 is a cross-sectional view in the yz plane along the line XXIV-XXIV in FIG.

  In the present embodiment, the semiconductor element 200 is configured as a so-called transistor. The semiconductor element 200 has a front surface 201 and a back surface 202, and a first surface electrode 211, a second surface electrode 212, and a back electrode 220 are formed. The front surface 201 and the back surface 202 face in opposite directions in the z direction. As an example of the size of the semiconductor element 200, the dimension in the x direction is about 300 μm and the dimension in the y direction is about 300 μm.

  As shown in FIG. 25, the first surface electrode 211 and the second surface electrode 212 are formed on the surface 201, and are constituted by a part of the electrode layer 213 made of, for example, an Au plating layer. In the present embodiment, the first surface electrode 211 is a gate electrode, and the second surface electrode 212 is a source electrode. In the present embodiment, in FIGS. 18 and 25, the first surface electrode 211 is located on the left side in the x direction, and the second surface electrode 212 is located on the right side in the x direction. Further, the first surface electrode 211 is located on the lower side in the y direction diagram, and the second surface electrode 212 is located on the upper side in the y direction diagram. The back electrode 220 is formed on the back surface 202. In the present embodiment, the back electrode 220 is a drain electrode.

  The removal region 214 is formed by removing a part of the electrode layer 231. The removal region 214 has a shape surrounding the first surface electrode 211. More specifically, the removal region 214 includes a portion that extends in parallel with each other along the four sides of the semiconductor element 200 and a portion that is located across a relatively large area so as to surround the first surface electrode 211. Yes. The first surface electrode 211 and the second surface electrode 212 are insulated by such an annular removal region 214.

  The peripheral area of the second surface electrode 212 is an active area 216. In the active region 216, a MOSFET 217 is formed at a site inward in the z direction from the surface 201. The MOSFET 217 includes a plurality of unit cells 218 arranged in a matrix. The arrangement form of the plurality of unit cells 218 is not limited to the matrix form, and may be, for example, a stripe form or a staggered form.

  In the present embodiment, one second surface electrode 212 is provided as a source electrode. However, the present invention is not limited to this, and a plurality of second surface electrodes 212 may be provided.

  FIG. 21 shows the vicinity of the back electrode 220 of the semiconductor element 200. The semiconductor element 200 of this embodiment has a semiconductor layer 231 and a eutectic layer 232. The semiconductor layer 231 is a layer in which each part functioning as a transistor is formed, and is made of, for example, Si. The eutectic layer 232 is made of a eutectic of a semiconductor and a metal constituting the semiconductor layer 231. In the present embodiment, the eutectic layer 232 is made of a eutectic of Si as a semiconductor and Au as a metal. The eutectic layer 232 is formed by alloying treatment by heating a layer made of Au on the semiconductor layer 231 and then heating them. A back electrode 220 is stacked below the eutectic layer 232 in the z direction. The back electrode 220 is an example in which an Au layer is formed on the eutectic layer 232 by vapor deposition, and is an example of a single metal layer referred to in the present invention. The eutectic layer 232 has a thickness of about 1200 nm, for example. The back electrode 220 as a single metal layer has a thickness of about 600 nm, for example, and is thinner than the eutectic layer 232. In the present embodiment, the surface of the eutectic layer 232 facing downward in the z direction is defined as the back surface 202 of the semiconductor element 200.

  The main lead 300 includes a die pad portion 310, a main back surface terminal portion 320, a main full thickness portion 330, and a main eaves portion 340. The main lead 300 is formed by patterning such as etching on a metal plate made of Cu, for example.

  The die pad portion 310 faces upward in the z direction and is a portion where the semiconductor element 200 is mounted. In the present embodiment, the die pad portion 310 has a rectangular shape with an x-direction dimension of about 0.4 mm and a y-direction dimension of about 0.5 mm. In the present embodiment, the main surface plating layer 311 is formed on the die pad portion 310. Main surface plating layer 311 is formed over the entire area of die pad portion 310. The main surface plating layer 311 is made of Ag having a thickness of about 2 μm, for example. In FIG. 16, halftone is given to the main surface plating layer 311 for convenience of understanding.

  The main back surface terminal portion 320 faces downward in the z direction opposite to the die pad portion 310 and is used for surface mounting the semiconductor device 101. The main back terminal portion 320 has a rectangular shape with an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.48 mm. The main back surface terminal portion 320 entirely overlaps the die pad portion 310 when viewed in the z direction, and is included in the die pad portion 310. In the present embodiment, a main back plating layer 321 is formed on the main lead 300. The main back plating layer 321 is laminated on a portion of the main lead 300 for forming the main back terminal portion 320, and is made of, for example, Ni, Sn having a thickness of about 0.06 mm, or an alloy thereof. In the present embodiment, for convenience, the lower surface in the z direction of the main back plating layer 321 is defined as the main back terminal portion 320. A terminal portion 320 may be configured.

  The main full thickness portion 330 is a portion extending from the die pad portion 310 to the main back surface terminal portion 320 in the z direction. In the present embodiment, the main full thickness portion 330 indicates a portion made of Cu excluding the main back plating layer 321 and has a thickness of about 0.1 mm. As with the main back surface terminal portion 320, the main full thickness portion 330 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.48 mm.

  The main eaves part 340 protrudes from the part of the main full thickness part 330 on the die pad part 310 side in the x and y directions perpendicular to the z direction. The main eaves portion 340 has a z-direction upper end surface that is flush with the main full thickness portion 330. In the present embodiment, the main eaves part 340 has a main front part 341, a main side part 342, and a main rear part 343. The thickness of the main eaves part 340 is, for example, half of the main full thickness part 330 and is about 0.05 mm.

  The main front portion 341 protrudes from the main full thickness portion 330 toward the first sub lead 400 and the second sub lead 500 in the x direction. In the present embodiment, the main front portion 341 has a rectangular shape with an x-direction dimension of about 0.21 mm and a y-direction dimension of about 0.5 mm.

  The main side portion 342 protrudes from the main full thickness portion 330 in the y direction. In the present embodiment, two main side portions 342 are formed. The main side portion 342 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.01 mm. In the present embodiment, the main lead 300 has two main side connecting portions 351. The main side connection part 351 extends from the main side part 342 of the main eaves part 340 and has the same thickness as the main side part 342. An end surface in the y direction of the main side connecting portion 351 is exposed from the resin package 800. The main side connecting portion 351 has an x-direction dimension of about 0.1 mm and a y-direction dimension of about 0.04 mm.

  The main rear part 343 protrudes from the main full thickness part 330 to the side opposite to the main front part 341. The main rear portion 343 has an x-direction dimension of about 0.01 mm and a y-direction dimension of about 0.5 mm. In the present embodiment, the main lead 300 has two main rear connecting portions 352. The main rear connection part 352 extends from the main rear part 343 of the main eaves part 340 and has the same thickness as the main rear part 343. An end surface in the x direction of the main rear connecting portion 352 is exposed from the resin package 800. The main rear connecting portion 352 has an x-direction dimension of about 0.04 mm and a y-direction dimension of about 0.1 mm.

  With the above-described configuration, in the present embodiment, all of the main full thickness portion 330 is surrounded by the main eaves portion 340 when viewed in the z direction. Moreover, the z-direction upper surface of the main full thickness part 330 and the main eaves part 340 is a die pad part 310, and the main surface plating layer 311 overlaps all of the main full thickness part 330 and the main eaves part 340. Further, as clearly shown in FIG. 18, the semiconductor element 200 has approximately half of the semiconductor element 200 overlapped with the main full thickness portion 330 as viewed in the z direction, and the other half overlapped with the main front portion 341 of the main eaves portion 340. Yes. The first surface electrode 211 as a gate electrode overlaps with the main full thickness part 330, and the second surface electrode 212 as a source electrode overlaps with the main front part 341 of the main eaves part 340.

  As shown in FIG. 21, in the semiconductor element 200, the back electrode 220 is bonded to the die pad portion 310 (main surface plating layer 311). Specifically, back electrode 220 as a single metal layer is directly bonded to die pad portion 310 (main surface plating layer 311) by, for example, a thermocompression bonding technique. In this thermocompression bonding, no vibration is applied, and only heat and pressure are applied.

  The first sub lead 400 is spaced apart from the main lead 300 in the x direction, and includes a first wire bonding portion 410, a first sub back terminal portion 420, a first sub full thickness portion 430, and a first sub lead. An eaves portion 440 is provided. The first sub lead 400 is formed, for example, by performing patterning such as etching on a metal plate made of Cu.

  The first wire bonding part 410 faces upward in the z direction and is a part to which the first wire 600 is bonded. In the present embodiment, the first wire bonding portion 410 has a rectangular shape with an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.2 mm. In the present embodiment, the first subsurface plating layer 411 is formed on the first wire bonding portion 410. The first subsurface plating layer 411 is formed over the entire area of the first wire bonding portion 410. The first subsurface plating layer 411 is made of Ag having a thickness of about 2 μm, for example. In FIG. 16, for the sake of easy understanding, the first subsurface plating layer 411 is halftone.

  The first sub-back surface terminal portion 420 faces downward in the z direction opposite to the first wire bonding portion 410 and is used for surface mounting the semiconductor device 101. The first sub-back terminal portion 420 has a rectangular shape with an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm. The first sub-back terminal portion 420 entirely overlaps the first wire bonding portion 410 when viewed in the z direction, and is included in the first wire bonding portion 410. In the present embodiment, a first sub back plating layer 421 is formed on the first sub lead 400. The first sub-back plating layer 421 is laminated on a portion of the first sub-lead 400 for forming the first sub-back terminal portion 420. For example, Ni, Sn having a thickness of about 0.06 mm, or these Made of alloy. In the present embodiment, for convenience, the lower surface in the z direction of the first sub back plating layer 421 is defined as the first sub back terminal portion 420. For example, in the configuration that does not include the first sub back plating layer 421, the above-described Cu The first sub-back terminal portion 420 may be configured by the portion made up of.

  The first sub full thickness portion 430 is a portion extending from the first wire bonding portion 410 to the first sub back surface terminal portion 420 in the z direction. In this embodiment, the 1st sub full thickness part 430 points out the site | part which consists of Cu except the 1st sub back plating layer 421, and the thickness is about 0.1 mm. The first sub full thickness portion 430 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm, similarly to the first sub-back terminal portion 420.

  The first sub eaves part 440 protrudes from the first wire bonding part 410 side portion of the first sub full thickness part 430 in the x and y directions perpendicular to the z direction. The first sub eaves portion 440 has a z-direction upper end surface that is flush with the first sub full thickness portion 430. In the present embodiment, the first sub eaves part 440 includes a first sub front part 441, a first sub side part 442, and a first sub rear part 443. The thickness of the 1st sub eaves part 440 is a half of the 1st sub full thickness part 430, for example, and is about 0.05 mm.

  The first sub front part 441 protrudes from the first sub full thickness part 430 toward the main lead 300 in the x direction. In the present embodiment, the first sub-front portion 441 has an x-direction dimension of about 0.01 mm and a y-direction dimension of about 0.2 mm.

  The first secondary side portion 442 protrudes from the first secondary full thickness portion 430 in the y direction. In the present embodiment, two first sub lateral portions 442 are formed. In FIG. 18, the first sub lateral portion 442 located in the upper direction in the y direction diagram protrudes toward the second sub lead 500, and the x direction dimension is about 0.2 mm and the y direction dimension is about 0.06 mm. is there. The first sub lateral portion 442 located in the lower direction in the y direction diagram has a y direction x direction dimension of about 0.2 mm and a y direction dimension of about 0.01 mm. In the present embodiment, the first sub lead 400 has a first sub side connecting portion 451. The first auxiliary side connecting portion 451 extends downward from the first auxiliary side portion 442 of the first auxiliary eaves portion 440 in the y-direction diagram in FIG. 18 and has the same thickness as the first auxiliary side portion 442. ing. The end surface in the y direction of the first sub lateral connecting portion 451 is exposed from the resin package 800. The first sub-side connecting portion 451 has an x-direction dimension of about 0.1 mm and a y-direction dimension of about 0.04 mm.

  The first sub rear portion 443 protrudes from the first sub full thickness portion 430 to the side opposite to the first sub front portion 441. The first auxiliary rear portion 443 has an x-direction dimension of about 0.01 mm and a y-direction dimension of about 0.14 mm. In the present embodiment, the first sub lead 400 has a first sub rear connecting portion 452. The first sub-back connecting portion 452 extends from the first sub-back portion 443 of the first sub eaves portion 440 and has the same thickness as the first sub-back portion 443. An end surface in the x direction of the first sub-rear connecting portion 452 is exposed from the resin package 800. The first sub-rear connecting portion 452 has an x-direction dimension of about 0.04 mm and a y-direction dimension of about 0.1 mm.

  With the above-described configuration, in the present embodiment, all of the first sub full thickness portion 430 is surrounded by the first sub eaves portion 440 when viewed in the z direction. Further, the upper surfaces in the z direction of the first sub full thickness portion 430 and the first sub eaves portion 440 are first wire bonding portions 410, and the first sub total surface plating layer 411 includes the first sub full thickness portion 430 and It overlaps with all of the first sub eaves part 440.

  The second sub lead 500 is disposed in the x direction away from the main lead 300 at a position aligned with the first sub lead 400 in the y direction. The second wire bonding portion 510 and the second sub back surface terminal portion. 520, a second sub full thickness portion 530, and a second sub eaves portion 540. The second sub lead 500 is formed by patterning such as etching on a metal plate made of Cu, for example.

  The second wire bonding portion 510 faces upward in the z direction, and is a portion where the second wire 700 is bonded. In the present embodiment, the second wire bonding portion 510 has a rectangular shape with an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.2 mm. In the present embodiment, the second subsurface plating layer 511 is formed on the second wire bonding portion 510. The second subsurface plating layer 511 is formed over the entire area of the second wire bonding portion 510. The second subsurface plating layer 511 is made of Ag having a thickness of about 2 μm, for example. In FIG. 16, the second subsurface plating layer 511 is halftone for convenience of understanding.

  The second sub-back terminal portion 520 faces downward in the z direction opposite to the second wire bonding portion 510 and is used for surface mounting the semiconductor device 101. The second sub-back terminal portion 520 has a rectangular shape with an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm. The second sub-back terminal portion 520 is entirely overlapped with the second wire bonding portion 510 when viewed in the z direction, and is included in the second wire bonding portion 510. In the present embodiment, a second sub back plating layer 521 is formed on the second sub lead 500. The second sub-back plating layer 521 is stacked on the second sub-lead 500 at a portion for forming the second sub-back terminal portion 520. For example, Ni, Sn having a thickness of about 0.06 mm, or these Made of alloy. In the present embodiment, for convenience, the lower surface in the z direction of the second sub back plating layer 521 is defined as the second sub back terminal portion 520. For example, in the configuration that does not include the second sub back plating layer 521, the above-described Cu The second sub-back terminal portion 520 may be configured by the portion made of

  The second sub full thickness portion 530 is a portion extending from the second wire bonding portion 510 to the second sub back surface terminal portion 520 in the z direction. In this embodiment, the 2nd sub full thickness part 530 points out the site | part which consists of Cu except the 2nd sub back plating layer 521, and the thickness is about 0.1 mm. The second sub full thickness part 530 has an x-direction dimension of about 0.18 mm and a y-direction dimension of about 0.13 mm, similarly to the second sub-back surface terminal part 520.

  The second sub eaves portion 540 protrudes from the second wire bonding portion 510 side portion of the second sub full thickness portion 530 in the x direction and the y direction that are perpendicular to the z direction. The second sub eaves portion 540 has a z-direction upper end surface that is flush with the second sub full thickness portion 530. In the present embodiment, the second sub eaves part 540 includes a second sub front part 541, a second sub side part 542, and a second sub rear part 543. The thickness of the second auxiliary eaves part 540 is, for example, half of the second auxiliary full thickness part 530 and is about 0.05 mm.

  The second auxiliary front part 541 protrudes from the second auxiliary full thickness part 530 toward the main lead 300 in the x direction. In the present embodiment, the second sub-front portion 541 has an x-direction dimension of about 0.01 mm and a y-direction dimension of about 0.2 mm.

  The second sub lateral portion 542 protrudes from the second sub full thickness portion 530 in the y direction. In the present embodiment, two second sub lateral portions 542 are formed. In FIG. 18, the second sub-side portion 542 located below in the y-direction diagram protrudes toward the first sub-lead 400 and has an x-direction dimension of about 0.2 mm and a y-direction dimension of about 0.06 mm. is there. The second sub lateral portion 542 located in the upper direction in the y direction diagram has an x direction dimension of about 0.2 mm and a y direction dimension of about 0.01 mm. In the present embodiment, the second sub lead 500 has a second sub side connecting portion 551. The second secondary side connecting portion 551 extends upward from the second secondary side portion 542 of the second secondary eave portion 540 in the y-direction diagram in FIG. 18 and has the same thickness as the second secondary side portion 542. ing. An end surface in the y direction of the second sub lateral connecting portion 551 is exposed from the resin package 800. The second sub-side connecting portion 551 has an x-direction dimension of about 0.1 mm and a y-direction dimension of about 0.04 mm.

  The second auxiliary rear part 543 protrudes from the second auxiliary full thickness part 530 to the side opposite to the second auxiliary front part 541. The second sub rear portion 543 has an x-direction dimension of about 0.01 mm and a y-direction dimension of about 0.14 mm. In the present embodiment, the second sub lead 500 has a second sub rear connecting portion 552. The second secondary rear connecting portion 552 extends from the second secondary rear portion 543 of the second secondary eaves portion 540 and has the same thickness as the second secondary rear portion 543. An end surface in the x direction of the second sub-rear connecting portion 552 is exposed from the resin package 800. The second sub-rear connecting portion 552 has an x-direction dimension of about 0.04 mm and a y-direction dimension of about 0.1 mm.

  With the above-described configuration, in the present embodiment, all of the second sub full thickness portion 530 is surrounded by the second sub eaves portion 540 when viewed in the z direction. The z-direction upper surfaces of the second sub full thickness portion 530 and the second sub eaves portion 540 are second wire bonding portions 510, and the second sub total surface plating layer 511 includes the second sub full thickness portion 530 and It overlaps with all of the second sub eaves part 540.

  The first wire 600 is bonded to the first surface electrode 211 of the semiconductor element 200 and the first wire bonding part 410 of the first sub lead 400, and has a first bonding part 610 and a second bonding part 620. The first wire 600 is made of Au having a diameter of about 20 μm.

  The first bonding portion 610 is bonded to the first wire bonding portion 410 of the first sub lead 400 and has a crown-shaped lump portion. The second bonding unit 620 is bonded to the first surface electrode 211 of the semiconductor element 200 through the first bump 630. The second bonding portion 620 has a tapered shape in which the thickness in the z direction becomes smaller toward the tip. The first bump 630 is a portion similar to the lump portion of the first bonding unit 610. In the present embodiment, the first bump 630 has a slightly smaller volume than the above-mentioned lump portion of the first bonding portion 610.

  The second wire 700 is bonded to the second surface electrode 212 of the semiconductor element 200 and the second wire bonding portion 510 of the second sub lead 500, and has a first bonding portion 710 and a second bonding portion 720. The second wire 700 is made of Au having a diameter of about 20 μm.

  The first bonding portion 710 is bonded to the second wire bonding portion 510 of the second sub lead 500 and has a crown-shaped lump portion. The second bonding part 720 is bonded to the second surface electrode 212 of the semiconductor element 200 through the second bump 730. The second bonding portion 720 has a tapered shape in which the z-direction thickness decreases toward the tip. The second bump 730 is a part similar to the lump part of the first bonding part 710. In the present embodiment, the volume of the second bump 730 is slightly smaller than the above-described lump portion of the first bonding portion 710.

  The resin package 800 covers the semiconductor element 200 and part of the main lead 300, the first sub lead 400, and the second sub lead 500, and is made of, for example, black epoxy resin. In the resin package 800, the main back terminal portion 320 of the main lead 300, the first sub back terminal portion 420 of the first sub lead 400, and the second sub back terminal portion 520 of the second sub lead 500 are all arranged in the z direction. It is exposed on the lower side. In the present embodiment, the distance between the upper ends in the z direction of the first wires 600 and the second wires 700 and the upper end in the z direction of the resin package 800 is about 50 μm.

  Next, an example of a method for manufacturing the semiconductor device 101 will be described below with reference to FIGS.

  26 to 32, the process of bonding the first wire 600 will be mainly described, but the second wire 700 is bonded by the same process. First, as shown in FIG. 26, the semiconductor element 200 is bonded to the main lead 300. At this time, if a lead frame in which a plurality of main leads 300, first sub leads 400, and second sub leads 500 are connected to each other is used, manufacturing efficiency can be improved. A capillary Cp is prepared, and the wire 601 is exposed from the tip. The wire 601 is made of Au having a diameter of about 20 μm. Then, a ball 602 is formed at the tip of the wire 601 by generating a spark immediately above the first surface electrode 211 of the semiconductor element 200.

  Next, as shown in FIG. 27, the ball 602 is joined to the first surface electrode 211 of the semiconductor element 200 by lowering the capillary Cp. Then, the capillary Cp is raised with the wire 601 fixed to the capillary Cp. As a result, as shown in FIG. 28, the first bump 630 is formed on the first surface electrode 211.

  Next, as shown in FIG. 29, a ball 602 is formed again at the tip of the wire 601 by generating a spark immediately above the first wire bonding portion 410 of the first sub lead 400. Next, as shown in FIG. 30, the ball 602 is joined to the first wire bonding portion 410 of the first sub lead 400 by lowering the capillary Cp.

  Next, the capillary Cp is moved as shown in FIG. 31 without fixing the wire 601 to the capillary Cp. Thereby, first, the first bonding part 610 is formed. Further, the tip of the capillary Cp is pressed against the first bump 630. At this time, the wire 601 is sandwiched between the capillary Cp and the first bump 630. Further, for example, heat and vibration may be applied via a support base (not shown) that holds the main lead 300. The capillary Cp is separated from the semiconductor element 200 with the wire 601 fixed to the capillary Cp. Thereby, the second bonding part 620 is formed. FIG. 32 is an enlarged image obtained by photographing the second bonding unit 620 and the first bump 630 from above in the z direction. As clearly shown in the figure, the second bonding part 620 having a slightly widened shape is joined to the first bump 630 having a circular shape in plan view.

  Thereafter, the bonding process of the second wire 700 is performed together with the bonding process of the first wire 600. Further, for example, a black epoxy resin is used so as to cover the semiconductor element 200, a part of each of the main lead 300, the first sub lead 400, and the second sub lead 500, and the first wire 600 and the second wire 700. A plate-shaped resin member is formed. FIG. 33 shows the above-described lead frame, semiconductor element 200, first wire 600, and second wire 700, which are covered with the resin member (not shown). And the semiconductor device 101 shown in FIGS. 16-24 is obtained by cut | disconnecting the said resin member and the said lead frame collectively along the cutting line CL in a figure.

  Next, the operation of the semiconductor device 101 will be described.

  According to the present embodiment, the die pad portion 310 and the semiconductor element 200 overlap both the main full thickness portion 330 and the main eaves portion 340 when viewed in the z direction. The main eaves part 340 exhibits a function of increasing the bonding strength between the main lead 300 and the resin package 800. It is possible to suppress the main lead 300 from excessively protruding from the semiconductor element 200 while improving the bonding strength. This contributes to reducing the size of the semiconductor device 101 viewed in the z direction. In addition, at least one of the first surface electrode 211 and the second surface electrode 212 overlaps the main eaves part 340 is advantageous in reducing the size of the semiconductor device 101 viewed in the z direction. The second bonding portion 620 of the first wire 600 is bonded to the first surface electrode 211 via the first bump 630, and the second bonding portion 720 of the second wire 700 is bonded to the second surface electrode 212 via the second bump 730. By adopting a configuration in which the first wire 600 and the second wire 700 are bonded to each other, the height in the z direction can be reduced. This contributes to reducing the height of the semiconductor device 101 in the z direction. Therefore, according to the present embodiment, the semiconductor device 101 can be downsized.

  Since the first surface electrode 211 as the gate electrode is further away from the first sub lead 400 and the second sub lead 500 than the second surface electrode 212 as the source electrode, the length of the first wire 600 is increased. Can be made longer than the second wire 700. The first wire 600 having a longer length is particularly easy to increase the bonding strength in the second bonding portion 620. In general, the first surface electrode 211 as a gate electrode is formed on a relatively smooth surface of the semiconductor layer 231 via an insulating layer (not shown). Such a first surface electrode 211 is relatively difficult to improve the bonding strength of wire bonding. On the other hand, the second surface electrode 212 as a source electrode is often connected to a metal portion filled in a plurality of trenches (pits) formed in the semiconductor layer 231. With such a configuration, the second surface electrode 212 is relatively easy to improve the bonding strength of wire bonding. Therefore, bonding the first wire 600 that easily increases the bonding strength to the first surface electrode 211 as the gate electrode, which is relatively concerned about the bonding strength, is advantageous in avoiding problems such as wire peeling. .

  As the first surface electrode 211 overlaps with the main full thickness portion 330 when viewed in the z direction, as shown in FIGS. On the other hand, the capillary Cp can be pressed more reliably. On the other hand, by disposing the second surface electrode 212 as a source electrode that is relatively easy to improve the bonding strength at a position overlapping the main eaves part 340 when viewed in the z direction, the size of the semiconductor device 101 when viewed in the z direction is reduced. be able to.

  Since the main eaves part 340 includes the main front part 341, the bonding strength between the main lead 300 and the resin package 800 can be increased. Further, the main back terminal portion 320, the first sub back terminal portion 420, and the second sub back terminal portion 520 are unduly approached while bringing the semiconductor element 200, the first sub lead 400, and the second sub lead 500 close to each other. You can avoid that.

  Since the main eaves part 340 includes the main side part 342 and the main rear part 343, the bonding strength between the main lead 300 and the resin package 800 can be increased. The configuration in which all of the main full thickness portion 330 is surrounded by the main eaves portion 340 is suitable for increasing the bonding strength between the main lead 300 and the resin package 800.

  The main side connecting portion 351 and the main rear connecting portion 352 appropriately hold the main lead 300 in the manufacturing process of the semiconductor device 101. Although the end surface in the y direction of the main side connection portion 351 and the end surface in the x direction of the main rear connection portion 352 are exposed from the resin package 800, they are separated from the main back surface terminal portion 320. For this reason, there is little possibility that the solder for surface mounting the semiconductor device 101 will accidentally spread on the y-direction end surface of the main side connection portion 351 and the x-direction end surface of the main rear connection portion 352.

  By forming the main surface plating layer 311 on the die pad portion 310, the bonding strength between the back electrode 220 of the semiconductor element 200 and the die pad portion 310 can be increased. When the main surface plating layer 311 overlaps all of the main eaves part 340, the area that can be used as the die pad part 310 can be expanded.

  Since the first sub lead 400 includes the first sub eaves portion 440, the bonding strength between the first sub lead 400 and the resin package 800 can be increased. Since the first sub eaves portion 440 includes the first sub front portion 441, the bonding strength with the resin package 800 is increased, and the distance between the first sub back terminal portion 420 and the main back terminal portion 320 is unreasonably set. It is possible to avoid approaching.

  Since the first sub eaves part 440 includes the first sub side part 442 and the first sub rear part 443, the bonding strength between the first sub lead 400 and the resin package 800 can be increased. The configuration in which the first sub full thickness portion 430 is entirely surrounded by the first sub eaves portion 440 is suitable for increasing the bonding strength between the first sub lead 400 and the resin package 800. Since the first sub-side portion 442 on the second sub-lead 500 side is relatively large, the bonding strength is improved and the first sub-back terminal portion 420 and the second sub-back terminal portion 520 are inappropriate. Can be avoided.

  The first sub-side connecting portion 451 and the first sub-rear connecting portion 452 appropriately hold the first sub lead 400 in the manufacturing process of the semiconductor device 101. The y-direction end surface of the first sub-side connecting portion 451 and the x-direction end surface of the first sub-rear connecting portion 452 are exposed from the resin package 800 but are separated from the first sub-back terminal portion 420. For this reason, there is little possibility that the solder for surface mounting the semiconductor device 101 will spread on the y-direction end surface of the first sub-side connection portion 451 and the x-direction end surface of the first sub-rear connection portion 452 by mistake.

  By forming the first subsurface plating layer 411 on the first wire bonding portion 410, the bonding strength between the first wire 600 and the first wire bonding portion 410 can be increased.

  Since the second sub lead 500 includes the second sub eaves portion 540, the bonding strength between the second sub lead 500 and the resin package 800 can be increased. Since the second sub eaves portion 540 includes the second sub front portion 541, the bonding strength between the resin package 800 and the distance between the second sub back terminal portion 520 and the main back terminal portion 320 is unreasonably increased. It is possible to avoid approaching.

  Since the second sub eaves portion 540 includes the second sub side portion 542 and the second sub rear portion 543, the bonding strength between the second sub lead 500 and the resin package 800 can be increased. The configuration in which the second sub full thickness portion 530 is entirely surrounded by the second sub eaves portion 540 is suitable for increasing the bonding strength between the second sub lead 500 and the resin package 800. Since the second sub-side portion 542 on the first sub-lead 400 side is relatively large, the bonding strength is improved, and the second sub-back terminal portion 520 and the first sub-back terminal portion 420 are inappropriate. Can be avoided.

  The second sub lateral connecting portion 551 and the second sub rear connecting portion 552 appropriately hold the second sub lead 500 in the manufacturing process of the semiconductor device 101. Although the y-direction end surface of the second sub-side connecting portion 551 and the x-direction end surface of the second sub-rear connecting portion 552 are exposed from the resin package 800, they are separated from the second sub-back surface terminal portion 520. For this reason, there is little possibility that the solder for surface mounting the semiconductor device 101 spreads inadvertently on the y-direction end surface of the second sub-side connecting portion 551 and the x-direction end surface of the second sub-rear connecting portion 552.

  By forming the second subsurface plating layer 511 on the second wire bonding portion 510, the bonding strength between the second wire 700 and the second wire bonding portion 510 can be increased.

  In joining the semiconductor element 200 and the die pad portion 310 of the main lead 300, the back electrode 220 made of a single metal layer is directly joined to the die pad portion 310, and no vibration is applied during the joining. With such a configuration, it is not necessary to set a margin area in consideration of vibration in an area located around the semiconductor element 200 in the main lead 300. This is advantageous for miniaturization of the semiconductor device 101.

  FIG. 34 is an X-ray image of the semiconductor device 101. As clearly shown in the figure, when the main lead 300, the first sub lead 400, and the second sub lead 500 are patterned by etching, the boundary between the main full thickness portion 330 and the main eaves portion 340 is as shown in FIG. The clear corners shown in FIG. 24 are not formed but are curved. Similarly, the boundary between the first sub full thickness portion 440 and the first sub eaves portion 440 in the first sub lead 400 or the second sub full thickness portion 540 and the second sub eaves portion 540 in the second sub lead 500. The boundary is also a curved surface. This is because, even if the design intended for the forms shown in FIGS. 16 to 24 is performed, if the semiconductor device 101 has the above-described very small configuration, the above-described curved surface is inevitably generated in the etching process. .

  FIG. 35 shows a semiconductor device according to the fourth embodiment of the present invention. In the figure, the same or similar elements as those of the above embodiment are denoted by the same reference numerals as those of the above embodiment.

  In the present embodiment, the first surface electrode 211 overlaps both the main full thickness part 330 and the main eaves part 340 when viewed in the z direction. The first bump 630 and the second bonding portion 620 of the first wire 600 overlap both the main full thickness portion 330 and the main eaves portion 340 in the z direction view. In the figure, a broken line extending in the y direction overlaps the first bump 630 and the second bonding portion 620 of the first wire 600. This broken line is the boundary between the main full thickness part 330 and the main eaves part 340 when viewed in the z direction. Such an embodiment can also reduce the size of the semiconductor device 102.

  The semiconductor device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be modified in various ways.

  The semiconductor element referred to in the present invention is not limited to a transistor, and various semiconductor elements having a first surface electrode and a second surface electrode can be used.

DESCRIPTION OF SYMBOLS 101 Semiconductor device 102 Semiconductor device 200 Semiconductor element 201 Front surface 202 Back surface 211 First surface electrode 212 Second surface electrode 220 Back surface electrode 231 Semiconductor layer 232 Eutectic layer 300 Main lead 310 Main lead main surface 311 Main surface plating layer 320 Main lead back surface 330 Main full thickness part 340 Main eaves part 341 Main front part 342 Main side part 343 Main rear part 351 Main side connection part 352 Main rear connection part 400 First sub lead 410 First sub lead main surface 411 First sub surface Plating layer 420 First sub lead back surface 430 First sub full thickness portion 440 First sub eaves portion 441 First sub front portion 442 First sub inner portion 460 First sub extension portion 461 First sub rear portion 462 First Secondary side portion 481 First secondary lead end surface 482 First secondary lead side surface 500 Second secondary lead 510 Second secondary lead main surface 511 Second secondary surface plating Layer 520 Second secondary lead back surface 530 Second secondary full thickness part 540 Second secondary eaves part 541 Second secondary front part 542 Second secondary inward part 560 Second secondary extension part 561 Second secondary rear part 562 Second secondary Side portion 581 Second secondary lead end surface 582 Second secondary lead side surface 600 First wire 610 First bonding portion 620 Second bonding portion 630 First bump 700 Second wire 710 First bonding portion 720 Second bonding portion 730 Second bump 800 Resin package 801 Resin main surface 802 Resin back surface 803 First resin side surface 804 Second resin side surface 805 Second resin end surface 806 Second resin end surface 901 Tape Ct1 Line Ct2 Line x direction y direction z Thickness direction 101, 102 Semiconductor device 200 Semiconductor element 201 Front surface 202 Back surface 211 First surface electrode 212 Second surface electrode 213 Electrode layer 214 Removal region 216 Active region 217 MOSFET
218 Unit cell 220 Back electrode (single metal layer)
231 Semiconductor layer 232 Eutectic layer 300 Main lead 310 Die pad part 311 Main surface plating layer 320 Main back terminal part 321 Main back plating layer 330 Main full thickness part 340 Main eaves part 341 Main front part 342 Main side part 343 Main rear part 351 Main side connecting portion 352 Main rear connecting portion 400 First sub lead 410 First wire bonding portion 411 First sub surface plating layer 420 First sub back terminal portion 421 First sub back plating layer 430 First sub full thickness portion 440 1st sub eaves part 441 1st sub front part 442 1st sub side part 443 1st sub back part 451 1st sub side connection part 452 1st sub back connection part 500 2nd sub lead 510 Second wire bonding Part 511 Second sub-surface plating layer 520 Second sub-back terminal part 521 Second sub-back plating layer 530 Second sub full thickness part 540 Second sub eaves part 541 Second Sub-front part 542 Second sub-side part 543 Second sub-rear part 551 Second sub-side connection part 552 Second sub-rear connection part 600 First wire 610 First bonding part 620 Second bonding part 630 First bump 700 Second Wire 710 First bonding portion 720 Second bonding portion 730 Second bump 800 Resin package Cp Capillary 601 Wire 602 Ball

Claims (39)

A semiconductor element;
A main lead on which the semiconductor element is disposed;
A first sub lead that is separated from the main lead and is electrically connected to the semiconductor element;
A resin package that covers the semiconductor element, the main lead, and the first sub lead, and has a rectangular shape in the thickness direction of the semiconductor element;
The resin package has a first surface having a normal direction parallel to the thickness direction and a second surface having a normal direction perpendicular to the thickness direction,
The main lead and the first sub lead are exposed from the first surface of the resin package;
The main lead has a first part exposed from the second surface of the resin package, and the first sub lead has a second part exposed from the second surface of the resin package, The size of the thickness direction of 1 part and the 2nd part differs in a semiconductor device mutually.   The semiconductor device according to claim 1, wherein the semiconductor element includes a portion that does not overlap the main lead when viewed in the thickness direction. The main lead has a main lead main surface and a main lead back surface facing each other,
The semiconductor element is arranged on the main lead main surface,
The semiconductor device according to claim 1, wherein the back surface of the main lead is exposed from the first surface of the resin package. The main lead includes a main full thickness part and a main eaves part,
The main full thickness portion is a portion extending from the main lead main surface to the main lead back surface,
The semiconductor device according to claim 3, wherein the main eaves part protrudes from the main full thickness part in a direction perpendicular to the thickness direction.   The semiconductor device according to claim 4, wherein the entire main full thickness portion overlaps with the semiconductor element in the thickness direction view.   The semiconductor device according to claim 4, wherein the main eaves portion has a main front portion, and the main front portion protrudes from the main full thickness portion toward the first sub lead.   The main eaves portion has a main side portion, and the main side portion protrudes from the main full thickness portion in a direction perpendicular to a direction in which the main front portion protrudes. 6. The semiconductor device according to 6.     The semiconductor device according to claim 7, wherein the main lead includes a main side connection portion protruding from the main side portion, and the main side connection portion has an end surface exposed from the resin package.   The semiconductor according to claim 6, wherein the main eaves portion has a main rear portion, and the main rear portion protrudes from the main full thickness portion in a direction opposite to a direction in which the main front portion protrudes. apparatus.   The semiconductor device according to claim 9, wherein the main lead includes a main rear connection portion that protrudes from the main rear portion, and the main rear connection portion has an end surface that is exposed from the resin package.   5. The semiconductor device according to claim 4, wherein the main full thickness portion is surrounded by the main eaves portion as viewed in the thickness direction throughout.   The semiconductor device according to claim 4, wherein the main eaves part overlaps the semiconductor element as viewed in the thickness direction throughout.   The semiconductor device according to claim 4, further comprising a main surface plating layer formed on the main lead and interposed between the semiconductor element and the main lead.   The semiconductor device according to claim 13, wherein the main surface plating layer overlaps the entire main eaves portion. The first sub lead has a first sub lead main surface and a first sub lead back surface facing opposite to each other, and the first sub lead back surface is exposed from the resin package;
The first sub lead includes a first sub full thickness portion and a first sub eaves portion,
The first sub full thickness portion is a portion extending from the first sub lead main surface to the first sub lead back surface,
The first sub eaves portion protrudes from the first sub full thickness portion in a direction perpendicular to the thickness direction of the semiconductor element and constitutes the first sub lead main surface. The semiconductor device according to claim 1. The first sub eaves portion has a first sub front portion,
The semiconductor device according to claim 15, wherein the first sub front portion protrudes from the first sub full thickness portion toward the main lead.   The semiconductor device according to claim 15, wherein the first sub full thickness portion constitutes at least a part of the back surface of the first sub lead exposed from the resin package. The first sub lead includes a first sub extension part,
The first sub extension portion extends from the first sub full thickness portion in a direction perpendicular to the thickness direction of the semiconductor element, and constitutes the back surface of the first sub lead. And
The first sub extension portion is exposed from the resin package,
The semiconductor device according to claim 15, wherein the first sub extension portion has an end surface that is parallel to the thickness direction and exposed from the resin package. The first sub lead has a first sub lead main surface and a first sub lead back surface facing to opposite sides,
The semiconductor device according to claim 1, wherein the back surface of the first sub lead is exposed from the resin package.   The semiconductor device according to claim 19, wherein the back surface of the first sub lead is flush with the first surface of the resin package.   The first sub lead has a first sub lead end surface connected to a back surface of the first sub lead, and the first sub lead end surface faces a side opposite to a side where the main lead is located. 19. The semiconductor device according to 19.   The semiconductor device according to claim 21, wherein the first sub-lead end surface is exposed from the resin package. The resin package has a first resin end surface that faces the same direction as the first sub-lead end surface.
The semiconductor device according to claim 21, wherein the first resin end surface is flush with the first sub lead end surface.   The second portion of the first sub-lead includes a first sub-lead side surface connected to the back surface of the first sub-lead, and the first sub-lead side surface extends in a direction facing the end surface of the first sub-lead and the semiconductor element. The semiconductor device according to claim 21, wherein the semiconductor device faces in a direction perpendicular to any of the thickness directions.   25. The semiconductor device according to claim 24, wherein the side surface of the first sub lead is exposed from the resin package. The resin package has a first resin side surface facing in the same direction as the direction of the first sub lead side surface,
25. The semiconductor device according to claim 24, wherein the first sub-lead side surface is flush with the first resin side surface.   The semiconductor device according to claim 21, further comprising a first wire that is directly connected to the semiconductor element and electrically connects the semiconductor element and the first sub lead.   28. The semiconductor device according to claim 27, further comprising a first sub plating layer interposed between the first sub lead and the first wire. A second sub lead connected to the semiconductor element;
The semiconductor device according to claim 15, wherein the second sub lead is separated from the main lead and the first sub lead and is exposed from the resin package.   30. The semiconductor device according to claim 29, further comprising a second wire that is directly connected to the semiconductor element and that electrically connects the semiconductor element and the second sub lead.   31. The semiconductor device according to claim 30, further comprising a second sub plating layer interposed between the second sub lead and the second wire.   The semiconductor element has a semiconductor layer stacked on top of each other, a single crystal layer of a semiconductor and metal eutectic layer and a back electrode, and the single metal layer is directly bonded to the main lead. The semiconductor device according to claim 1.   The semiconductor device according to claim 32, wherein the eutectic layer is made of a eutectic of Si and Au.   The semiconductor device according to claim 32, wherein the single metal layer is thinner than the eutectic layer. A first wire;
The semiconductor device according to claim 4, wherein the semiconductor element includes a first surface electrode to which the first wire is bonded. A second wire;
36. The semiconductor device according to claim 35, wherein the semiconductor element includes a second surface electrode to which the second wire is bonded.   37. The semiconductor device according to claim 36, wherein at least one of the first surface electrode and the second surface electrode overlaps the main full thickness portion when viewed in the thickness direction. The main lead has a third portion exposed from the first surface,
The first sub lead has a fourth portion exposed from the first surface,
The third part is on the first side with respect to the center line of the first surface;
The fourth part is on the second side with respect to the center line of the first surface,
The semiconductor device according to claim 1, wherein the third part and the fourth part have different areas.   The first portion has a first edge perpendicular to the thickness direction, and the second portion has a second edge perpendicular to the thickness direction, and the first edge The semiconductor device according to claim 1, wherein the second edge is on the same line.