JP2020184578A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2020184578A
JP2020184578A JP2019088315A JP2019088315A JP2020184578A JP 2020184578 A JP2020184578 A JP 2020184578A JP 2019088315 A JP2019088315 A JP 2019088315A JP 2019088315 A JP2019088315 A JP 2019088315A JP 2020184578 A JP2020184578 A JP 2020184578A
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frame portion
semiconductor element
frame
semiconductor device
semiconductor
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JP7090579B2 (en
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英樹 山口
Hideki Yamaguchi
英樹 山口
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Mitsubishi Electric Corp
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

To provide a technique for suppressing one-sided contact of a joint area of a semiconductor element with respect to the tip of a capillary and improving the bondability between the semiconductor element and a wire.SOLUTION: A semiconductor device includes semiconductor elements 5, 6, and 7 and a lead frame. The lead frame includes a frame unit 2a on which the semiconductor element 5 is mounted, and frame portions 3a and 3b on which semiconductor elements 6 and 7 are mounted, and the frame portion 2a is located at the first height, and the frame portions 3a and 3b are located at the second height lower than the first height. The upper surfaces of the frame portions 3a and 3b are inclined with respect to the upper surface of the frame portion 2a.SELECTED DRAWING: Figure 1

Description

本発明は、段差のあるリードフレームに複数の半導体素子が搭載され、ボンディングヘッドに取り付けられたキャピラリの先端を複数の半導体素子のワイヤボンディング領域に接触させることでワイヤボンディングされる半導体装置およびその製造方法に関するものである。 The present invention is a semiconductor device in which a plurality of semiconductor elements are mounted on a lead frame having a step, and the tip of a capillary attached to a bonding head is brought into contact with a wire bonding region of the plurality of semiconductor elements to be wire-bonded. It's about the method.

パワー半導体装置では、複数の半導体素子間を配線するために、金ワイヤ、銀ワイヤ、銅ワイヤ、またはアルミワイヤを用いて、熱を加えながら超音波を印加し接合する方法が採用されている。キャピラリが取り付けられたボンディングヘッドの円弧動作によりワイヤボンディングされる。 In a power semiconductor device, in order to wire between a plurality of semiconductor elements, a method of using a gold wire, a silver wire, a copper wire, or an aluminum wire and applying ultrasonic waves while applying heat to join them is adopted. Wire bonding is performed by the arc motion of the bonding head to which the capillary is attached.

例えば特許文献１には、段差のないリードフレームなどの基板に搭載された半導体素子を傾けた状態で配置することで、キャピラリのワイヤボンディング領域への接触を避けてワイヤボンディング領域下の集積回路にクラックなどのダメージを与えないようにする技術が開示されている。 For example, in Patent Document 1, by arranging semiconductor elements mounted on a substrate such as a lead frame having no steps in an inclined state, contact with the wire bonding region of the capillary is avoided and the integrated circuit under the wire bonding region is formed. A technique for preventing damage such as cracks is disclosed.

特開２００４−１４６３７号公報Japanese Unexamined Patent Publication No. 2004-14637

段差のあるリードフレームでは、上側部分に搭載された半導体素子、下側部分に搭載された半導体素子の順にワイヤボンディングされ、ボンディングヘッドにおける上側部分に搭載された半導体素子から下側部分に搭載された半導体素子への高さ分の移動は円弧動作により行われる。 In the lead frame having a step, the semiconductor element mounted on the upper portion and the semiconductor element mounted on the lower portion are wire-bonded in this order, and the semiconductor element mounted on the upper portion of the bonding head is mounted on the lower portion. The movement of the height to the semiconductor element is performed by an arc operation.

上側部分と下側部分に搭載された半導体素子が水平面に配置されている場合、上側部分に搭載された半導体素子についてはキャピラリの先端が接合面であるワイヤボンディング領域に垂直に当たるが、下側部分に搭載された半導体素子についてはキャピラリが傾くことからキャピラリの先端がワイヤボンディング領域に片当たりする。そのため、下側部分に搭載された半導体素子については接合エネルギーが適切に接合面に伝わらず、半導体素子とワイヤとの接合性が低下するという問題があった。 When the semiconductor elements mounted on the upper part and the lower part are arranged on a horizontal plane, the tip of the capillary corresponds to the wire bonding region which is the bonding surface of the semiconductor element mounted on the upper part, but the lower part. Since the capillary of the semiconductor element mounted on the device is tilted, the tip of the capillary hits the wire bonding region. Therefore, the semiconductor element mounted on the lower portion has a problem that the bonding energy is not properly transmitted to the bonding surface and the bondability between the semiconductor element and the wire is lowered.

また、特許文献１に記載の技術では、第１半導体チップ側の第２半導体チップのワイヤボンディング領域の高さ位置が第１半導体チップのワイヤボンディング領域の高さ位置より高くなるように第２半導体チップが基板上に接着材で傾斜させて搭載されており、段差のあるリードフレームに第１，第２半導体チップが搭載されることについては想定されていない。 Further, in the technique described in Patent Document 1, the second semiconductor so that the height position of the wire bonding region of the second semiconductor chip on the first semiconductor chip side is higher than the height position of the wire bonding region of the first semiconductor chip. It is not assumed that the first and second semiconductor chips are mounted on the lead frame having a step, because the chip is mounted on the substrate at an angle with an adhesive.

そこで、本発明は、キャピラリの先端に対する半導体素子の接合面への片当たりを抑制し、半導体素子とワイヤとの接合性を向上させる技術を提供することを目的とする。 Therefore, an object of the present invention is to provide a technique for suppressing one-sided contact of the semiconductor element with respect to the tip of the capillary to the bonding surface and improving the bondability between the semiconductor element and the wire.

本発明に係る半導体装置は、第１半導体素子および第２半導体素子と、前記第１半導体素子が搭載された第１フレーム部と、前記第２半導体素子が搭載された第２フレーム部とを有し、かつ、前記第１フレーム部が第１高さに位置し前記第２フレーム部が前記第１高さよりも低い第２高さに位置するリードフレームとを備え、前記第２フレーム部の上面は、前記第１フレーム部の上面に対して傾斜するものである。 The semiconductor device according to the present invention includes a first semiconductor element, a second semiconductor element, a first frame portion on which the first semiconductor element is mounted, and a second frame portion on which the second semiconductor element is mounted. Moreover, the first frame portion is provided with a lead frame located at a first height and the second frame portion is located at a second height lower than the first height, and the upper surface of the second frame portion is provided. Is inclined with respect to the upper surface of the first frame portion.

本発明によれば、キャピラリの先端に対する第２半導体素子の接合面への片当たりを抑制することができる。これにより、第２半導体素子の接合面に対して接合エネルギーが伝わりやすくなることから、第２半導体素子とワイヤとの接合性を向上させることができる。 According to the present invention, it is possible to suppress one-sided contact of the second semiconductor element with respect to the tip of the capillary. As a result, the bonding energy is easily transmitted to the bonding surface of the second semiconductor element, so that the bonding property between the second semiconductor element and the wire can be improved.

実施の形態１に係る半導体装置の断面模式図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 1. FIG. 第１フレーム部上の第１半導体素子にワイヤボンディングする際のボンディングヘッドと第１フレーム部の位置関係を示す断面模式図である。It is sectional drawing which shows the positional relationship of the bonding head and the 1st frame part at the time of wire bonding to the 1st semiconductor element on the 1st frame part. 第２フレーム部上の第２半導体素子にワイヤボンディングする際のボンディングヘッドと第２フレーム部の位置関係を示す断面模式図である。It is sectional drawing which shows the positional relationship of the bonding head and the 2nd frame part at the time of wire bonding to the 2nd semiconductor element on the 2nd frame part. 実施の形態１に係る半導体装置であって、第２半導体素子の位置ずれと第２半導体素子の表面にはんだ付着が生じた状態における第２フレーム部およびその周辺の断面模式図である。FIG. 5 is a schematic cross-sectional view of a second frame portion and its surroundings in a state in which the position of the second semiconductor element is displaced and solder is adhered to the surface of the second semiconductor element in the semiconductor device according to the first embodiment. 実施の形態２に係る半導体装置が備える第２フレーム部およびその周辺の断面模式図である。FIG. 5 is a schematic cross-sectional view of a second frame portion and its periphery included in the semiconductor device according to the second embodiment. 実施の形態２に係る半導体装置が備える第２半導体素子の表面へのはんだ這い上がりが発生した場合における第２フレーム部およびその周辺の断面模式図である。FIG. 5 is a schematic cross-sectional view of a second frame portion and its periphery when solder creeps up to the surface of a second semiconductor element included in the semiconductor device according to the second embodiment. 実施の形態３に係る半導体装置が備える第２フレーム部およびその周辺の断面模式図である。FIG. 5 is a schematic cross-sectional view of a second frame portion and its periphery included in the semiconductor device according to the third embodiment. 実施の形態３に係る半導体装置においてはんだ流れが発生した場合における第２フレーム部およびその周辺の断面模式図である。FIG. 5 is a schematic cross-sectional view of a second frame portion and its surroundings when a solder flow occurs in the semiconductor device according to the third embodiment. 実施の形態４に係る半導体装置が備える第２フレーム部およびその周辺の断面模式図である。FIG. 5 is a schematic cross-sectional view of a second frame portion and its periphery included in the semiconductor device according to the fourth embodiment.

＜実施の形態１＞
本発明の実施の形態１について、図面を用いて以下に説明する。図１は、実施の形態１に係る半導体装置の断面模式図である。 <Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

図１に示すように、半導体装置は、半導体素子５，６，７、第１リードフレーム１、第２リードフレーム２、第３リードフレーム３、放熱板１１、絶縁層１２、および封止材１０を備えている。 As shown in FIG. 1, the semiconductor device includes semiconductor elements 5, 6 and 7, a first lead frame 1, a second lead frame 2, a third lead frame 3, a heat radiating plate 11, an insulating layer 12, and a sealing material 10. It has.

第２リードフレーム２は、第１リードフレーム１に対して同じ高さ位置に横方向に離間した状態で配置されている。半導体素子５は、はんだ４を介して第２リードフレーム２のフレーム部２ａに搭載されている。第２リードフレーム２のフレーム部２ａは第１高さに位置し、フレーム部２ａの上面は水平面である。 The second lead frame 2 is arranged at the same height position as the first lead frame 1 in a laterally separated state. The semiconductor element 5 is mounted on the frame portion 2a of the second lead frame 2 via the solder 4. The frame portion 2a of the second lead frame 2 is located at the first height, and the upper surface of the frame portion 2a is a horizontal plane.

ここで、フレーム部２ａは第２リードフレーム２における半導体素子５が搭載される部分およびその周辺である。フレーム部２ａが第１フレーム部に相当し、半導体素子５が第１半導体素子に相当する。 Here, the frame portion 2a is a portion of the second lead frame 2 on which the semiconductor element 5 is mounted and its periphery. The frame portion 2a corresponds to the first frame portion, and the semiconductor element 5 corresponds to the first semiconductor element.

第３リードフレーム３は、第２リードフレーム２に対して横方向に離間した状態で配置されている。半導体素子６は、はんだ４を介して第３リードフレーム３のフレーム部３ａに搭載されている。半導体素子７は、はんだ４を介して第３リードフレーム３のフレーム部３ｂに搭載されている。 The third lead frame 3 is arranged so as to be laterally separated from the second lead frame 2. The semiconductor element 6 is mounted on the frame portion 3a of the third lead frame 3 via the solder 4. The semiconductor element 7 is mounted on the frame portion 3b of the third lead frame 3 via the solder 4.

フレーム部３ａ，３ｂは、絶縁層１２を介して放熱板１１に配置されている。フレーム部３ａ，３ｂは第１高さよりも低い第２高さに位置している。フレーム部３ａ，３ｂの上面は、フレーム部２ａの上面に対して傾斜する傾斜面である。具体的には、フレーム部３ａ，３ｂの上面は、フレーム部２ａ側からフレーム部２ａとは反対側に渡って上方から下方に傾斜する傾斜面である。そのため、フレーム部３ａ，３ｂにおけるフレーム部２ａとは反対側のそれぞれの端部に隣接する位置に、段差３ｄ，３ｅが形成されている。なお、段差３ｄはフレーム部３ｂにおけるフレーム部２ａ側の端部により形成され、段差３ｅは第３リードフレーム３のフレーム部３ｃにおける内側の端部に形成されている。 The frame portions 3a and 3b are arranged on the heat radiating plate 11 via the insulating layer 12. The frame portions 3a and 3b are located at a second height lower than the first height. The upper surfaces of the frame portions 3a and 3b are inclined surfaces that are inclined with respect to the upper surface of the frame portions 2a. Specifically, the upper surface of the frame portions 3a and 3b is an inclined surface that inclines from the upper side to the lower side from the frame portion 2a side to the side opposite to the frame portion 2a. Therefore, steps 3d and 3e are formed at positions adjacent to the respective ends of the frame portions 3a and 3b on the opposite sides of the frame portions 2a. The step 3d is formed by the end portion of the frame portion 3b on the frame portion 2a side, and the step 3e is formed by the inner end portion of the frame portion 3c of the third lead frame 3.

また、フレーム部３ａ，３ｂの下面は水平面である。このようにフレーム部３ａ，３ｂ全体が傾いているのではなく、フレーム部３ａ，３ｂの上面のみに傾斜面が形成されることで、フレーム部３ａ，３ｂの下側に配置される絶縁層１２の厚みを均一にすることができる。 Further, the lower surfaces of the frame portions 3a and 3b are horizontal planes. In this way, the entire frame portions 3a and 3b are not inclined, but the inclined surface is formed only on the upper surface of the frame portions 3a and 3b, so that the insulating layer 12 arranged under the frame portions 3a and 3b The thickness of the can be made uniform.

ここで、フレーム部３ａは第３リードフレーム３における半導体素子６が搭載される部分およびその周辺であり、フレーム部３ｂは第３リードフレーム３における半導体素子７が搭載される部分およびその周辺である。フレーム部３ａ，３ｂが第２フレーム部に相当し、半導体素子６，７が第２半導体素子に相当する。また、第１リードフレーム１、第２リードフレーム２、および第３リードフレーム３が第１フレーム部と第２フレーム部とを有するリードフレームに相当する。 Here, the frame portion 3a is a portion of the third lead frame 3 on which the semiconductor element 6 is mounted and its periphery, and the frame portion 3b is a portion of the third lead frame 3 on which the semiconductor element 7 is mounted and its periphery. .. The frame portions 3a and 3b correspond to the second frame portion, and the semiconductor elements 6 and 7 correspond to the second semiconductor element. Further, the first lead frame 1, the second lead frame 2, and the third lead frame 3 correspond to a lead frame having a first frame portion and a second frame portion.

第１リードフレーム１と半導体素子５はワイヤ８ａで接続され、半導体素子５と半導体素子６はワイヤ８ｂで接続されている。半導体素子６と半導体素子７と第３リードフレーム３はワイヤ９で接続されている。なお、ワイヤ８ａ，８ｂ，９は、金ワイヤ、銀ワイヤ、銅ワイヤ、またはアルミワイヤである。 The first lead frame 1 and the semiconductor element 5 are connected by a wire 8a, and the semiconductor element 5 and the semiconductor element 6 are connected by a wire 8b. The semiconductor element 6, the semiconductor element 7, and the third lead frame 3 are connected by a wire 9. The wires 8a, 8b, and 9 are gold wires, silver wires, copper wires, or aluminum wires.

封止材１０は樹脂からなり、半導体素子５，６，７、第１リードフレーム１の一端部を除く部分、第２リードフレーム２、第３リードフレーム３の一端部を除く部分、絶縁層１２、および放熱板１１の底面を除く部分を覆いこれらを保護する。 The sealing material 10 is made of resin, and includes semiconductor elements 5, 6 and 7, a portion excluding one end of the first lead frame 1, a portion excluding one end of the second lead frame 2 and the third lead frame 3, and an insulating layer 12. , And the portion of the heat radiating plate 11 other than the bottom surface is covered to protect them.

次に、図２と図３を用いて、半導体装置の製造方法におけるワイヤボンディングについて説明する。図２は、フレーム部２ａ上の半導体素子５にワイヤボンディングする際のボンディングヘッド１３とフレーム部２ａの位置関係を示す断面模式図である。図３は、フレーム部３ｂ上の半導体素子７にワイヤボンディングする際のボンディングヘッド１３とフレーム部３ｂの位置関係を示す断面模式図である。 Next, wire bonding in a method for manufacturing a semiconductor device will be described with reference to FIGS. 2 and 3. FIG. 2 is a schematic cross-sectional view showing the positional relationship between the bonding head 13 and the frame portion 2a when wire bonding to the semiconductor element 5 on the frame portion 2a. FIG. 3 is a schematic cross-sectional view showing the positional relationship between the bonding head 13 and the frame portion 3b when wire bonding to the semiconductor element 7 on the frame portion 3b.

図２に示すように、ボンディングヘッド１３はボンディングヘッド１３の中心軸とフレーム部２ａの上面が平行となるように配置される。ボンディングヘッド１３に取り付けられたアルミナからなるキャピラリ１４の先端が半導体素子５のボンディングパッドなどのワイヤボンディング領域に対して垂直に接触することで、半導体素子５に対してワイヤボンディングが行われる。 As shown in FIG. 2, the bonding head 13 is arranged so that the central axis of the bonding head 13 and the upper surface of the frame portion 2a are parallel to each other. Wire bonding is performed on the semiconductor element 5 by vertically contacting the tip of the capillary 14 made of alumina attached to the bonding head 13 with respect to a wire bonding region such as a bonding pad of the semiconductor element 5.

次に、ボンディングヘッド１３は図２に示す位置から図３に示す位置へ円弧動作により移動する。そのため、ボンディングヘッド１３およびキャピラリ１４はフレーム部２ａの上面に対して傾いた状態となるが、フレーム部３ｂの上面はフレーム部２ａの上面に対して傾斜しており、図３に示すように、ボンディングヘッド１３はボンディングヘッド１３の中心軸とフレーム部３ｂの上面が平行となるように配置される。 Next, the bonding head 13 moves from the position shown in FIG. 2 to the position shown in FIG. 3 by an arc operation. Therefore, the bonding head 13 and the capillary 14 are tilted with respect to the upper surface of the frame portion 2a, but the upper surface of the frame portion 3b is tilted with respect to the upper surface of the frame portion 2a, and as shown in FIG. The bonding head 13 is arranged so that the central axis of the bonding head 13 and the upper surface of the frame portion 3b are parallel to each other.

キャピラリ１４の先端が半導体素子７のワイヤボンディング領域に対して垂直に接触することで、半導体素子７に対してワイヤボンディングが行われる。ワイヤボンディングの際、キャピラリ１４の先端が接合面であるワイヤボンディング領域に対して垂直に接触することで接合面に対して接合エネルギーが伝わりやすくなる。半導体素子６についても半導体素子７と同様の方法でワイヤボンディングが行われるため説明を省略する。 When the tip of the capillary 14 comes into contact with the wire bonding region of the semiconductor element 7 perpendicularly, wire bonding is performed to the semiconductor element 7. At the time of wire bonding, the tip of the capillary 14 comes into contact with the wire bonding region which is the bonding surface perpendicularly, so that the bonding energy is easily transmitted to the bonding surface. Since wire bonding is performed on the semiconductor element 6 in the same manner as in the semiconductor element 7, the description thereof will be omitted.

なお、第１フレームであるフレーム部２ａは第２リードフレーム２に形成され、第２フレームであるフレーム部３ａ，３ｂは第３リードフレーム３に形成されるとして説明を行ったが、フレーム部２ａおよびフレーム部３ａ，３ｂは共に第２リードフレーム２または第３リードフレーム３に形成されていてもよい。 Although it has been described that the frame portion 2a, which is the first frame, is formed in the second lead frame 2, and the frame portions 3a, 3b, which are the second frames, are formed in the third lead frame 3, the frame portion 2a And the frame portions 3a and 3b may both be formed in the second lead frame 2 or the third lead frame 3.

また、キャピラリ１４はアルミナにジルコニアを添加した材料により形成されていてもよい。さらに、キャピラリ１４の先端はポリッシュ仕上げ加工またはマット仕上げ加工されていてもよい。 Further, the capillary 14 may be formed of a material obtained by adding zirconia to alumina. Further, the tip of the capillary 14 may be polished or matte finished.

以上のように、実施の形態１に係る半導体装置は、半導体素子５，６，７と、半導体素子５が搭載されたフレーム部２ａと、半導体素子６，７が搭載されたフレーム部３ａ，３ｂとを有し、かつ、フレーム部２ａが第１高さに位置しフレーム部３ａ，３ｂが第１高さよりも低い第２高さに位置するリードフレームとを備え、フレーム部３ａ，３ｂの上面は、フレーム部２ａの上面に対して傾斜する。 As described above, the semiconductor device according to the first embodiment includes the semiconductor elements 5, 6 and 7, the frame portions 2a on which the semiconductor elements 5 are mounted, and the frame portions 3a and 3b on which the semiconductor elements 6 and 7 are mounted. The frame portions 2a are located at the first height, and the frame portions 3a and 3b are provided with a lead frame located at a second height lower than the first height, and the upper surfaces of the frame portions 3a and 3b are provided. Is inclined with respect to the upper surface of the frame portion 2a.

また、実施の形態１に係る半導体装置の製造方法は、ボンディングヘッド１３の中心軸とフレーム部２ａの上面が平行となるようにボンディングヘッド１３を配置し、ボンディングヘッド１３に取り付けられたキャピラリ１４の先端を半導体素子５のワイヤボンディング領域に対して垂直に接触させる工程（ａ）と、ボンディングヘッド１３の中心軸とフレーム部３ａ，３ｂの上面が平行となるようにボンディングヘッド１３を配置し、キャピラリ１４の先端を半導体素子６，７のワイヤボンディング領域に対して垂直に接触させる工程（ｂ）とを備え、ボンディングヘッド１３における工程（ａ）から工程（ｂ）への高さ分の移動は円弧動作により行われる。 Further, in the method for manufacturing a semiconductor device according to the first embodiment, the bonding head 13 is arranged so that the central axis of the bonding head 13 and the upper surface of the frame portion 2a are parallel to each other, and the capillary 14 is attached to the bonding head 13. The step (a) in which the tip is brought into vertical contact with the wire bonding region of the semiconductor element 5 and the bonding head 13 are arranged so that the central axis of the bonding head 13 and the upper surfaces of the frame portions 3a and 3b are parallel to each other. The step (b) is provided in which the tip of the 14 is brought into contact with the wire bonding regions of the semiconductor elements 6 and 7 perpendicularly, and the movement of the height from the step (a) to the step (b) in the bonding head 13 is an arc. It is done by operation.

したがって、キャピラリ１４の先端に対する半導体素子６，７の接合面への片当たりを抑制することができる。これにより、半導体素子６，７の接合面に対して接合エネルギーが伝わりやすくなることから、半導体素子６，７とワイヤ９との接合性を向上させることができる。以上より、半導体装置の耐久性の向上と歩留りの向上を図ることが可能となる。 Therefore, it is possible to suppress one-sided contact of the semiconductor elements 6 and 7 with respect to the tip of the capillary 14. As a result, the bonding energy is easily transmitted to the bonding surfaces of the semiconductor elements 6 and 7, so that the bondability between the semiconductor elements 6 and 7 and the wire 9 can be improved. From the above, it is possible to improve the durability and the yield of the semiconductor device.

＜実施の形態２＞
次に、実施の形態２に係る半導体装置について説明する。図４は、実施の形態１に係る半導体装置であって、半導体素子７の位置ずれと半導体素子７の表面にはんだ付着が生じた状態におけるフレーム部３ｂおよびその周辺の断面模式図である。図５は、実施の形態２に係る半導体装置が備えるフレーム部３ｂおよびその周辺の断面模式図である。なお、実施の形態２において、実施の形態１で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 2>
Next, the semiconductor device according to the second embodiment will be described. FIG. 4 is a schematic cross-sectional view of the frame portion 3b and its periphery in a state in which the semiconductor device 7 is displaced and the surface of the semiconductor element 7 is soldered, in the semiconductor device according to the first embodiment. FIG. 5 is a schematic cross-sectional view of the frame portion 3b included in the semiconductor device according to the second embodiment and its surroundings. In the second embodiment, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

最初に、実施の形態１に係る半導体装置において発生し得る問題点について簡単に説明する。図４に示すように、半導体素子７が搭載されるフレーム部３ｂの上面が傾斜面であるため、フレーム部３ｂにおけるフレーム部２ａとは反対側の端部に隣接する位置に段差３ｅが形成されている。そのため、半導体素子７のダイボンディング後に、はんだ流れが発生することで半導体素子７に位置ずれが発生したり、さらには位置ずれに伴い段差３ｅからはみ出たはんだ４ａが半導体素子７の表面に付着する可能性がある。実施の形態２はこのような課題を解決するものである。 First, problems that may occur in the semiconductor device according to the first embodiment will be briefly described. As shown in FIG. 4, since the upper surface of the frame portion 3b on which the semiconductor element 7 is mounted is an inclined surface, a step 3e is formed at a position adjacent to the end portion of the frame portion 3b opposite to the frame portion 2a. ing. Therefore, after the die bonding of the semiconductor element 7, a solder flow occurs, which causes the semiconductor element 7 to be misaligned, and further, the solder 4a protruding from the step 3e adheres to the surface of the semiconductor element 7 due to the misalignment. there is a possibility. The second embodiment solves such a problem.

図５に示すように、実施の形態２では、フレーム部３ｂにおけるフレーム部２ａとは反対側の端部に、フレーム部３ｂにおけるフレーム部２ａ側の上面よりも上方に突出する段差３ｅが形成されている。段差３ｅの上端部には、半導体素子７側に突出する突起部１５が形成されている。突起部１５の先端が半導体素子７におけるフレーム部２ａとは反対側の端に当接することで、突起部１５は半導体素子７を支持している。 As shown in FIG. 5, in the second embodiment, a step 3e is formed at the end of the frame portion 3b on the opposite side of the frame portion 2a so as to project upward from the upper surface of the frame portion 3b on the frame portion 2a side. ing. A protrusion 15 protruding toward the semiconductor element 7 is formed at the upper end of the step 3e. The protrusion 15 supports the semiconductor element 7 by abutting the tip of the protrusion 15 on the end of the semiconductor element 7 opposite to the frame portion 2a.

以上のように、実施の形態２に係る半導体装置では、フレーム部３ｂの上面は、フレーム部２ａ側からフレーム部２ａとは反対側に渡って上方から下方に傾斜し、フレーム部３ｂにおけるフレーム部２ａとは反対側の端部に隣接する位置に、フレーム部２ａ側の上面よりも上方に突出する段差３ｅと、段差３ｅの上端部から半導体素子７側に突出し半導体素子７を支持する突起部１５が形成されている。 As described above, in the semiconductor device according to the second embodiment, the upper surface of the frame portion 3b is inclined from the upper side to the lower side from the frame portion 2a side to the side opposite to the frame portion 2a, and the frame portion in the frame portion 3b. A step 3e projecting upward from the upper surface on the frame portion 2a side and a protrusion projecting from the upper end of the step 3e toward the semiconductor element 7 to support the semiconductor element 7 at a position adjacent to the end on the opposite side of 2a. 15 is formed.

したがって、突起部１５により、はんだ流れが発生することで半導体素子７に位置ずれが発生したり、半導体素子７の表面にはんだ４ａが付着することを抑制できる。 Therefore, it is possible to prevent the semiconductor element 7 from being displaced due to the occurrence of the solder flow by the protrusions 15 and to prevent the solder 4a from adhering to the surface of the semiconductor element 7.

実施の形態２では、フレーム部３ｂに突起部１５が形成された場合について説明を行ったが、フレーム部３ａにも突起部１５が形成されていてもよい。この場合、上記と同様の効果が得られる。 In the second embodiment, the case where the protrusion 15 is formed on the frame portion 3b has been described, but the protrusion 15 may also be formed on the frame portion 3a. In this case, the same effect as described above can be obtained.

＜実施の形態３＞
次に、実施の形態３に係る半導体装置について説明する。図６は、実施の形態２に係る半導体装置が備える半導体素子７の表面へのはんだ這い上がりが発生した場合におけるフレーム部３ｂおよびその周辺の断面模式図である。図７は、実施の形態３に係る半導体装置が備えるフレーム部３ｂおよびその周辺の断面模式図である。なお、実施の形態３において、実施の形態１，２で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 3>
Next, the semiconductor device according to the third embodiment will be described. FIG. 6 is a schematic cross-sectional view of the frame portion 3b and its surroundings when solder creeps up to the surface of the semiconductor element 7 included in the semiconductor device according to the second embodiment. FIG. 7 is a schematic cross-sectional view of the frame portion 3b included in the semiconductor device according to the third embodiment and its surroundings. In the third embodiment, the same components as those described in the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted.

最初に、実施の形態２に係る半導体装置において発生し得る問題点について簡単に説明する。図６に示すように、フレーム部３ｂにおけるフレーム部２ａとは反対側の端部に段差３ｅと突起部１５が形成されたため、半導体素子７のダイボンディング後に段差３ｅと突起部１５を伝ってはんだ４ａが半導体素子７の表面側へ這い上がる可能性がある。実施の形態３はこのような課題を解決するものである。 First, problems that may occur in the semiconductor device according to the second embodiment will be briefly described. As shown in FIG. 6, since the step 3e and the protrusion 15 are formed on the end of the frame 3b opposite to the frame 2a, the step 3e and the protrusion 15 are passed through the solder after die bonding of the semiconductor element 7. There is a possibility that 4a crawls up to the surface side of the semiconductor element 7. The third embodiment solves such a problem.

図７に示すように、実施の形態３では、フレーム部３ｂにおける段差３ｅの基端部の周辺にＶ字状の溝１６が形成されている。溝１６はフレーム部３ｂにおける突起部１５の下側に形成され、溝１６の開口側は溝１６の奥側よりも広くなっている。 As shown in FIG. 7, in the third embodiment, a V-shaped groove 16 is formed around the base end portion of the step 3e in the frame portion 3b. The groove 16 is formed on the lower side of the protrusion 15 in the frame portion 3b, and the opening side of the groove 16 is wider than the inner side of the groove 16.

以上のように、実施の形態３に係る半導体装置では、フレーム部３ｂにおける段差３ｅの基端部の周辺にＶ字状の溝１６が形成されたため、溝１６が半導体素子７を接合する際にはみ出したはんだ４ａのはんだ溜まりとして機能する。これにより、半導体素子７のダイボンディング後に段差３ｅと突起部１５を伝ってはんだ４ａが半導体素子７の表面側へ這い上がることを抑制できる。 As described above, in the semiconductor device according to the third embodiment, since the V-shaped groove 16 is formed around the base end portion of the step 3e in the frame portion 3b, when the groove 16 joins the semiconductor element 7. It functions as a solder pool of the protruding solder 4a. As a result, it is possible to prevent the solder 4a from creeping up to the surface side of the semiconductor element 7 along the step 3e and the protrusion 15 after die bonding of the semiconductor element 7.

実施の形態３では、フレーム部３ｂに溝１６が形成された場合について説明を行ったが、フレーム部３ａにも突起部１５と共に溝１６が形成されていてもよい。この場合、上記と同様の効果が得られる。 In the third embodiment, the case where the groove 16 is formed in the frame portion 3b has been described, but the groove 16 may also be formed in the frame portion 3a together with the protrusion portion 15. In this case, the same effect as described above can be obtained.

＜実施の形態４＞
次に、実施の形態４に係る半導体装置について説明する。図８は、実施の形態３に係る半導体装置においてはんだ流れが発生した場合におけるフレーム部３ｂおよびその周辺の断面模式図である。図９は、実施の形態４に係る半導体装置が備えるフレーム部３ｂおよびその周辺の断面模式図である。なお、実施の形態４において、実施の形態１〜３で説明したものと同一の構成要素については同一符号を付して説明は省略する。 <Embodiment 4>
Next, the semiconductor device according to the fourth embodiment will be described. FIG. 8 is a schematic cross-sectional view of the frame portion 3b and its periphery when a solder flow occurs in the semiconductor device according to the third embodiment. FIG. 9 is a schematic cross-sectional view of the frame portion 3b included in the semiconductor device according to the fourth embodiment and its surroundings. In the fourth embodiment, the same components as those described in the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.

最初に、実施の形態３に係る半導体装置において発生し得る問題点について簡単に説明する。図８に示すように、フレーム部３ｂにおける突起部１５の基端部の周辺にＶ字状の溝１６が形成されたため、半導体素子７を接合する際にはみ出したはんだ４ａが溝１６に流れることにより、半導体素子７の下面にあるはんだ４が不足する可能性がある。実施の形態４はこのような課題を解決するものである。 First, problems that may occur in the semiconductor device according to the third embodiment will be briefly described. As shown in FIG. 8, since the V-shaped groove 16 is formed around the base end portion of the protrusion 15 in the frame portion 3b, the solder 4a protruding when joining the semiconductor element 7 flows into the groove 16. As a result, the solder 4 on the lower surface of the semiconductor element 7 may be insufficient. The fourth embodiment solves such a problem.

図９に示すように、実施の形態４では、フレーム部３ｂの上面における半導体素子７が搭載される搭載部３ｆに、半導体素子７の平面視輪郭よりも０．１ｍｍ以上０．３ｍｍ以下大きいサイズを有するＡｇめっき層１７が形成されている。Ａｇめっき層１７は、フレーム部３ｂの上面で材質および表面性状を変化させることではんだの濡れ性を低下させる目的で形成されている。Ａｇめっき層１７の上面にはんだ４を介して半導体素子７が接合される。 As shown in FIG. 9, in the fourth embodiment, the mounting portion 3f on which the semiconductor element 7 is mounted on the upper surface of the frame portion 3b has a size 0.1 mm or more and 0.3 mm or less larger than the plan view contour of the semiconductor element 7. The Ag plating layer 17 having the above is formed. The Ag plating layer 17 is formed on the upper surface of the frame portion 3b for the purpose of reducing the wettability of the solder by changing the material and the surface texture. The semiconductor element 7 is bonded to the upper surface of the Ag plating layer 17 via the solder 4.

以上のように、実施の形態４に係る半導体装置では、フレーム部３ｂの上面における半導体素子７が搭載される搭載部３ｆに、半導体素子７の平面視輪郭よりも０．１ｍｍ以上０．３ｍｍ以下大きいサイズを有するＡｇめっき層１７が形成されている。 As described above, in the semiconductor device according to the fourth embodiment, the mounting portion 3f on which the semiconductor element 7 is mounted on the upper surface of the frame portion 3b is 0.1 mm or more and 0.3 mm or less from the plan view contour of the semiconductor element 7. An Ag plating layer 17 having a large size is formed.

したがって、フレーム部３ｂの上面におけるはんだ４の濡れ性を低下させることで、はんだ流れにより半導体素子７の下面にあるはんだ４が不足することを、半導体素子７の位置ずれと共に抑制できる。 Therefore, by reducing the wettability of the solder 4 on the upper surface of the frame portion 3b, it is possible to suppress the shortage of the solder 4 on the lower surface of the semiconductor element 7 due to the solder flow together with the misalignment of the semiconductor element 7.

実施の形態４では、フレーム部３ｂにＡｇめっき層１７が形成された場合について説明を行ったが、フレーム部３ａにも突起部１５および溝１６と共にＡｇめっき層１７が形成されていてもよい。この場合、上記と同様の効果が得られる。 In the fourth embodiment, the case where the Ag plating layer 17 is formed on the frame portion 3b has been described, but the Ag plating layer 17 may also be formed on the frame portion 3a together with the protrusions 15 and the grooves 16. In this case, the same effect as described above can be obtained.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

１ 第１リードフレーム、２ 第２リードフレーム、２ａ フレーム部、３ 第３リードフレーム、３ａ，３ｂ フレーム部、３ｆ 搭載部、５，６，７ 半導体素子、１３ ボンディングヘッド、１４ キャピラリ、１５ 突起部、１６ 溝、１７ Ａｇめっき層。 1 1st lead frame, 2nd lead frame, 2a frame part, 3rd lead frame, 3a, 3b frame part, 3f mounting part, 5, 6, 7 semiconductor element, 13 bonding head, 14 capillary, 15 protrusion , 16 grooves, 17 Ag plating layer.

Claims (5)

第１半導体素子および第２半導体素子と、
前記第１半導体素子が搭載された第１フレーム部と、前記第２半導体素子が搭載された第２フレーム部とを有し、かつ、前記第１フレーム部が第１高さに位置し前記第２フレーム部が前記第１高さよりも低い第２高さに位置するリードフレームと、を備え、
前記第２フレーム部の上面は、前記第１フレーム部の上面に対して傾斜する、半導体装置。 The first semiconductor element and the second semiconductor element,
The first frame portion on which the first semiconductor element is mounted and the second frame portion on which the second semiconductor element is mounted are provided, and the first frame portion is located at the first height. A lead frame whose two frame portions are located at a second height lower than the first height is provided.
A semiconductor device in which the upper surface of the second frame portion is inclined with respect to the upper surface of the first frame portion. 前記第２フレーム部の前記上面は、前記第１フレーム部側から前記第１フレーム部とは反対側に渡って上方から下方に傾斜し、
前記第２フレーム部における前記第１フレーム部とは反対側の端部に隣接する位置に、前記第１フレーム部側の上面よりも上方に突出する段差と、
前記段差の上端部から前記第２半導体素子側に突出し前記第２半導体素子を支持する突起部が形成された、請求項１に記載の半導体装置。 The upper surface of the second frame portion is inclined from the upper surface to the lower surface from the first frame portion side to the side opposite to the first frame portion.
At a position adjacent to the end of the second frame portion opposite to the first frame portion, a step protruding upward from the upper surface on the first frame portion side, and
The semiconductor device according to claim 1, wherein a protrusion is formed so as to project from the upper end of the step toward the second semiconductor element and support the second semiconductor element. 前記第２フレーム部における前記段差の基端部の周辺にＶ字状の溝が形成された、請求項２に記載の半導体装置。 The semiconductor device according to claim 2, wherein a V-shaped groove is formed around the base end portion of the step in the second frame portion. 前記第２フレーム部の前記上面における前記第２半導体素子が搭載される搭載部に、前記第２半導体素子の平面視輪郭よりも０．１ｍｍ以上０．３ｍｍ以下大きいサイズを有するＡｇめっき層が形成された、請求項１から請求項３のいずれか１つに記載の半導体装置。 An Ag plating layer having a size 0.1 mm or more and 0.3 mm or less larger than the plan view contour of the second semiconductor element is formed on the mounting portion on the upper surface of the second frame portion on which the second semiconductor element is mounted. The semiconductor device according to any one of claims 1 to 3. 請求項１から請求項４のいずれか１つに記載の半導体装置を製造する半導体装置の製造方法であって、
（ａ）ボンディングヘッドの中心軸と前記第１フレーム部の上面が平行となるように前記ボンディングヘッドを配置し、前記ボンディングヘッドに取り付けられたキャピラリの先端を前記第１半導体素子のワイヤボンディング領域に対して垂直に接触させる工程と、
（ｂ）前記ボンディングヘッドの中心軸と前記第２フレーム部の上面が平行となるように前記ボンディングヘッドを配置し、前記キャピラリの先端を前記第２半導体素子のワイヤボンディング領域に対して垂直に接触させる工程と、を備え、
前記ボンディングヘッドにおける前記工程（ａ）から前記工程（ｂ）への高さ分の移動は円弧動作により行われる、半導体装置の製造方法。 A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is manufactured.
(A) The bonding head is arranged so that the central axis of the bonding head and the upper surface of the first frame portion are parallel to each other, and the tip of the capillary attached to the bonding head is placed in the wire bonding region of the first semiconductor element. The process of making vertical contact with each other
(B) The bonding head is arranged so that the central axis of the bonding head is parallel to the upper surface of the second frame portion, and the tip of the capillary is in contact with the wire bonding region of the second semiconductor element perpendicularly. With the process of making
A method for manufacturing a semiconductor device, wherein the bonding head is moved by a height from the step (a) to the step (b) by an arc operation.
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