JP2009141068A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for reducing the warp, especially the warp accompanied by twist, of a semiconductor package without increasing the number of parts. <P>SOLUTION: The semiconductor device is provided with a wiring board 102, a plurality of semiconductor chips 103 laminated on the upper surface of the wiring board 102, a plurality of adhesion members 106, 107 and 108 for attaching the semiconductor chips with each other or the semiconductor chip and the wiring board, and a sealing resin 113 for covering them. The width of the first layer semiconductor chip of the top layer is smaller than the width of a second layer semiconductor chip to which the first layer semiconductor chip is attached. The upper surface of the second layer semiconductor chip has an angle with the upper surface of the wiring board 102, and the center of the first layer semiconductor chip is positioned by being shifted in the decreasing direction of thickness from the upper surface of the second layer semiconductor chip to the upper surface of the wiring board 102 relative to the center of the second layer semiconductor chip. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device of a semiconductor chip stacked type having a structure in which semiconductor chips are stacked. More specifically, the present invention relates to a semiconductor device by reducing an uneven distribution of a sealing resin and a semiconductor chip in a resin sealing region. The present invention relates to a semiconductor device that reduces warping of a package.

  In recent years, semiconductor packages have been highly integrated in order to cope with higher functionality of electronic devices. Accordingly, a semiconductor chip stacked type semiconductor package in which a plurality of semiconductor chips are stacked is proposed.

  FIG. 9 is a cross-sectional view showing a conventional semiconductor chip stacked semiconductor package 800. As shown in FIG. 9, the conventional semiconductor package 800 is a BGA (Ball Grid Array) type. The semiconductor package 800 includes a plurality of solder balls 801, a wiring board 802, semiconductor chips 803 to 805, adhesive members 806, 807 and 808, bonding wires 809 to 812, and a sealing resin 813. As indicated by the black arrows in FIG. 9, the direction toward the upper layer of the semiconductor chip is the upward direction, and the direction opposite to the upward direction is the downward direction. In addition, the directions indicated by white arrows in FIG. 9 are the right direction and the left direction. A broken line X is a straight line extending in the vertical direction and passing through the center of the semiconductor package 800.

  A plurality of solder balls 801 are arranged on a lower surface (hereinafter referred to as a lower surface) of the wiring board 802. A semiconductor chip 803 is bonded to an upper surface of the wiring substrate 802 (hereinafter referred to as an upper surface) via an adhesive member 806. A semiconductor chip 804 is bonded to the upper surface of the semiconductor chip 803 via an adhesive member 807. A semiconductor chip 805 is bonded to the upper surface of the semiconductor chip 804 via an adhesive member 808. The wiring board 802 and the semiconductor chip 803 are connected by bonding wires 809. The semiconductor chip 803 and the semiconductor chip 804 are connected by bonding wires 810 and 811. The wiring board 802 and the semiconductor chip 805 are connected by a bonding wire 812. In addition, the quantity and connection of a bonding wire are examples, and another quantity and connection may be sufficient. The uppermost semiconductor chip 805 is smaller than the bonded semiconductor chip 804. More specifically, the width A of the uppermost semiconductor chip 805 is smaller than the width B of the semiconductor chip 804 to which the semiconductor chip 805 is bonded. FIG. 9 shows a case where the width A is about a quarter of the width B as an example. The sealing resin 813 is formed on the upper surface of the wiring substrate 802 so as to integrally cover the semiconductor chips 803 to 805, the adhesive members 806 to 808, and the bonding wires 809 to 812.

  Here, as the width A of the uppermost semiconductor chip 805 becomes smaller than the width B of the semiconductor chip 804 to which the semiconductor chip 805 is bonded, the volume of the sealing resin 813 increases. Further, internal stress is generated in the sealing resin 813. As a result, as the volume of the sealing resin 813 increases, the force acting inside the sealing resin 813 increases. As a result, there is a problem that warpage of the semiconductor package 800 is increased.

  In addition, in order to shorten the length of the bonding wire 812 connected to the semiconductor chip 805, the uppermost semiconductor chip 805 needs to be shifted from the center (broken line X) of the semiconductor package 800 (FIG. 10). See). FIG. 10 is a cross-sectional view showing a conventional semiconductor package 820 in which the installation position of the uppermost semiconductor chip 805 is shifted from the center of the semiconductor package with respect to the semiconductor package 800 shown in FIG. In the semiconductor package 820, similarly to the semiconductor package 800, the force acting inside the sealing resin 813 increases as the volume of the sealing resin 813 increases, so that the warpage increases. In addition to this, in the semiconductor package 820, as shown in FIG. 10, the resin distribution inside the sealing resin 813 lacks symmetry greatly between the right side and the left side of the broken line X when the right side and the left side of the broken line X are compared. . That is, an uneven resin distribution in the left-right direction occurs inside the sealing resin 813. As a result, in the semiconductor package 820, unlike the semiconductor package 800, the force acting on the inside of the sealing resin 813 is biased, and thus a warp accompanied by a twist occurs. As a result, there is a problem that it is difficult to mount the semiconductor package 820 on a mounting substrate (not shown).

  A technique for solving the above-described problem is described in Patent Document 1. FIG. 11 is a cross-sectional view for explaining a conventional semiconductor package 850 described in Patent Document 1. In FIG. The semiconductor package 850 includes a dummy semiconductor chip 851 that is a dummy with respect to the semiconductor package 820 (see FIG. 10). Note that in the semiconductor package 850, the same components as those of the semiconductor package 820 are denoted by the same reference numerals, and the description thereof is omitted. As shown in FIG. 11, the dummy semiconductor chip 851 is installed in the uppermost layer, suppresses an increase in the volume of the sealing resin 813, and eliminates the uneven resin distribution in the horizontal direction of the broken line X inside the sealing resin 813. . As a result, the semiconductor package 850 can reduce warping accompanied by twisting.

  The warping of the BGA type semiconductor package has been described above. Hereinafter, warping of the lead frame type semiconductor package will be described. FIG. 12 is a cross-sectional view for explaining a conventional semiconductor chip stacked type semiconductor package 900. As shown in FIG. 12, the conventional semiconductor package 900 is a lead frame type. The semiconductor package 900 includes a lead frame 901, semiconductor chips 902 and 903, adhesive members 904 and 905, bonding wires 906 to 908, and a sealing resin 909. As shown by the black arrows in FIG. 12, the direction toward the upper layer of the semiconductor chip is the upward direction, and the direction opposite to the upward direction is the downward direction. In addition, the directions indicated by white arrows in FIG. 12 are the right direction and the left direction. A broken line X is a straight line extending in the vertical direction and passing through the center of the semiconductor package 900.

  A semiconductor chip 902 is bonded to the upper surface of the lead frame 901 via an adhesive member 904. A semiconductor chip 903 is bonded to the upper surface of the semiconductor chip 902 via an adhesive member 905. The lead frame 901 and the semiconductor chip 902 are connected by bonding wires 906 and 907. The lead frame 901 and the semiconductor chip 903 are connected by a bonding wire 908. In addition, the quantity and connection of a bonding wire are examples, and another quantity and connection may be sufficient. The uppermost semiconductor chip 903 is smaller than the bonded semiconductor chip 906. More specifically, the width A of the uppermost semiconductor chip 903 is smaller than the width B of the semiconductor chip 906 to which the semiconductor chip 903 is bonded. FIG. 12 shows a case where the width A is about one-fourth of the width B as an example. The sealing resin 909 is formed on the upper and lower surfaces of the lead frame 901 so as to integrally cover the semiconductor chips 902 and 903, the adhesive members 904 and 905, and the bonding wires 906 to 908.

  Here, the following three problems occur in the semiconductor package 900 of the lead frame type. The first is a problem of warpage caused by an increase in the amount (volume) of the sealing resin 909 due to the width A being smaller than the width B, as in the semiconductor package 820 of FIG. The second is a problem of warping accompanied by twisting caused by the deviation of the resin distribution in the horizontal direction of the broken line X in the sealing resin 909 as in the semiconductor package 820 of FIG. The third is a problem of warpage caused by the uneven resin distribution in the vertical direction in the sealing resin 909. More specifically, the portion of the sealing resin 909 formed on the upper surface of the lead frame 901 and the portion formed on the lower surface of the lead frame 901 are warped due to a deviation in resin distribution. It is a problem.

As a technique for solving the above third problem, there is a technique described in Patent Document 2. The technique of Patent Document 2 is a technique for reducing the bias in the resin distribution in the vertical direction by installing a dummy semiconductor chip on the lower surface of the lead frame. FIG. 13 is a cross-sectional view showing a conventional semiconductor package 950 in which the technique of Patent Document 2 is applied to the semiconductor package 900. The semiconductor package 950 includes dummy semiconductor chips 910 and 911 that are dummy with respect to the semiconductor package 900 (see FIG. 12). In the semiconductor package 950, the same reference numerals are given to the same components as those of the semiconductor package 900, and the description thereof is omitted. As shown in FIG. 13, the dummy semiconductor chip 910 is installed on the lower surface of the lead frame 901. The dummy semiconductor chip 911 is installed on the lower surface of the dummy semiconductor chip 910. As a result, the conventional semiconductor package 950 can solve the problem of warping (third problem) caused by the uneven resin distribution in the vertical direction in the sealing resin 909.
JP 2007-165454 A JP-A-2-28353

  However, the conventional semiconductor package described above has the following problems.

  In the conventional semiconductor package 850 (see FIG. 11), since it is necessary to install the dummy semiconductor chip 851, the number of parts increases and the manufacturing cost increases. Incidentally, stress concentrates on the upper surface of the semiconductor chip 804 in the vicinity of the portion where the edges of the semiconductor chip 805 and the dummy semiconductor chip 851 are located. For this reason, in the semiconductor package 850, when the dummy semiconductor chip 851 is installed, a portion where stress is concentrated on the upper surface of the semiconductor chip 804 increases. As a result, in the semiconductor package 850, the risk of destruction of the semiconductor chip 804 increases.

  Since the conventional semiconductor package 950 (see FIG. 13) needs to be provided with dummy semiconductor chips 910 and 911, the number of parts increases and the manufacturing cost increases. 13 is applied to the semiconductor package 950 described with reference to the semiconductor package 850 illustrated in FIG. 11 (technology for installing the dummy semiconductor chip 851 in the uppermost layer), the semiconductor package 900 described above. The first and second problems can be solved. However, in this case, a dummy semiconductor chip 851 is further installed, and the manufacturing cost further increases.

  Therefore, an object of the present invention is to reduce the volume of the sealing resin without increasing the number of components using a dummy semiconductor chip, and to reduce the distribution of the sealing resin and the semiconductor chip in the resin sealing region. It is an object of the present invention to provide a semiconductor device that reduces the warpage of a semiconductor package, in particular, warpage accompanied by twisting.

  The present invention is directed to a semiconductor chip stacked type semiconductor device. In order to achieve the above object, a semiconductor device of the present invention includes a wiring board, a plurality of semiconductor chips stacked on the upper surface of the wiring board, and a plurality of semiconductor chips bonded to each other or between the semiconductor chip and the wiring board. And a sealing resin that is formed on the upper surface of the wiring substrate and covers the plurality of semiconductor chips and the plurality of adhesive members, and the width of the first layer semiconductor chip of the uppermost layer among the plurality of semiconductor chips is: The width of the second layer semiconductor chip is smaller than the width of the second layer semiconductor chip to which the first layer semiconductor chip is bonded, the upper surface of the second layer semiconductor chip has an angle with the upper surface of the wiring substrate, and the center of the first layer semiconductor chip is the second The thickness from the upper surface of the second layer semiconductor chip to the upper surface of the wiring board is shifted with respect to the center of the layer semiconductor chip in a direction of decreasing thickness.

  Preferably, at least one upper surface and lower surface of the plurality of semiconductor chips excluding the first layer semiconductor chip are not parallel.

  Further, at least one upper surface and lower surface of the plurality of adhesive members excluding the adhesive member that bonds the first layer semiconductor chip and the second layer semiconductor chip may be not parallel.

  In addition, a girder made of a material harder than the adhesive member before curing may be inserted into at least one of the adhesive members whose upper surface and lower surface are not parallel.

  In order to achieve the above object, a semiconductor device of the present invention includes a lead frame composed of a lead portion and a die pad portion, a plurality of semiconductor chips stacked on the upper surface of the die pad portion, A plurality of adhesive members for bonding the semiconductor chip and the die pad portion; and a sealing resin that covers a part of the lead portion, the die pad portion, the plurality of semiconductor chips, and the plurality of adhesive members. The width of the upper first layer semiconductor chip is smaller than the width of the second layer semiconductor chip to which the first layer semiconductor chip is bonded, and the upper surface of the second layer semiconductor chip has an angle with the lower surface of the sealing resin. The center of the first layer semiconductor chip is shifted from the center of the second layer semiconductor chip in a direction in which the thickness from the upper surface of the second layer semiconductor chip to the lower surface of the sealing resin decreases.

  Preferably, at least one upper surface and lower surface of the plurality of semiconductor chips excluding the first layer semiconductor chip are not parallel.

  Further, at least one upper surface and lower surface of the plurality of adhesive members excluding the adhesive member that bonds the first layer semiconductor chip and the second layer semiconductor chip may be not parallel.

  In addition, a girder made of a material harder than the adhesive member before curing may be inserted into at least one of the adhesive members whose upper surface and lower surface are not parallel.

  In addition, the upper surface and the lower surface of the die pad portion may not be parallel.

  In addition, the plurality of semiconductor chips excluding the first layer semiconductor chip, the plurality of adhesive members excluding the adhesive member that bonds the first layer semiconductor chip and the second layer semiconductor chip, and the upper surface and the lower surface of the die pad portion are parallel to each other. It is good.

  Preferably, the sealing resin amount formed above the laminated body composed of the die pad portion, the plurality of semiconductor chips, and the plurality of adhesive members is equal to the sealing resin amount formed below. Laminate the stacks.

  According to the above-described invention, the volume of the sealing resin is reduced without increasing the number of parts using the dummy semiconductor chip, and the uneven distribution of the sealing resin and the semiconductor chip in the resin sealing region is reduced. Accordingly, it is possible to provide a semiconductor device capable of reducing the warpage of the semiconductor package, in particular, the warp accompanied by the twist.

(First embodiment)
FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor package 100 according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor package 100 is a BGA type. The semiconductor package 100 includes a plurality of solder balls 101, a wiring substrate 102, semiconductor chips 103 to 105, adhesive members 106 to 108, bonding wires 109 to 112, and a sealing resin 113. As indicated by the black arrows in FIG. 1, the direction toward the upper layer of the semiconductor chip is the upward direction, and the direction opposite to the upward direction is the downward direction. In addition, the directions indicated by the white arrows in FIG. 1 are the right direction and the left direction. The broken line X is a straight line extending in the vertical direction and passing through the center of the semiconductor package 100.

  A plurality of solder balls 101 are arranged on a lower surface (hereinafter referred to as a lower surface) of the wiring board 102. A semiconductor chip 103 is bonded to an upper surface (hereinafter referred to as an upper surface) of the wiring substrate 102 via an adhesive member 106. A semiconductor chip 104 is bonded to the upper surface of the semiconductor chip 103 via an adhesive member 107. A semiconductor chip 105 is bonded to the upper surface of the semiconductor chip 104 via an adhesive member 108. The wiring board 102 and the semiconductor chip 103 are connected by a bonding wire 109. The semiconductor chip 103 and the semiconductor chip 104 are connected by bonding wires 110 and 111. The wiring board 102 and the semiconductor chip 105 are connected by bonding wires 112. In addition, the quantity and connection of a bonding wire are examples, and another quantity and connection may be sufficient.

  The uppermost semiconductor chip 105 is smaller than the bonded semiconductor chip 104. More specifically, the width A of the uppermost semiconductor chip 105 is smaller than the width B of the semiconductor chip 104 to which the semiconductor chip 105 is bonded. FIG. 1 shows a case where the width A is about one-fourth of the width B as an example. Further, in order to shorten the length of the bonding wire 112 connected to the semiconductor chip 105, the uppermost semiconductor chip 105 is located on the left side from the center of the semiconductor chip 104 (in FIG. 1, the center coincides with the broken line X). It is installed in a staggered manner. More specifically, when a line passing through the center of the semiconductor chip 105 and parallel to the broken line X is a broken line Y, the broken line Y is shifted from the broken line X to the left.

  The lower surface and the upper surface of the semiconductor chip 104 are not parallel but have an angle. Thus, as can be seen from FIG. 1, the volume of the semiconductor chip 104 is small on the left side of the broken line X where the semiconductor chip 105 is installed, and on the right side of the broken line X where the semiconductor chip 105 is not installed. Since the upper surface and the lower surface of the semiconductor chip 103 and the adhesive member 106 are both parallel, the upper surface of the wiring substrate 102 and the upper surface of the semiconductor chip 104 are not parallel but have an angle.

  Similar to the lower surface and the upper surface of the semiconductor chip 104, the lower surface and the upper surface of the uppermost semiconductor chip 105 are not parallel but have an angle. As a result, as shown in FIG. 1, the upper surface of the semiconductor chip 105 is substantially parallel to the upper surface of the wiring substrate 102. Note that the upper surface and the lower surface of the adhesive member 108 are parallel to each other.

  The sealing resin 113 is formed on the upper surface of the wiring substrate 102 so as to integrally cover the semiconductor chips 103 to 105, the adhesive members 106 to 108, and the bonding wires 109 to 112.

  Here, an example of a processing method in which the lower surface and the upper surface of the semiconductor chips 104 and 105 are not parallel will be briefly described. First, the semiconductor wafer is diced (cut) in only one direction, ie, a vertical direction or a horizontal direction, to produce a belt-like substrate in which semiconductor chips are arranged in a line. After that, the lower surface of the band-shaped substrate is polished so as to have an angle with the upper surface of the band-shaped substrate. Thereafter, the belt-like substrate is cut to produce semiconductor chips having the same shape. Note that after the semiconductor chip is cut out by dicing the semiconductor wafer in the vertical and horizontal directions, the lower surface of each semiconductor chip may be polished so as to have an angle with the upper surface.

  With the configuration described above, the semiconductor package 100 according to the first embodiment is sealed as shown in FIG. 1 when comparing the right side and the left side from the center (broken line X) of the semiconductor package 100. The uneven distribution of the resin 113 can be reduced. As a result, the semiconductor package 100 according to the first embodiment reduces the volume of the sealing resin and warps the semiconductor package, in particular, twists, similarly to the conventional semiconductor package 850 (see FIG. 11). It is possible to reduce the warp accompanied by. Furthermore, unlike the conventional semiconductor package 850, the semiconductor package 100 according to the first embodiment can avoid an increase in the number of components since no dummy semiconductor chip is installed, and an increase in stress concentration points on the upper surface of the semiconductor chip. Can be avoided.

  The uppermost semiconductor chip 105 may be in the form of a normal semiconductor chip whose bottom surface and top surface are parallel. However, when the lower surface and the upper surface of the uppermost semiconductor chip 105 are provided with an angle, the upper surface of the semiconductor chip 105 and the upper surface of the wiring substrate 102 are substantially parallel (see FIG. 1). The uneven distribution of resin in the stop resin 113 can be further reduced. This is because the hot water flow of the resin is improved when the sealing resin 113 is molded.

  In the above, as an example, the case where the uppermost semiconductor chip 105 is shifted from the center of the semiconductor chip 104 to the left side has been described. However, the uppermost semiconductor chip 105 may be installed shifted from the center of the semiconductor chip 104 to the right side. In this case, the upper surface and the lower surface of the semiconductor chip 104 have an angle so that the volume on the right side where the semiconductor chip 105 is installed is small, while the volume on the left side where the semiconductor chip 105 is not installed is large. It becomes the shape which has.

  In the first embodiment, the case where the number of stacked semiconductor chips is three has been described. However, the number of stacked semiconductor chips may be two or more. When the number of stacked semiconductor chips is three or more, at least one of the semiconductor chips other than the uppermost semiconductor chip may have a shape having an angle between the lower surface and the upper surface of the semiconductor chip.

(Second Embodiment)
FIG. 2 is a cross-sectional view showing a configuration example of a semiconductor package 200 according to the second embodiment of the present invention. The semiconductor package 200 is characterized in that the bias in the distribution of the sealing resin is reduced by providing an angle between the lower surface and the upper surface of the adhesive member. In the semiconductor package 200 of the second embodiment, the same reference numerals are given to the same components as those of the semiconductor package 100 (see FIG. 1) of the first embodiment, and detailed description thereof is omitted. To do.

  As shown in FIG. 2, the semiconductor package 200 is a BGA type. The semiconductor package 200 includes a plurality of solder balls 101, a wiring board 102, semiconductor chips 103, 203 to 205, adhesive members 106, 214, 207 and 208, bonding wires 209 to 212, and a sealing resin 213. Prepare. The broken line X is a straight line extending in the vertical direction and passing through the center of the semiconductor package 200.

  A plurality of solder balls 101 are arranged on the lower surface of the wiring board 102. A semiconductor chip 103 is bonded to the upper surface of the wiring substrate 102 via an adhesive member 106. The semiconductor chip 203 is bonded to the upper surface of the semiconductor chip 103 via an adhesive member 214. A semiconductor chip 204 is bonded to the upper surface of the semiconductor chip 203 via an adhesive member 207. A semiconductor chip 205 is bonded to the upper surface of the semiconductor chip 204 via an adhesive member 208. The wiring substrate 102 and the semiconductor chip 103 are connected by bonding wires 209. The semiconductor chip 103 and the semiconductor chip 203 are connected by a bonding wire 210. The semiconductor chip 203 and the semiconductor chip 204 are connected by a bonding wire 211. The wiring board 102 and the semiconductor chip 205 are connected by bonding wires 212. In addition, the quantity and connection of a bonding wire are examples, and another quantity and connection may be sufficient.

  The width A of the uppermost semiconductor chip 205 is smaller than the width B of the semiconductor chip 204 to which the semiconductor chip 205 is bonded. FIG. 2 shows a case where the width A is about one-fourth of the width B as an example. In order to shorten the length of the bonding wire 212 connected to the semiconductor chip 205, the uppermost semiconductor chip 205 is located on the left side from the center of the semiconductor chip 204 (in FIG. 2, the center coincides with the broken line X). It is installed in a staggered manner. More specifically, when a line passing through the center of the semiconductor chip 205 and parallel to the broken line X is a broken line Y, the broken line Y is shifted from the broken line X to the left.

  The lower surface and the upper surface of the adhesive members 214 and 207 are not parallel but have an angle. Thus, as can be seen from FIG. 2, the volume of the adhesive members 214 and 207 is small on the left side where the semiconductor chip 205 is installed, while it is large on the right side where the semiconductor chip 205 is not installed. Since the upper and lower surfaces of the semiconductor chips 103, 203, and 204 are all parallel, the upper surface of the wiring board 102 and the upper surface of the semiconductor chip 204 are not parallel but have an angle.

  The lower surface and the upper surface of the adhesive member 208 are not parallel, but have an angle, like the lower surfaces and the upper surface of the adhesive members 214 and 207. As a result, as shown in FIG. 2, the upper surface of the semiconductor chip 205 is substantially parallel to the upper surface of the wiring substrate 102. Note that the lower surface and the upper surface of the semiconductor chip 205 are parallel to each other.

  The sealing resin 213 is formed on the upper surface of the wiring substrate 102 so as to integrally cover the semiconductor chips 103 and 203 to 205, the adhesive members 106, 214, 207, and 208 and the bonding wires 209 to 212.

  Here, an example of a method of forming the bottom surface and the top surface of the adhesive members 214, 207, and 208 with an angle will be briefly described. When using a paste-type adhesive member, the thickness is gradually increased from one end of the adhesive member to the other end by increasing the amount of application. When a film-type adhesive member is used, one having a shape in which the thickness gradually increases from one end to the other end of the adhesive member is used.

  With the configuration described above, the semiconductor package 200 according to the second embodiment is sealed as shown in FIG. 2 when the right side and the left side are compared from the center (broken line X) of the semiconductor package 200. The unevenness of the resin distribution of the resin 213 can be reduced. As a result, the semiconductor package 200 according to the second embodiment can achieve the same effects as the semiconductor package 100 according to the first embodiment (see FIG. 1).

  The adhesive member 208 may have a normal adhesive member shape in which the lower surface and the upper surface are parallel. However, when the lower surface and the upper surface of the adhesive member 208 are provided with an angle so that the upper surface of the semiconductor chip 205 and the upper surface of the wiring substrate 102 are substantially parallel (see FIG. 2), the sealing resin 213 is used. The deviation of the resin distribution inside can be further reduced. This is because the hot water flow of the resin is improved when the sealing resin 213 is molded.

  In the above, as an example, the case where the uppermost semiconductor chip 205 is shifted from the center of the semiconductor chip 204 to the left side has been described. However, the uppermost semiconductor chip 205 may be installed shifted from the center of the semiconductor chip 204 to the right side. In this case, the adhesive members 214 and 207 have an upper surface and a lower surface so that the volume on the right side where the semiconductor chip 205 is installed is small, while the volume on the left side where the semiconductor chip 205 is not installed is large. Becomes a shape having an angle.

  In the second embodiment, the case where the number of stacked semiconductor chips is four has been described. However, the number of stacked semiconductor chips may be two or more. Further, in the second embodiment, the adhesive members 214 and 207 have been described as shapes having an angle between the lower surface and the upper surface, respectively. However, at least one of the adhesive members excluding the adhesive member (see 208 in FIG. 2) that adheres the uppermost semiconductor chip only needs to have a shape having an angle between the lower surface and the upper surface of the adhesive member.

  Further, as a method of forming an adhesive member having an angle between the lower surface and the upper surface, there is a method of providing a girder. FIG. 3 is a cross-sectional view showing a configuration example of the semiconductor package 200-1 when an adhesive member is formed by providing a girder. In the semiconductor package 200-1, the same components as those of the semiconductor package 200 (see FIG. 2) are denoted by the same reference numerals, and the description thereof is omitted. For simplicity of explanation, the case where the semiconductor package 200-1 includes two semiconductor chips will be described as an example. As illustrated in FIG. 3, the adhesive member 207 includes a girder 270 at a position where the thickness inside the adhesive member 207 is large (a position on the right side from the center of the adhesive member 207). Similarly, the adhesive member 208 includes a girder 280 at a position where the thickness inside the adhesive member 208 is large (position on the left side from the center of the adhesive member 208). The girders 270 and 280 prevent the adhesive members 207 and 208 having fluidity from being crushed by the weight of the semiconductor chip or the like in the semiconductor chip bonding process. Accordingly, the adhesive members 207 and 208 can be formed in a shape having a larger inclination than that described with reference to FIG. 2, and the thickness accuracy is improved as compared with the case described with reference to FIG.

  Below, the example of the formation method of the adhesive member 207 provided with the girder 270 and the adhesive member 208 provided with the girder 280 is demonstrated easily. For the girders 270 and 280, polyimide tape or the like is used. First, after placing the girders 270 on the upper surface of the wiring substrate 102, a paste-type adhesive member is applied to the upper surface of the wiring substrate 102. Thereafter, the semiconductor chip 204 is placed on the upper surface of the applied adhesive member, and the adhesive member is hardened. By this method, the adhesive member 207 is formed. Note that after the semiconductor chip 204 is inclined and placed on the girders 270 disposed on the upper surface of the wiring substrate 102, an adhesive member is injected into the space between the semiconductor chip 204 and the wiring substrate 102 to form the adhesive member 207. Also good. Similarly, since the adhesive member 208 is also formed, description thereof is omitted.

  Also, in the above, the semiconductor package 100 (first embodiment; see FIG. 1) in which the bias of the sealing resin 113 is reduced by providing the semiconductor chip 104 having an angle between the lower surface and the upper surface; Semiconductor packages 200 and 200-1 that reduce the bias of the sealing resin 213 by providing adhesive members 207, 214, and 208 having an angle with the upper surface (second embodiment; see FIGS. 2 and 3) And explained. However, as in the semiconductor package 300 illustrated in FIG. 4, the semiconductor chip and the lower surface and the upper surface of the adhesive member may have an angle. In the semiconductor package 300 shown in FIG. 4, the same components as those of the semiconductor packages 100, 200, and 200-1 shown in FIGS.

  In the above description, the BGA type semiconductor packages 100, 200, 200-1, and 300 are described as examples. However, the type of the semiconductor package is not limited to the BGA type as long as the sealing resin is a type of semiconductor package that is integrally formed on the upper surface of the wiring substrate 102.

(Third embodiment)
FIG. 5 is a cross-sectional view showing a configuration example of a semiconductor package 400 according to the third embodiment of the present invention. As shown in FIG. 5, the semiconductor package 400 is a lead frame type. The semiconductor package 400 includes a lead part 401 and a die pad part 402 that constitute a lead frame 411, adhesive members 403 and 405, semiconductor chips 404 and 406, bonding wires 407 to 409, and a sealing resin 410. In the lead part 401, the part covered with the sealing resin 410 is the inner lead part 401-1, and the part not covered with the sealing resin 410 is the outer lead part 401-2. As shown by the black arrows in FIG. 5, the direction toward the upper layer of the semiconductor chip is the upward direction, and the direction opposite to the upward direction is the downward direction. In addition, the directions indicated by white arrows in FIG. 5 are the right direction and the left direction. The broken line X is a straight line extending in the vertical direction and passing through the center of the semiconductor package 400. The mounting surface 490 is a mounting surface of the semiconductor package 400.

  As shown in FIG. 5, a semiconductor chip 404 is bonded to an upper surface (hereinafter referred to as an upper surface) of the die pad unit 402 via an adhesive member 403. A semiconductor chip 406 is bonded to the upper surface of the semiconductor chip 404 via an adhesive member 405. The semiconductor chip 404 and the inner lead part 401-1 are connected by bonding wires 407 and 409. The semiconductor chip 406 and the inner lead part 401-1 are connected by a bonding wire 408. The sealing resin 410 covers the inner lead part 401-1, the die pad part 402, the adhesive members 403 and 405, the semiconductor chips 404 and 406, and the bonding wires 407 to 409. In addition, the quantity and connection of a bonding wire are examples, and another quantity and connection may be sufficient.

  The uppermost semiconductor chip 406 is smaller than the bonded semiconductor chip 404. More specifically, the width A of the uppermost semiconductor chip 406 is smaller than the width B of the semiconductor chip 404 to which the semiconductor chip 406 is bonded. FIG. 5 shows a case where the width A is about one-fourth of the width B as an example. Further, in order to shorten the length of the bonding wire 408 connected to the semiconductor chip 406, the uppermost semiconductor chip 406 is located on the left side from the center of the semiconductor chip 404 (in FIG. 5, the center coincides with the broken line X). It is installed in a staggered manner. More specifically, when a line passing through the center of the semiconductor chip 406 and parallel to the broken line X is a broken line Y, the broken line Y is shifted from the broken line X to the left.

  The outer lead portion 401-2 has a shape that allows the semiconductor package 400 to be installed on the mounting surface 490. A lower surface (hereinafter referred to as a lower surface) of the sealing resin 410 is generally parallel to the mounting surface 490. The lower surface of the die pad portion 402 is parallel to the lower surface of the sealing resin 410. The upper surface of the die pad unit 402 is not parallel to the lower surface of the die pad unit 402 and has an angle. As a result, as can be seen from FIG. 5, the volume of the die pad unit 402 is small on the left side of the broken line X where the semiconductor chip 406 is installed, and on the right side of the broken line X where the semiconductor chip 406 is not installed. Since the upper surface and the lower surface of the semiconductor chip 404 and the adhesive member 403 are both parallel, the lower surface of the sealing resin 410 and the upper surface of the semiconductor chip 404 are not parallel but have an angle. Further, the lower surface and the upper surface of the semiconductor chip 406 and the adhesive member 405 are both parallel.

  Here, the arrangement position of the laminated body 491 (not shown in FIG. 5) composed of the die pad portion 402, the semiconductor chips 404 and 406, and the adhesive members 403 and 405 will be described. The laminated body 491 has a volume of the sealing resin α (see the broken line) formed above the laminated body 491 and a volume of the sealing resin β (see the broken line) formed below the laminated body 491. It arrange | positions in the position which becomes substantially equal. As a result, in the semiconductor package 400, the lower surface of the die pad portion 402 is positioned below the lower surface of the inner lead portion 401-1.

  With the configuration described above, the semiconductor package 400 according to the third embodiment can reduce the unevenness of the resin distribution in the horizontal direction and the vertical direction of the sealing resin 410 as shown in FIG. Thus, unlike the conventional semiconductor package 950 (see FIG. 13), the semiconductor package 400 according to the third embodiment does not increase the number of parts by installing dummy semiconductor chips, and the semiconductor package 400 Warpage, in particular, warpage accompanied by twisting can be reduced. Further, the semiconductor package 400 according to the third embodiment can avoid stress concentration on the upper surface of the semiconductor chip, which is caused by installing the dummy semiconductor chip.

  In addition, although it is influenced by the shape of the laminated body 491 etc., generally the laminated body 491 is arrange | positioned in the position where the volume of sealing resin (alpha) and the volume of sealing resin (beta) become equal as already demonstrated. Most preferred. Then, as the arrangement position of the laminate 491 approaches the position where the volume of the sealing resin α and the volume of the sealing resin β are equal, the deviation in the vertical resin distribution of the sealing resin 410 can be reduced. it can.

  In addition, the semiconductor chip 104 (see FIG. 1) having an angle between the lower surface and the upper surface described in the first embodiment may be applied to the semiconductor package 400. In addition, the adhesive members 214 and 207 (see FIGS. 2 to 4) having an angle between the lower surface and the upper surface described in the second embodiment may be applied to the semiconductor package 400. Further, the semiconductor chip 104 of the first embodiment and the adhesive members 214 and 207 of the second embodiment may be applied to the semiconductor package 400. FIG. 6 is a cross-sectional view illustrating a configuration example of a semiconductor package 400-1 in which a semiconductor chip and an adhesive member having an angle between the lower surface and the upper surface are applied to the semiconductor package 400. As shown in FIG. 6, the semiconductor package 400-1 includes a semiconductor chip 431 and adhesive members 430 and 432 having an angle between the lower surface and the upper surface. The adhesive member 432 includes a girder 433.

  When the semiconductor chip 400-1 includes a semiconductor chip having an angle between the lower surface and the upper surface and / or an adhesive member having an angle between the lower surface and the upper surface, the semiconductor package 400-1 has a lower surface and an upper surface instead of the die pad portion 402. You may provide the die pad part 434 which is parallel. FIG. 7 is a cross-sectional view illustrating a configuration example of a semiconductor package 400-2 in which the die pad portion 402 is replaced with a die pad portion 434 whose bottom surface and top surface are parallel to each other in the semiconductor package 400-1 of FIG.

  Further, in the third embodiment, at least one of the semiconductor chip excluding the uppermost semiconductor chip, the adhesive member excluding the adhesive member that adheres the uppermost semiconductor chip, and the die pad portion is provided between the lower surface and the upper surface. The case where the shape has an angle has been described. However, all of the semiconductor chip excluding the uppermost semiconductor chip, the adhesive member excluding the adhesive member for adhering the uppermost semiconductor chip, and the die pad portion may have a shape in which the lower surface and the upper surface are parallel. FIG. 8 is a cross-sectional view illustrating a configuration example of a semiconductor package 400-3 in which the die pad portion 406 is replaced with a die pad portion 434 whose bottom surface and top surface are parallel in the semiconductor package 400 (see FIG. 5). As shown in FIG. 8, in the semiconductor package 400-3, the lower surface of the die pad portion 434 has an angle with the lower surface of the sealing resin 410. Similarly to the semiconductor package 400, the semiconductor package 400-3 is disposed at a position where the volume of the sealing resin α and the volume of the sealing resin β are approximately equal. Thereby, the semiconductor package 400-3 can reduce the unevenness of the resin distribution in the horizontal direction and the vertical direction of the sealing resin 410. Note that the semiconductor package 400 of FIG. 5 can reduce the uneven distribution of the resin distribution of the sealing resin 410 as compared to the semiconductor package 400-3 of FIG.

  In the third embodiment, as an example, the case where the uppermost semiconductor chip 406 is shifted from the center of the semiconductor chips 404 and 431 to the left side has been described. However, the uppermost semiconductor chip 406 may be shifted from the center of the semiconductor chips 404 and 431 to the right. In this case, the upper surfaces of the semiconductor chips 404 and 431 have an angle with the lower surface of the sealing resin 410 in a state in which the upper surfaces of the semiconductor chips 404 and 431 are farther away from the lower surface of the sealing resin 410 in the right direction.

  In the third embodiment, the case where the number of stacked semiconductor chips is two has been described. However, the number of stacked semiconductor chips may be two or more.

  INDUSTRIAL APPLICABILITY The present invention can be used for a semiconductor device having a structure in which semiconductor chips are stacked, and particularly, a semiconductor by reducing the uneven distribution of a sealing resin and a semiconductor chip in a resin sealing region. This is useful for reducing package warpage.

Sectional drawing which shows the structural example of the semiconductor package 100 which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the structural example of the semiconductor package 200 which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the structural example of the semiconductor package 200-1 which concerns on the 2nd Embodiment of this invention when providing a girder and forming an adhesive member Sectional drawing which shows the structural example of the semiconductor package 300 which concerns on the 2nd Embodiment of this invention when the angle is given to the lower surface and upper surface of a semiconductor chip and an adhesive member, respectively. Sectional drawing which shows the structural example of the semiconductor package 400 which concerns on the 3rd Embodiment of this invention. Sectional drawing which shows the structural example of the semiconductor package 400-1 which concerns on the 3rd Embodiment of this invention which applied the semiconductor chip and adhesive member in which a lower surface and an upper surface have an angle to the semiconductor package 400 6 is a cross-sectional view illustrating a configuration example of a semiconductor package 400-2 according to the third embodiment of the present invention in which the die pad portion 402 is replaced with a die pad portion 434 whose bottom surface and top surface are parallel in the semiconductor package 400-1 of FIG. Figure Sectional drawing which shows the structural example of the semiconductor package 400-3 based on the 3rd Embodiment of this invention which replaced the die pad part 406 in the semiconductor package 400 with the die pad part 434 whose lower surface and upper surface are parallel. Sectional drawing which shows the conventional semiconductor chip lamination type semiconductor package 800 9 is a cross-sectional view showing a conventional semiconductor package 820 in which the installation position of the uppermost semiconductor chip 805 is shifted from the center of the semiconductor package with respect to the semiconductor package 800 shown in FIG. Sectional drawing for demonstrating the conventional semiconductor package 850 described in patent document 1 Sectional drawing for demonstrating the conventional semiconductor chip laminated | stacked semiconductor package 900 Sectional drawing which shows the conventional semiconductor package 950 which applied the technique of patent document 2 to the semiconductor package 900

Explanation of symbols

100, 200, 200-1, 300, 400, 400-1, 400-2, 400-3, 800, 820, 850, 900, 950 Semiconductor package 101, 801 Solder ball 102, 802 Wiring substrate 103, 104, 105 , 203 to 205, 404, 406, 431, 803 to 805, 902, 903 Semiconductor chip 106 to 108, 203, 207, 208, 214, 403, 405, 430, 432, 806 to 808, 904, 905 Adhesive member 109 -112, 209-212, 407-409, 809-812, 906-908 Bonding wire 113, 213, 410, 813, 909 Sealing resin 270, 280, 433 Digit 401 Lead part 402, 434 Die pad part 401-1 Inner Lead part 401-2 Tarido portion 411,901 lead frame 490 mounting surface 491 laminate 851,910,911 dummy semiconductor chip

Claims (11)

A semiconductor device of a semiconductor chip stacking type,
A wiring board;
A plurality of semiconductor chips stacked on the upper surface of the wiring board;
A plurality of adhesive members for bonding the semiconductor chips or the semiconductor chip and the wiring board,
A sealing resin formed on an upper surface of the wiring board and covering the plurality of semiconductor chips and the plurality of adhesive members;
The width of the uppermost first layer semiconductor chip among the plurality of semiconductor chips is smaller than the width of the second layer semiconductor chip to which the first layer semiconductor chip is bonded.
The upper surface of the second layer semiconductor chip has an angle with the upper surface of the wiring board,
The center of the first layer semiconductor chip is shifted from the center of the second layer semiconductor chip in a direction in which the thickness from the upper surface of the second layer semiconductor chip to the upper surface of the wiring board becomes thinner. A semiconductor device characterized by the above.   2. The semiconductor device according to claim 1, wherein an upper surface and a lower surface of at least one of the plurality of semiconductor chips excluding the first layer semiconductor chip are not parallel to each other.   2. The upper surface and the lower surface of at least one of the plurality of adhesive members excluding an adhesive member that bonds the first layer semiconductor chip and the second layer semiconductor chip are not parallel to each other. Semiconductor device.   The girder made of a material harder than the adhesive member before curing is inserted in at least one of the adhesive members whose upper surface and lower surface are not parallel to each other in the bonding step. Semiconductor device. A semiconductor device of a semiconductor chip stacking type,
A lead frame composed of a lead portion and a die pad portion;
A plurality of semiconductor chips stacked on the upper surface of the die pad portion;
A plurality of adhesive members for bonding the semiconductor chips or the semiconductor chip and the die pad part,
A sealing resin that covers a part of the lead part, the die pad part, the plurality of semiconductor chips, and the plurality of adhesive members;
The width of the uppermost first layer semiconductor chip among the plurality of semiconductor chips is smaller than the width of the second layer semiconductor chip to which the first layer semiconductor chip is bonded.
The upper surface of the second layer semiconductor chip has an angle with the lower surface of the sealing resin,
The center of the first layer semiconductor chip is shifted from the center of the second layer semiconductor chip in a direction in which the thickness from the upper surface of the second layer semiconductor chip to the lower surface of the sealing resin is reduced. A semiconductor device.   6. The semiconductor device according to claim 5, wherein an upper surface and a lower surface of at least one of the plurality of semiconductor chips excluding the first layer semiconductor chip are not parallel to each other.   The upper surface and the lower surface of at least one of the plurality of adhesive members excluding an adhesive member that bonds the first layer semiconductor chip and the second layer semiconductor chip are not parallel to each other. Semiconductor device.   The girder made of a material harder than the adhesive member before curing is inserted into at least one of the adhesive members whose upper surface and lower surface are not parallel in the bonding step. Semiconductor device.   The semiconductor device according to claim 5, wherein an upper surface and a lower surface of the die pad portion are not parallel.   A plurality of semiconductor chips excluding the first layer semiconductor chip; a plurality of adhesive members excluding an adhesive member that bonds the first layer semiconductor chip and the second layer semiconductor chip; and upper and lower surfaces of the die pad portion; The semiconductor devices according to claim 5, wherein each is parallel to each other.   The laminated body in a direction in which the amount of sealing resin formed above and the amount of sealing resin formed below is equal to the laminated body composed of the die pad portion, the plurality of semiconductor chips, and the plurality of adhesive members. The semiconductor device according to claim 5, wherein the semiconductor devices are arranged to be shifted from each other.

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