JP7142695B2 - 半導体デバイスおよびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 66
- 125000006850 spacer group Chemical group 0.000 claims description 57
- 238000010884 ion-beam technique Methods 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 34
- 238000000059 patterning Methods 0.000 claims description 34
- 238000002955 isolation Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 12
- 238000000605 extraction Methods 0.000 claims description 12
- 239000002243 precursor Substances 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims 1
- 238000012545 processing Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000003491 array Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000000276 deep-ultraviolet lithography Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000000635 electron micrograph Methods 0.000 description 2
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- 230000000694 effects Effects 0.000 description 1
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- 238000002474 experimental method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
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- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Description
Claims (13)
- 半導体デバイス構造を製造する方法であって、
基板ベースおよび前記基板ベース上に配置されたパターニングスタックを備える基板を提供するステップを含み、前記基板はさらに、
前記パターニングスタック内に、第1の方向に沿って延在する第1の線形構造を、および
前記パターニングスタック内に、前記第1の方向に対して非ゼロの角度を成す第2の方向に沿って延在する第2の線形構造を備え、
前記第2の線形構造の1組の側壁上に一組の側壁スペーサを選択的に形成するステップを含む、方法。 - 前記第1の線形構造が第1の組の側壁と第2の組の側壁を含み、前記第2の線形構造が第3の組の側壁と第4の組の側壁を含み、前記一組の側壁スペーサが前記第4の組の側壁上に配置され、前記第1の組の側壁、前記第2の組の側壁、または前記第3の組の側壁上には配置されない、請求項1に記載の方法。
- 前記側壁スペーサを選択的に形成するステップは、
前記第1の線形構造および前記第2の線形構造上にブランケット側壁層を堆積するステップと、
前記第1の組の側壁、前記第2の組の側壁、および前記第3の組の側壁から前記ブランケット側壁層を選択的に除去するステップと、
を含む請求項2に記載の方法。 - 前記側壁スペーサを選択的に形成するステップは、
前記ブランケット側壁層を堆積した後、前記基板をプラズマチャンバに隣接するプロセスチャンバ内に供給するステップと、
イオンビームを前記プラズマチャンバから抽出アパーチャを通してプロセスチャンバに抽出し、前記イオンビームは基板平面に対して非ゼロ入射角を規定する軌道を形成する、ステップと、
前記基板が前記抽出アパーチャに対してスキャンされ、前記基板が前記イオンビームに暴露される複数のスキャンを実行するステップと、
を含む、請求項3に記載の方法。 - 前記複数のスキャンを実行するステップは、
第1のスキャンを実行して、前記第1の組の側壁を前記イオンビームに暴露するステップ、
第2のスキャンを実行して、前記第2の組の側壁をイオンビームに暴露するステップ、および
第3のスキャンを実行して、前記第3の組の側壁をイオンビームに暴露するステップ、
を含み、
前記第4の組の側壁は、前記第1のスキャン、前記第2のスキャン、または前記第3のスキャン中に前記イオンビームに暴露されない、
請求項4に記載の方法。 - 前記第1の線形構造および前記一組の側壁スペーサが第1の分離パターンを画定し、前記方法は、前記第1の分離パターンを、前記パターニングスタックおよび前記基板ベースをエッチングすることによって、前記基板ベースに転写するステップをさらに含む、請求項1に記載の方法。
- 前記パターニングスタックは複数の層を含み、前記複数の層のうちの少なくとも2つの層は異なる材料を含み、さらに酸化ケイ素、窒化ケイ素、炭素、またはそれらの任意の組み合わせを含む、請求項1に記載の方法。
- ダイナミックランダムアクセスメモリを製造する方法であって、
基板ベースおよび前記基板ベース上に配置されたパターニングスタックを備える基板を提供するステップと、
前記パターニングスタック内に第1の方向に沿って細長い第1の線形構造を含む第1のパターンを形成するステップと、
前記パターニングスタック内に前記第1の方向に対して非ゼロの角度を成す第2の方向に沿って細長い第2の線形構造を含む第2のパターンを形成するステップと、
前記第2の線形構造の1組の側壁上に一組の側壁スペーサを選択的に形成するステップと、
前記第1の線形構造及び前記一組の側壁スペーサを含む第1の分離パターンを形成するステップと、
前記第1の分離パターンを前記基板ベースに転写するステップと、
を含む、方法。 - 前記第1の分離パターンを前記基板ベースに転写するステップは、前記第1の分離パターンを使用して、前記パターニングスタックおよび前記基板ベースをエッチングするステップを含む、請求項8に記載の方法。
- 前記一組の側壁スペーサを選択的に形成するステップは、
前記第1の線形構造および前記第2の線形構造上にブランケット側壁層を堆積するステップと、
前記第1の線形構造上に堆積された第1の組の側壁および第2の組の側壁から前記ブランケット側壁層を選択的に除去するステップと、
前記第2の線形構造上に堆積された第3の組の側壁から前記ブランケット側壁層を選択的に除去するステップと、
を含む請求項8に記載の方法。 - 前記側壁スペーサを選択的に形成するステップは、
前記ブランケット側壁層を堆積した後、前記基板をプラズマチャンバに隣接するプロセスチャンバ内に供給するステップと、
イオンビームを前記プラズマチャンバから抽出アパーチャを通してプロセスチャンバに抽出し、前記イオンビームは基板平面に対して非ゼロ入射角を規定する軌道を形成する、ステップと、
前記基板が前記抽出アパーチャに対してスキャンされ、前記基板が前記イオンビームに暴露される複数のスキャンを実行するステップと、
を含む、請求項10に記載の方法。 - 前記複数のスキャンを実行するステップは、
第1のスキャンを実行して、前記第1の組の側壁を前記イオンビームに暴露するステップ、
第2のスキャンを実行して、前記第2の組の側壁をイオンビームに暴露するステップ、および
第3のスキャンを実行して、前記第3の組の側壁をイオンビームに暴露するステップ、
を含み、
前記第2の線形構造上に堆積された第4の組の側壁は、前記第1のスキャン、前記第2のスキャン、または前記第3のスキャン中に前記イオンビームに暴露されない、
請求項11に記載の方法。 - 前記第1の線形構造を形成するステップは、
前記パターニングスタックの最上層にエッチングによって一組の線形前駆体構造を形成するステップと、
前記一組の線形前駆体構造上にブランケット層を堆積させるステップと、
前記ブランケット層をエッチングして、前記一組の線形前駆体構造上に一組の前駆体側壁スペーサを形成するステップと、
前記一組の前駆体側壁スペーサを除去せずに、前記パターニングスタックの最上層を選択的に除去するステップと、
を備え、
前記一組の前駆体側壁スペーサが前記第1の線形構造を形成する、請求項10に記載の方法。
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US15/803,283 US10607999B2 (en) | 2017-11-03 | 2017-11-03 | Techniques and structure for forming dynamic random access device |
US15/803,283 | 2017-11-03 | ||
PCT/US2018/057064 WO2019089277A1 (en) | 2017-11-03 | 2018-10-23 | Techniques and structure for forming dynamic random access device |
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JP7142695B2 true JP7142695B2 (ja) | 2022-09-27 |
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JP (1) | JP7142695B2 (ja) |
KR (1) | KR102329036B1 (ja) |
CN (1) | CN111279478B (ja) |
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US10629437B2 (en) * | 2018-05-09 | 2020-04-21 | Varian Semiconductor Equipment Associates, Inc. | Techniques and structure for forming dynamic random-access device using angled ions |
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