JP7125257B2 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

In recent years, CMOS technology has improved, and SoC (System on a Chip) in which analog circuits and digital circuits are mixed is used for various purposes. In such a mixed chip, a high resistance region is formed in the semiconductor substrate in order to improve the characteristics of the analog circuit. For example, by performing ion irradiation a plurality of times while changing the acceleration energy from the back side of the element region, a high resistance region for noise reduction is formed (see, for example, Patent Document 1).

JP 2015-119039 A

In the above-mentioned document, it is reported that when heat treatment at 200° C. or higher is applied to the high resistance region formed by ion irradiation, the resistivity is significantly lowered. It is described that heat treatment is desirable. However, in the manufacturing process of a semiconductor device, a post-process involving heat treatment at 200° C. or more may be performed, and in that case, the high resistivity obtained by ion irradiation cannot be maintained.

An exemplary object of one aspect of the present invention is to provide a technique for forming a high resistance region that can withstand heat treatment at 200° C. or higher.

A method of manufacturing a semiconductor device according to one aspect of the present invention includes irradiating a p-type semiconductor substrate on which a semiconductor element is formed with hydrogen (H) ions so that the hydrogen density is 2×10 ¹⁵ cm ⁻³ or more and 2×10 ¹⁷ cm ^{− 3} or less and having a resistivity higher than that of the p-type semiconductor substrate before ion irradiation; heating at a temperature.

Another aspect of the present invention is a semiconductor device. This device includes a p-type semiconductor substrate, a semiconductor element provided on the p-type semiconductor substrate, and a high resistance region provided within the p-type semiconductor substrate. The high-resistance region is a region having a hydrogen density of 2×10 ¹⁵ cm ⁻³ or more and 2×10 ¹⁷ cm ⁻³ or less and having a resistivity higher than that of the p-type semiconductor substrate.

It should be noted that arbitrary combinations of the above-described constituent elements and mutually replacing the constituent elements and expressions of the present invention in methods, devices, systems, etc. are also effective as aspects of the present invention.

According to the present invention, a high resistance region that can withstand heat treatment at 200° C. or higher can be formed.

1 is a cross-sectional view schematically showing the structure of a semiconductor device according to an embodiment; FIG. 7 is a graph showing an example of resistivity change due to helium (He) ion irradiation and heat treatment according to a comparative example; 5 is a graph showing an example of resistivity change due to hydrogen (H) ion irradiation and heat treatment according to an example. 7 is a graph showing an example of resistivity change due to hydrogen (H) ion irradiation and heat treatment according to another example. 4 is a graph showing the activation rate of hydrogen by heat treatment. It is a graph which shows typically the carrier concentration change by heat processing. 4 is a graph showing an example of the relationship between hydrogen density and resistivity change due to heat treatment. 4 is a graph showing an example of the relationship between the dose of hydrogen ion irradiation and the hydrogen density; It is a flow chart which shows a manufacturing method of a semiconductor device typically.

DETAILED DESCRIPTION OF THE INVENTION Embodiments for carrying out the present invention will be described in detail below. The configuration described below is an example and does not limit the scope of the present invention. Also, in the description of the drawings, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted as appropriate. In addition, in each cross-sectional view referred to in the following description, the thickness and size of the semiconductor substrate and other layers are for convenience of description, and do not necessarily represent actual dimensions and ratios.

FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is an integrated circuit (IC) such as a system LSI or system-on-chip. A semiconductor device 10 includes a semiconductor substrate 12 and a wiring layer 18 .

The semiconductor substrate 12 is a low resistance semiconductor substrate having a resistivity of 100 Ω·cm or less, and is a semiconductor substrate having a resistivity of about 1 to 100 Ω·cm. The semiconductor substrate 12 is, for example, a p-type silicon (Si) wafer manufactured by the Czochralski (CZ) method. Wafers produced by the CZ method have lower resistivity and are cheaper than high-resistance wafers produced by the floating zone (FZ) method or the like. In one embodiment, semiconductor substrate 12 has a resistivity of 4 Ω·cm and a p-type carrier concentration of 3.4×10 ¹⁵ cm ⁻³ .

A first element region 22 and a second element region 24 are provided on the main surface 14 of the semiconductor substrate 12 . For example, the first element region 22 is provided with a first semiconductor element 26 for digital circuits, and the second element area 24 is provided with a second semiconductor element 28 for analog circuits. The first semiconductor element 26 and the second semiconductor element 28 are, for example, transistors and diodes. Impurity diffusion layers such as well regions, source/drain regions and contact regions for forming semiconductor elements are provided in each of the first element region 22 and the second element region 24 .

In this specification, the direction perpendicular to the main surface 14 of the semiconductor substrate 12 is sometimes referred to as the vertical direction or the depth direction. Further, in the interior of the semiconductor substrate 12, the direction toward the principal surface 14 may be referred to as the upward direction or the upper side, and the direction toward the back surface 16 opposite to the principal surface 14 may be referred to as the downward direction or the downward direction. Also, the direction parallel to the main surface 14 may be referred to as the lateral direction or the horizontal direction.

A high resistance region 30 is provided inside the semiconductor substrate 12 . The high resistance region 30 is a region having higher resistivity than the body portion of the semiconductor substrate 12 . The high resistance region 30 has a resistivity of 100 Ω·cm or more, for example, 500 Ω·cm or more, preferably 1 kΩ·cm or more. The high resistance region 30 includes a trench type high resistance region 32 and a planar type high resistance region 34 .

The trench-type high-resistance region 32 is provided in the isolation region 20 between the first element region 22 and the second element region 24, and has a certain depth from the main surface 14 toward the back surface 16 of the semiconductor substrate 12. It is formed. The depth of the trench type high resistance region 32 is 20 μm or more, preferably about 50 μm to 200 μm. The trench type high resistance region 32 is formed to reach a position deeper than the impurity diffusion layers formed in the first element region 22 and the second element region 24 . The trench-type high-resistance region 32 has, for example, a function of blocking noise traveling from the digital circuit to the analog circuit and improving the characteristics of the analog circuit.

The planar high resistance region 34 extends horizontally in the second element region 24 . The planar high resistance region 34 extends horizontally from the isolation region 20 to the second element region 24 and may be provided to form a high resistance region continuous with the trench high resistance region 32 . The planar high-resistance region 34 contributes to the improvement of analog circuit characteristics by being formed directly under the analog circuit.

In the illustrated example, both the trench type high resistance region 32 and the planar type high resistance region 34 are formed inside the semiconductor substrate 12, but in the modified example, the trench type high resistance region 32 and the planar type high resistance region are formed. 34 may be provided.

The high-resistance region 30 is formed by irradiating the body portion of the semiconductor substrate 12, which is a low-resistance substrate, with hydrogen (H) ions. When the wafer is irradiated with ions, the ions reach a depth corresponding to the acceleration energy of the ions. At that time, lattice defects are formed in the vicinity including the reached region, and the regularity (periodicity) of the crystal is disturbed. Carriers (electrons or holes) are easily scattered in such a region with many lattice defects, and carrier movement is inhibited. As a result, in regions where ion irradiation causes local lattice defects, the resistivity increases compared to before irradiation.

The position and range in the depth direction where the resistivity is increased by ion irradiation can be adjusted by appropriately selecting the acceleration energy and dose of ion irradiation. For example, the depth position at which the high resistance region is formed can be adjusted by adjusting the acceleration energy of ions during ion irradiation. Further, by selecting the acceleration energy of ion irradiation, it is possible to adjust the depth position where the high resistance region is formed, the range in the depth direction (half width), and the spread width in the lateral direction. Furthermore, by performing ion irradiation a plurality of times while changing the acceleration energy, a thicker high-resistance region can be formed in the depth direction.

In this embodiment mode, hydrogen (H) ions are irradiated with an acceleration energy of 1 MeV or more and 100 MeV or less. For example, monovalent hydrogen ions ( ¹ H ⁺ ) are irradiated with acceleration energies of 4 MeV, 8 MeV, and 17 MeV. As a device for irradiating an ion beam with such acceleration energy, a cyclotron system or a Van de Graaff system is used. By using such irradiation conditions, ions can be made to reach a depth of 100 μm or more from the vicinity of the main surface 14 of the semiconductor substrate 12 in the silicon wafer.

The resistivity of the high resistance region formed by ion irradiation depends on the density of lattice defects (defect density) generated. According to the findings of the present inventors, it is known that a resistivity of 1 kΩ·cm or more can be suitably obtained if the defect density is 1×10 ¹⁷ cm ⁻³ or more. Such a defect density can be realized by setting the irradiation amount (dose amount) of hydrogen ions to 1×10 ¹³ cm ⁻² or more if the acceleration energy of irradiation ions is 4 MeV to 17 MeV.

It is known that the resistivity of the high-resistance region formed in this manner is reduced by heat treatment. According to the findings of the inventors, a decrease in resistivity is observed when the semiconductor substrate 12 after ion irradiation is heated to 200° C. or higher, and the resistivity decreases when the semiconductor substrate 12 is heated to 300° C. or higher or 400° C. or higher. Remarkably decreased. This is probably because the heat treatment recovers the lattice defects and reduces the defect density. Therefore, if the high-resistance region is formed by ion irradiation, it may be preferable not to apply heat treatment at 200° C. or higher in subsequent steps.

On the other hand, in order to form the high-resistance regions 30 at the intended positions such as the isolation regions 20 and the second element regions 24, ion irradiation must be performed before the wafer is diced, that is, before the post-process in the semiconductor process. need to run. In post-processes, heat treatments such as die bonding, wire bonding, and resin sealing are performed, and the semiconductor substrate 12 can be heated to a temperature of about 200.degree. C. to 300.degree. Therefore, there is a possibility that the resistivity of the high-resistance region is lowered by the heat treatment in the post-process, and the desired resistivity (for example, 500 Ω·cm or more) cannot be maintained.

Therefore, in the present embodiment, hydrogen implanted into the semiconductor substrate 12 by ion irradiation is activated by heat treatment, so that the resistivity of the high resistance region is maintained even after the heat treatment. When hydrogen is activated by heat treatment, the concentration of n-type carriers increases due to donor conversion, so the majority carriers (p-type carriers) of the p-type semiconductor substrate 12 are neutralized and the electrical conductivity decreases. For example, the semiconductor substrate 12 can be neutralized to increase the resistivity by activating hydrogen to obtain an n-type carrier concentration similar to the p-type carrier concentration of the semiconductor substrate 12 .

FIG. 2 is a graph showing an example of resistivity change due to helium (He) ion irradiation and heat treatment according to a comparative example. In the comparative example, helium ions ( ³ He ²⁺ ) are used instead of hydrogen ions ( ¹ H ⁺ ). The acceleration energy is 23 MeV, the dose amount is 1.0×10 ¹³ cm ⁻² , and the object to be irradiated is a p-type silicon substrate of about 4 Ω·cm. FIG. 2 shows the resistivity distribution in the depth direction of the substrate before ion irradiation, after ion irradiation (before heat treatment), and after heat treatment (200° C., 250° C., 300° C.). As shown in the figure, before heat treatment, a high resistance region of about 1 to 2 kΩ·cm can be formed to a depth of about 60 μm, and even after heat treatment at 200° C., a high resistance region with almost the same resistivity distribution can be maintained. ing. However, after heat treatment at 250° C., the resistivity of the high resistance region is less than 1 kΩ·cm and partially less than 500 Ω cm, and after heat treatment at 300° C., the resistivity of the high resistance region is 100 Ω·cm. is less than As described above, when ion irradiation is performed using helium, the resistivity of the high-resistance region is lowered by heat treatment above 200° C., and the resistivity is significantly lowered by heat treatment at 300° C. or higher.

FIG. 3 is a graph showing an example of changes in resistivity due to hydrogen (H) ion irradiation and heat treatment according to the example. In this example, hydrogen ions ( ¹ H ⁺ ) were irradiated, the acceleration energy was 8 MeV, the dose amount was 1.0×10 ¹⁴ cm ⁻² , and the object to be irradiated was a p-type of about 4 Ω·cm. A silicon substrate. FIG. 3 shows the resistivity distribution in the depth direction of the substrate before ion irradiation, after ion irradiation (before heat treatment), and after heat treatment (250° C., 400° C.). As shown in the figure, before heat treatment, a high resistance region of 1 kΩ·cm or more can be formed to a depth of about 110 μm, and even after heat treatment at 250° C., a high resistance region with almost the same resistivity distribution can be maintained. . Moreover, even after heat treatment at 400° C., a high resistance region of 1 kΩ·cm or more can be maintained at a depth of 10 μm to 80 μm. In this way, by using hydrogen ions, a high resistance region of 500 Ω·cm or more, preferably 1 kΩ·cm or more can be maintained even when heat treatment at 200° C. or higher or 300° C. or higher is applied.

FIG. 4 is a graph showing an example of resistivity change due to hydrogen (H) ion irradiation and heat treatment according to another example. In this example, hydrogen ions ( ¹ H ⁺ ) are irradiated as in FIG. 3, the acceleration energy is 8 MeV, and the irradiation target is a p-type silicon substrate of about 4 Ω·cm. This embodiment uses a dose amount different from that of FIG. 3, and is 2.6×10 ⁻¹⁴ cm ⁻² which is higher than the dose amount of the above-described embodiment. FIG. 4 shows the resistivity distribution in the depth direction of the substrate before ion irradiation, after ion irradiation (before heat treatment), and after heat treatment (200° C., 300° C., 400° C.). As shown in the figure, before heat treatment, a high resistance region of 1 kΩ·cm or more can be formed to a depth of about 45 μm, and even after heat treatment at 200° C., a high resistance region with almost the same resistivity distribution can be maintained. . However, after heat treatment at 300° C., the resistivity at a depth of about 10 to 30 μm is less than 1 kΩ·cm, and after heat treatment at 400° C., it is less than 100 Ω·cm. This is because by increasing the dose of hydrogen ions, hydrogen is excessively donated, the conductivity type is reversed from p-type to n-type, and the resistivity decreases due to the increase in n-type carrier concentration that becomes the majority carrier. It is considered to be the cause.

From the above comparative examples and examples, in order to maintain high resistivity (500 Ω cm or more) even after heat treatment exceeding 200 ° C., it is necessary to appropriately control the dose of hydrogen ions and the temperature of heat treatment. I can say.

FIG. 5 is a graph showing the activation rate of hydrogen by heat treatment, showing the relationship between the temperature and the activation rate. As shown in the figure, the activation rate of hydrogen is low in the range of 200° C. to 400° C., and the increase in the activation rate with increasing temperature is moderate. On the other hand, when the temperature exceeds 400° C., the rate of increase in the activation rate due to temperature rise increases, and the value of the activation rate exceeds 10%. Therefore, by using heat treatment in the range of 200° C. to 400° C. where the activation rate increases slowly with temperature rise, even if there is individual difference in heat treatment temperature in the subsequent process, the resistance due to the difference in treatment temperature can be reduced. A significant change in the rate can be suppressed.

FIG. 6 is a graph schematically showing changes in carrier concentration due to heat treatment, and schematically shows values of n-type carrier concentrations that are converted to donors by heat treatment for three different hydrogen densities. A has a hydrogen density of 5×10 ¹⁶ cm ⁻³ and corresponds to the example of FIG. 3 (energy: 8 MeV, dose: 1.0×10 ¹⁴ cm ⁻² ). B has a hydrogen density of 1.3×10 ¹⁷ cm ⁻³ and corresponds to the example of FIG. 4 (energy: 8 MeV, dose: 2.6×10 ¹⁴ cm ⁻² ). C has a hydrogen density of 5×10 ¹⁵ cm ⁻³ and D has a hydrogen density of 2.5×10 ¹⁶ cm ⁻³ . The dashed line in the graph indicates the p-type carrier concentration in the semiconductor substrate, which is 3.4×10 ¹⁵ cm ⁻³ .

In the case of A, the n-type carrier concentration is about 1.0×10 ¹⁵ cm ⁻³ at 200° C., and about 3.4×10 ¹⁵ cm ⁻³ which is the same as the p-type carrier concentration of the substrate at about 330° C., and 400° C. is about 6.0×10 ¹⁵ cm ⁻³ at . As a result, in the range of 250°C to 400°C, where the decrease in resistivity due to recovery of lattice defects becomes significant, the p-type carrier concentration and the n-type carrier concentration become approximately the same, realizing high resistivity due to the neutralization of the substrate. can. As a result, as shown in FIG. 3, even after heat treatment at 200° C. to 400° C., a high resistance of 1 kΩ·cm or more can be maintained.

In the case of B, the n-type carrier concentration is about 2.6×10 ¹⁵ cm ⁻³ at 200° C., and about 3.4×10 ¹⁵ cm ⁻³ which is the same as the p-type carrier concentration of the substrate at about 230° C., and 300° C. 6.8×10 ¹⁵ cm ⁻³ which is twice the p-type carrier concentration of the substrate, and 1.0×10 ¹⁶ cm ⁻³ or more at 350° C. or higher. As a result, as shown in FIG. 4, heat treatment at 300.degree.

In the case of C, since the hydrogen density is 0.1 times that of A, the carrier concentration resulting from hydrogen donor conversion is low, and the p-type carrier concentration of the substrate (3.4×10 ¹⁵ cm ⁻³ ). As a result, even if heat treatment at 200.degree. C. to 400.degree. Similarly, in the case of D, the hydrogen density is 0.5 times that of A, and even if heat treatment at 200° C. to 400° C. is applied, the p-type carrier concentration (3.4×10 ¹⁵ cm ⁻³ ) of the substrate is not reached. Therefore, it is considered that the neutralization of the substrate does not occur, and only the resistivity decreases due to the decrease in the defect density.

FIG. 7 is a graph showing an example of the relationship between hydrogen density and resistivity change due to heat treatment, showing resistivity changes corresponding to conditions A, B, C, and D in FIG. As shown, in the case of A (hydrogen density: 5×10 ¹⁶ cm ⁻³ ), a high resistance of 1 kΩ·cm or more can be maintained in the range of 200° C. to 400° C. FIG. In the case of B (hydrogen density: 1.3×10 ¹⁷ cm ⁻³ ), a high resistance of 500 Ω·cm or more can be maintained in the range of 200° C. to 300° C., but the resistivity drops to 200 Ω·cm or less at 350° C. or higher. turn into. In the case of C (hydrogen density: 5×10 ¹⁵ cm ⁻³ ), a high resistance of 1 kΩ·cm can be maintained by heat treatment at 200° C., but when the heat treatment exceeds 200° C., the resistivity drops significantly, reaching 250° C. After the above heat treatment, the resistance becomes 10 Ω·cm or less. The reason for this is thought to be that the concentration of n-type carriers for neutralization is insufficient due to the low hydrogen density. In the case of D (hydrogen density: 2.5×10 ¹⁶ cm ⁻³ ), a high resistance of 500 Ω·cm or more can be maintained in the range of 200° C. to 230° C., but the resistivity is 200 Ω·cm at 250° C. or higher. It becomes below.

From the above consideration, in order to maintain a high resistivity even after heat treatment, it is necessary to realize an n-type carrier concentration comparable to the p-type carrier concentration of the semiconductor substrate 12 in the temperature range of 200° C. to 400° C. be. Since the activation rate of hydrogen by heat treatment at 200° C. to 400° C. is about 2% to 10%, a hydrogen density of about 10 to 50 times the p-type carrier concentration of the semiconductor substrate 12 should be realized. In general, the p-type carrier concentration of a p-type silicon substrate with low resistance (1 to 100 Ω·cm) is 10 ¹⁴ to 10 ¹⁶ cm ⁻³ , so the concentration is 5×10 ¹⁵ cm ⁻³ or more and 2×10 ⁻¹⁷ cm It suffices if a hydrogen density of ^-3 or less can be realized. For example, if the p-type carrier concentration is 3.4×10 ¹⁵ cm ⁻³ , the hydrogen density is preferably 3.4×10 ¹⁶ cm ⁻³ or more and 1.7×10 ⁻¹⁷ cm ⁻³ or less.

If the conductivity type of at least part of the high-resistance region 30 is inverted to n-type, a pn junction is formed in the high-resistance region, which may affect the operation of circuit elements formed on the semiconductor substrate 12 . In order to suppress such an influence, the value of the hydrogen density may be controlled so that the n-type carrier concentration due to hydrogen activation does not exceed the p-type carrier concentration of the semiconductor substrate 12 . In other words, the hydrogen density and the heat treatment temperature may be controlled so that the conductivity type of the high resistance region 30 remains p-type.

FIG. 8 is a graph showing an example of the relationship between the dose amount of hydrogen ion irradiation and the hydrogen density, and shows cases where the hydrogen ion acceleration energies are 4 MeV, 8 MeV, and 17 MeV. As shown in the figure, the dose amount of hydrogen ions and the hydrogen density after irradiation are in a proportional relationship. Also, the lower the irradiation energy, the higher the hydrogen density obtained. This is because when the acceleration energy is low, the depth range in which hydrogen ions are implanted is limited, and the amount of hydrogen implanted per unit volume increases. From the graph, in order to achieve a hydrogen density of 5×10 ¹⁵ cm ⁻³ or more and 2×10 ⁻¹⁷ cm ⁻³ or less, 1×10 ⁻¹³ cm ⁻² or more and 2×10 ⁻¹⁴ cm ⁻ at 4 MeV. ² or less, 1×10 ⁻¹³ cm ⁻² or more and 4×10 ⁻¹⁴ cm ⁻² or less at 8 MeV, 3.6×10 ⁻¹³ cm ⁻² or more and 1×10 ⁻¹⁵ cm ⁻² or less at 17 MeV should be Incidentally, if ion irradiation is performed with these dose amounts, a defect density of 1×10 ¹⁷ cm ⁻³ or more can be obtained, so a high resistivity of 500 Ω·cm or more can be realized even before the heat treatment.

Next, a method for manufacturing the semiconductor device 10 according to this embodiment will be described. FIG. 9 is a flow chart schematically showing the manufacturing method of the semiconductor device 10. As shown in FIG. First, elements are formed on a p-type semiconductor substrate 12 by various processes (S10), a wiring layer is formed on the semiconductor substrate 12, and a protective film is formed to protect the formed elements and wiring (S14). ). The steps S10 to S14 are called "pre-processes" in the semiconductor process, and can be subjected to high temperature treatments of 400° C. or higher such as thermal oxidation, thermal diffusion, CVD, and annealing. Subsequently, the semiconductor substrate 12 is irradiated with hydrogen ions to form the high resistance region 30 (S16), and the back surface of the semiconductor substrate 12 is polished (S18). The steps of S16 and S18 are so-called "intermediate steps" or "post passivation process (PPP)".

Subsequently, a post-process (S20) including heat treatment is performed to complete a semiconductor integrated circuit. In the post-process of S20, for example, a step of dicing the wafer into individual pieces, a die bonding step of adhering the separated chips onto a mounting substrate, a step of connecting the mounting substrate and the chips by wire bonding, and A step of sealing with resin and the like are included. For example, in the die bonding process, wire bonding process and resin sealing process, heat treatment is performed at about 200.degree. C. to 300.degree. Annealing treatment for heating the semiconductor device 10 may be performed separately from the bonding and sealing steps. This annealing treatment may stabilize the resistivity of the high resistance region 30 by heating the high resistance region 30 at a predetermined temperature of 200° C. or more and 400° C. or less. It is sufficient to perform this annealing treatment for a relatively short time of 10 minutes or less, and it may be 5 minutes or less, 1 minute or less, or 30 seconds or less.

The present invention has been described above based on the embodiments. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that various design changes and modifications are possible, and that such modifications are within the scope of the present invention. It is about

In the above embodiment, only hydrogen ions are irradiated to form the high resistance region 30 . In a modification, the high resistance region may be formed by combining ion irradiation other than hydrogen. For example, hydrogen ion irradiation may be used to achieve the hydrogen density within the above numerical range, and ion species other than hydrogen may be irradiated to achieve the above numerical defect density. In a modification, hydrogen ion irradiation and helium ion irradiation may be combined to form a high resistance region that can maintain high resistance (500 Ω·cm or more) even after heat treatment at 200° C. or more.

DESCRIPTION OF SYMBOLS 10... Semiconductor device, 12... Semiconductor substrate, 14... Main surface, 16... Back surface, 18... Wiring layer, 20... Separation region, 22... First element region, 24... Second element region, 26... First semiconductor element, 28... Second semiconductor element, 30... High resistance region, 32... Trench type high resistance region, 34... Planar type high resistance region.

Claims (8)

A p-type silicon substrate on which a semiconductor element is formed is irradiated with hydrogen (H) ions, and a region having a hydrogen density of 5×10 ¹⁵ cm ⁻³ or more and 2×10 ¹⁷ cm ⁻³ or less is obtained before the ion irradiation. forming a high resistance region having a higher resistivity than the p-type silicon substrate;
A method of manufacturing a semiconductor device, comprising: heating the p-type silicon substrate on which the high resistance region is formed at a temperature of 200° C. or more and 300° C. or less. 2. The method of manufacturing a semiconductor device according to claim ¹ , wherein the high-resistance region is formed so as to have a defect density of 1.times.10.sup.17 cm.sup. ^-3 or more. 2. The high-resistance region is formed by hydrogen ion irradiation with an irradiation energy of 4 MeV or more and 17 MeV or less and a dose amount of 2×10 ¹³ cm ⁻² or more and 2×10 ¹⁴ cm ⁻² or less. 3. The method for manufacturing the semiconductor device according to 2. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the heating time is 10 minutes or less. 5. The resistivity of the p-type silicon substrate before the ion irradiation is 100 Ωcm or less, and the resistivity of the high resistance region after the heating is 500 Ωcm or more. A method for manufacturing the semiconductor device according to the above item. 6. The high-resistance region according to claim 1, wherein the hydrogen density is 10 times or more and 50 times or less than the carrier concentration of the p-type silicon substrate before the ion irradiation. A method for manufacturing the semiconductor device according to item 1. 7. The method of manufacturing a semiconductor device according to claim 1, wherein said high resistance region has a p-type conductivity after said heating. A p-type silicon substrate, a semiconductor element provided on the p-type silicon substrate, and a high resistance region provided in the p-type silicon substrate,
The high-resistance region is a region having a hydrogen density of 5×10 ¹⁵ cm ⁻³ or more and 2×10 ¹⁷ cm ⁻³ or less and having a resistivity higher than that of the p-type silicon substrate. semiconductor equipment.

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