JP2015119039A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high resistance layer.SOLUTION: A manufacturing method of a semiconductor device 150 comprises the steps of: preparing a semiconductor substrate 158 where an element region 156 is formed on a principal surface 152; subsequently performing a predetermined number of times, ion irradiation from the side of a rear face 154 of the semiconductor substrate 158, which is on the opposite side to the principal surface 152 by changing acceleration energy to form a high resistance layer 160 having resistivity higher than that of an element region 156 at a non-element part 164 between the principal surface 152 and the rear face 154. The ion irradiation may be performed with a second acceleration energy lower than a first acceleration energy after performing ion irradiation with the first acceleration energy.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Conventionally, a semiconductor integrated circuit is manufactured by performing various fine processing on a substrate such as a silicon wafer. There are various performances required for such a substrate depending on applications and manufacturing processes. For example, a high resistance substrate is used as a means for blocking noise transmitted from a digital circuit to an analog circuit through the substrate or as a means for improving the Q value of an on-chip inductor (see, for example, Patent Document 1). ). As the high resistance substrate, for example, an SOI (Silicon On Insulator) substrate or a substrate manufactured by an FZ (Floating Zone) method with few impurities is used.

JP-A-2005-93828

  However, the SOI substrate or the high resistance substrate manufactured by the FZ method is expensive and increases the manufacturing cost of the semiconductor device. Even if a substrate having a high resistivity is used, impurities implanted in the process of manufacturing an element such as a transistor or a diode may diffuse in the subsequent heat treatment process, thereby reducing the resistivity of the substrate. As a result, even if an expensive substrate with a high resistivity is used, the resistivity may change during the manufacturing process of the semiconductor device, and the originally targeted resistivity may not be obtained.

  An exemplary object of an embodiment of the present invention is to provide a technique for realizing a semiconductor device having a high resistance layer.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to an aspect of the present invention provides a semiconductor substrate having an element region formed on a main surface, and then from the back side of the semiconductor substrate on the opposite side of the main surface. Ion irradiation is performed a plurality of times while changing the acceleration energy, and a high resistance layer having a higher resistivity than the element region is formed in the non-element portion between the main surface and the back surface.

  Another embodiment of the present invention is a semiconductor device. The apparatus includes a main surface including an element region, a back surface opposite to the main surface, and a non-element portion between the main surface and the back surface. The non-element portion includes a first lattice defect layer having a higher resistivity than the element region and a second lattice defect layer having a higher resistivity than the element region and a lower resistivity than the first lattice defect layer. The second lattice defect layer is provided at a position closer to the back surface than the first lattice defect layer.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, a semiconductor device having a high resistance layer is provided.

It is the figure which showed typically schematic structure of the ion irradiation system. It is a figure which shows an example of a conveyance plate. It is the figure which showed typically the irradiation image of the ion beam. It is the figure which showed typically sectional drawing of the wafer in which the high resistance layer is formed. It is a graph which shows an example of the relationship between the depth from the surface of the silicon wafer after ion irradiation, and a resistivity. 6A is a diagram illustrating a graph of three high resistance layers having different resistivity peak depths, and FIG. 6B is a diagram illustrating a graph of three high resistance layers having different half widths. It is. It is a figure which shows typically the wafer which formed the high resistance layer in the deep position. 8 is a graph schematically showing the relationship between the depth from the surface of the wafer shown in FIG. 7 and the resistivity. It is a figure which shows typically the wafer 24 which formed two high resistance layers by ion irradiation twice. 10 is a graph schematically showing the relationship between the depth from the surface of the wafer shown in FIG. 9 and the resistivity. 11A to 11D show an example of a method for manufacturing a semiconductor device according to a comparative example. 12A to 12D show an example of a method for manufacturing a semiconductor device according to the present embodiment. It is a graph which shows typically the change of the resistivity by heat processing. 3 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the present embodiment. 15A to 15D show an example of a method for manufacturing a semiconductor device according to a modification.

  In the method for manufacturing a semiconductor device according to the present embodiment, after preparing a semiconductor substrate with an element region formed on the main surface, ion irradiation is performed by changing acceleration energy from the back surface side of the semiconductor substrate on the opposite side of the main surface. Perform multiple times. Thus, a high resistance layer having a higher resistivity than the element region is formed in the non-element portion between the main surface and the back surface. By providing the high resistance layer, the element region and the non-element portion are separated, and the operation characteristics of the circuit element provided in the element region are improved.

  When the semiconductor substrate is irradiated with an ion beam, ions collide with atoms constituting the semiconductor substrate to generate a lattice defect, and a region having a high resistivity is formed by the generation of the defect. The position where the region with high resistivity is formed (peak position where the resistivity becomes high) is determined mainly by the ion species of the irradiated ions and the magnitude of the acceleration energy. The higher the acceleration energy, the deeper the position in the ion irradiation direction. It becomes. In the present embodiment, a plurality of lattice defect layers having different peak positions of resistivity are formed in an overlapping manner by performing ion irradiation a plurality of times while changing acceleration energy. Thereby, compared with the case where ion irradiation is performed only with predetermined acceleration energy, a thick high resistance layer having a wide width in the depth direction can be formed.

  Further, when the ion beam is irradiated, a region having a relatively high resistivity is formed also in a place where ions mainly pass before the peak position. A lattice defect layer (hereinafter also referred to as a second lattice defect layer) formed before the peak position is more resistant than a lattice defect layer (hereinafter also referred to as a first lattice defect layer) formed in the vicinity of the peak position. Although the rate is difficult to increase, the resistivity is higher than that of the semiconductor substrate before ion irradiation. In the present embodiment, by performing ion irradiation a plurality of times while changing the acceleration energy, ions are passed a plurality of times in the ion passage region before the peak position, thereby forming a relatively high resistivity region. Thereby, the width of the high resistance layer in the depth direction can be widened to make a thicker high resistance layer. By forming a thicker resistance layer, the operating characteristics of the circuit element provided in the element region can be improved.

  Hereinafter, embodiments for carrying out the present invention will be described in detail. In addition, the structure described below is an illustration and does not limit the scope of the present invention at all. In the description of the drawings, the same elements are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. In each cross-sectional view shown when explaining the manufacturing method, the thickness and size of the semiconductor substrate and other layers are for convenience of explanation, and do not necessarily indicate actual dimensions and ratios.

(Ion irradiation equipment)
First, an ion irradiation system that performs ion irradiation on a semiconductor substrate will be described. FIG. 1 is a diagram schematically showing a schematic configuration of an ion irradiation system. The ion irradiation system 10 includes an accelerator 12, a wafer transfer device 14 that holds and transfers a semiconductor wafer, and a beam transport duct 16 that guides an ion beam emitted from the accelerator 12 to the wafer transfer device 14.

  The accelerator 12 accelerates ions and emits them as an ion beam to the outside. As the accelerator 12, for example, a cyclotron type or a bandegraph type device is used. The wafer transfer apparatus 14 includes a storage unit (not shown) that stores a plurality of transfer plates 18, an irradiation chamber 20 that irradiates a wafer mounted on the transfer plate 18 with an ion beam, a storage unit, and an irradiation chamber 20. And a moving mechanism 22 that moves the transport plate 18 between the two. In the middle of the beam transport duct 16, a vacuum pump for maintaining the inside in a vacuum, an electromagnetic coil for correcting the beam direction, and the like are provided.

  FIG. 2 is a diagram illustrating an example of the transport plate. The transport plate 18 has a mounting portion 26 on which a plurality of wafers 24 are mounted. The wafer 24 is held at a predetermined position while being mounted on the mounting portion 26. The moving mechanism 22 sequentially irradiates all the wafers 24 mounted on one transport plate 18 with an ion beam, and when the ion irradiation processing is completed, the end 28a of the transport shaft 28 is moved to the end of the transport plate 18. The transported plate 18 is returned to the accommodating portion by engaging with the provided engaged portion 30. Then, the next transport plate 18 is moved to the irradiation chamber 20.

  FIG. 3 is a diagram schematically showing an irradiation image of the ion beam B. As shown in FIG. The direction of the ion beam B emitted from the accelerator 12 is changed by the action of the magnet 32. Then, by sequentially scanning the surface of the wafer 24 with the ion beam B, a predetermined region of the wafer 24 is irradiated with ions, and the high resistance layer 34 is formed. An aluminum absorber 36 is disposed in front of the irradiation surface of the wafer 24 in order to adjust the acceleration energy of the ion beam. For the absorber 36, for example, a metal foil such as an aluminum foil is used.

  Next, the high resistance layer 34 will be described. FIG. 4 is a diagram schematically showing a cross-sectional view of the wafer 24 on which the high resistance layer 34 is formed. As shown in FIG. 4, the high resistance layer 34 is formed at a predetermined depth of the wafer 24 by the ion beam B. The mechanism by which the high resistance layer is formed by ion irradiation is considered as follows.

  When the wafer is irradiated with ions, the ions reach a depth corresponding to the acceleration energy of the ions. At that time, lattice defects are formed in the vicinity including the reached region, and the regularity (periodicity) of the crystal is disturbed. In such a region having many lattice defects, electrons are easily scattered, and movement of electrons is hindered. That is, the resistivity increases in a region where local lattice defects are generated by ion irradiation. In the present specification, a region where local lattice defects are generated in the vicinity of the resistivity peak is also referred to as a “first lattice defect layer”.

  FIG. 5 is a graph showing an example of the relationship between the depth from the surface of the silicon wafer after ion irradiation and the resistivity. Here, the measured silicon wafer is obtained by slicing an N-type silicon single crystal (substrate resistivity: 4 Ω · cm) manufactured by a CZ (Czochralski) method. As the wafer according to the present embodiment, silicon carbide (SiC), gallium nitride (GaN), or the like can be used in addition to silicon (Si).

This N-type CZ silicon wafer is irradiated with ³ He ions, accelerated by a cyclotron accelerator at an energy of 23 MeV, passed through a moderator (aluminum foil) and adjusted to an ion implantation depth of 9 μm, with a dose of 1.0E + 13 cm ⁻² . Irradiated in quantity.

  As a result, as shown in FIG. 5, the change in the depth direction of the resistivity is a mountain-shaped function having a peak resistivity of 1000 Ω · cm at a depth of 9.5 microns. The half width at which the resistivity is half of the peak is around 9.2 μm. Here, the region included in the half width is referred to as a high resistance layer 34. Note that the definition of the high resistance layer 34 is not necessarily limited thereto, and may be a predetermined region having a higher resistivity than the surroundings. Further, a region having a resistivity higher than a predetermined resistivity required for design may be a high resistance layer.

  In addition, in order to form a high resistance layer in a predetermined area | region, it is realizable by selecting suitably the acceleration energy of ion irradiation, ion seed | species, and irradiation amount. FIG. 6A is a diagram showing a graph of three high resistance layers having different resistivity peak depths, and FIG. 6B is a diagram showing a graph of three high resistance layers having different half widths. .

  As shown in FIG. 6A, for example, the depth at which the high resistance layer is formed can be freely set by adjusting the acceleration energy of ions during ion irradiation. For example, the acceleration energy of ion irradiation may be 0.001 MeV or more. Or it is good also as acceleration energy of 0.1 MeV or more. Alternatively, ion irradiation may be performed with acceleration energy of 100 MeV or less. Or it is good also as acceleration energy of 30 MeV or less.

Further, as shown in FIG. 6B, for example, high-resistance layers having different half widths can be formed by appropriately selecting ion species used for ion irradiation. Examples of ion species used for ion irradiation include those in which at least one atom selected from the group consisting of H, He, B, C, N, O, Ne, Si, Ar, Kr, and Xe is ionized. . Specific examples include ¹ H ⁺ , ² H ⁺ , ³ He ²⁺ , ⁴ He ^{2+ and the} like.

  As described above, in the ion irradiation system 10, by adjusting the ion species, acceleration energy, and ion irradiation amount (beam current, irradiation time), the position, width, and resistance of the high resistance layer formed in a predetermined region in the wafer. The magnitude of the rate can be set as appropriate.

(Lattice defect layer in the ion passage region)
Next, the second lattice defect layer formed in the ion passage region will be described. FIG. 7 is a diagram schematically showing the wafer 24 in which the high resistance layer 34 is formed at a deep position. FIG. 8 is a graph schematically showing the relationship between the depth from the surface of the wafer 24 shown in FIG. 7 and the resistivity.

  As described above, when the ion beam B is irradiated on the wafer, the ions reach a depth corresponding to the acceleration energy of the ions, and a first lattice defect layer having a high resistivity is formed in the vicinity including the reached region. . On the other hand, also in the ion passage region 40 located before the region where ions reach, a region having a relatively high resistivity is formed by the ion beam acting on the atoms constituting the wafer. In particular, the resistivity of the ion passage region 40 can be increased by performing ion irradiation with high acceleration energy so that the ion beam reaches a deep position on the wafer.

  In the ion passage region 40, the resistivity is higher as it is closer to the peak position, and the resistivity is gradually lowered as the distance from the peak position is increased. The reason why such a resistivity distribution is obtained is considered to be that the probability that lattice defects are formed increases as the speed of ions passing therethrough decreases. In the present specification, a region where lattice defects occur in an ion passage region away from the resistivity peak is also referred to as a “second lattice defect layer”.

  Such a “second lattice defect layer” has a p-type dopant such as boron (B) or aluminum (Al) rather than an n-type substrate in which an n-type dopant such as phosphorus (P) or arsenic (As) is diffused. A p-type substrate in which is diffused is easier to form. In other words, the increase in resistivity in the ion passage region 40 tends to be larger in the p-type substrate than in the n-type substrate. Therefore, the second lattice defect layer in the ion passage region 40 may be utilized particularly when a high resistance layer is formed on a p-type substrate.

  A region ahead of the region where the high resistance layer 34 is formed becomes a non-reaching region 42 where the irradiated ion beam B does not reach or is difficult to reach. In this region, since lattice defects due to ion irradiation hardly occur, the region has a resistivity as low as that of the wafer 24 before ion irradiation. That is, the non-reaching region 42 is a region having a lower resistivity than the ion passage region 40.

  Next, a case where ion irradiation is performed a plurality of times while changing acceleration energy will be described. FIG. 9 is a diagram schematically showing a wafer 24 on which two high resistance layers 34a and 34b are formed by ion irradiation twice. In this figure, in order to form two high resistance layers 34a and 34b having different depth positions, ion irradiation is performed while changing acceleration energy. First, the first high resistance layer 34a provided at a relatively deep position is formed by ion irradiation with the first acceleration energy. Thereafter, the second high resistance layer 34b provided at a relatively shallow position is formed by ion irradiation with an acceleration energy lower than the first acceleration energy.

  FIG. 10 is a graph schematically showing the relationship between the depth from the surface of the wafer 24 shown in FIG. 9 and the resistivity. (A) of this figure shows the resistivity distribution when only ion irradiation with the first acceleration energy is performed, and (b) shows the resistivity distribution when only ion irradiation with the second acceleration energy is performed. . Similarly to the case shown in FIG. 8, in (a) and (b), there is a resistivity peak at the position where the first high-resistance layer 34a or the second high-resistance layer 34b is formed, and the first lattice is formed. A defective layer is formed. In addition, a second lattice defect layer having a higher resistivity than the non-reaching region 42 is formed in the ion passage region 40 located in front of the high resistance layer.

  FIG. 10C shows a resistivity distribution when ion irradiation is performed with the second acceleration energy after ion irradiation with the first acceleration energy. In this case, a high resistance layer having a large width in the depth direction is formed so as to cover both the regions where the first high resistance layer 34a and the second high resistance layer 34b are formed. This region corresponds to the first lattice defect layer. Moreover, in the partial region 40a close to the peak position in the ion passage region 40, a region having a resistivity as high as that in the vicinity of the peak position is formed. Although this region corresponds to the second lattice defect layer, a large number of lattice defects are formed also in the ion passage region 40 by a plurality of ion irradiations, so that the resistance is about the same as that of the first lattice defect layer. It is a high area.

  Thus, by performing ion irradiation a plurality of times while changing the acceleration energy, a first lattice defect layer having a wide width in the depth direction is formed, and a higher resistivity is provided adjacent to the first lattice defect layer. A two lattice defect layer can be formed. In particular, since the high resistance layer is formed not only in the region where the first lattice defect layer is formed but also in the ion passing region in the region close to the first lattice defect layer, the thickness of the high resistance layer is increased. be able to.

  When two high resistance layers with different peak positions are formed, after forming a high resistance layer at a relatively deep position by high energy ion irradiation, a high resistance layer is formed at a relatively shallow position by low energy ion irradiation. It is desirable to form a resistance layer. If this order is reversed, a high-energy ion beam for reaching a deep position passes through a high resistance layer formed at a shallow position. This is because the ion beam may be diffused or the arrival position may be changed due to the influence of the previously formed high resistance layer. Note that the order of ion irradiation is reversed, a high resistance layer is formed at a relatively shallow position by low energy ion irradiation, and then a high resistance layer is formed at a relatively deep position by high energy ion irradiation. It is good.

(Ion irradiation from the back side)
Next, the direction of ion beam irradiation will be described. In this embodiment mode, the high resistance layer is formed by ion irradiation from the back side of the semiconductor substrate. This is because when ion irradiation is performed from the main surface side where the element region is formed, the second lattice defect layer is formed in a region close to the main surface serving as the ion passage region, and the resistivity of the element region is increased. First, after showing about the high resistance layer formed when ion irradiation is performed from the main surface side as a comparative example, the case of ion irradiation from the back surface will be described as this embodiment.

  11A to 11D show an example of a manufacturing method of the semiconductor device 100 according to the comparative example, and show a manufacturing method in the case where ion irradiation is performed from the main surface side where the element region is formed. First, as shown in FIG. 11A, a semiconductor device 100 having an element region 106 formed on the main surface 102 is prepared. The semiconductor device 100 includes a substrate 108 having a main surface 102 and a back surface 104. An element region 106 is formed on the main surface 102.

  The element region 106 is provided in a surface layer portion of the substrate 108 including the main surface 102, and the main surface 102 can also be referred to as a process formation surface. The element region 106 is a circuit region including elements and / or wiring layers. The element region 106 extends in the horizontal direction on the main surface side of the substrate 108 and has a depth in the vertical direction.

  The element region 106 includes at least one circuit element (for example, an active element or a passive element). The element region 106 may include, for example, an RF-CMOS inductor. The element region 106 may include a so-called lateral semiconductor element having a current path formed in the lateral direction. The element region 106 may include at least one electronic circuit (analog circuit or digital circuit).

  A non-element portion 114 is provided between the main surface 102 and the back surface 104. The non-element portion 114 is located below the element region 106 and is provided between the element region 106 and the back surface 104. The non-element portion 114 can also be said to be a portion where a circuit element that forms the element region 106 is not provided.

  Next, as shown in FIGS. 11B and 11C, high resistance layers 110 a and 110 b are formed on the non-element portion 114 by irradiating the main surface 102 with ions. First, the first high resistance layer 110a is formed in a region away from the element region 106 in the non-element portion 114 by ion irradiation with the first acceleration energy. Thereafter, the second high resistance layer 110b is formed in a region near the element region 106 in the non-element portion 114 by ion irradiation with a second acceleration energy lower than the first acceleration energy. As a result, as shown in FIG. 11D, a thick high-resistance layer 110 having a width in the depth direction, in which the first high-resistance layer 110a and the second high-resistance layer 110b are stacked, is formed.

  On the other hand, since the ions irradiated to form the high resistance layer 110 pass through the element region 106, the element region 106 also becomes the ion passage region 112. Although the resistivity of the ion passage region 112 is not as high as that of the high resistance layer 110 on which the first lattice defect layer is formed, the resistivity rises higher than that of the substrate 108 before irradiation due to the formation of the second lattice defect layer. Then, due to the increase in resistivity, the responsiveness of the circuit element formed in the element region 106 may be reduced, or a part of the electric signal may be consumed as Joule heat due to the resistance component, resulting in signal loss. is there. Therefore, in the present embodiment, ion irradiation is performed from the back side where the element region is not formed so that the element region does not become an ion passage region.

  12A to 12D show an example of a method for manufacturing the semiconductor device 150 according to the present embodiment. Similar to the comparative example, as shown in FIG. 12A, a semiconductor device 150 having an element region 156 formed on the main surface 152 is prepared. Next, as shown in FIGS. 12B and 12C, high resistance layers 160 a and 160 b are formed on the non-element portion 164 by irradiating ions from the back surface 154 opposite to the main surface 152. First, the first high resistance layer 160a is formed in a region near the element region 156 in the non-element portion 164 by ion irradiation with the first acceleration energy. After that, the second high resistance layer 160b is formed in a region far from the element region 156 in the non-element portion 164 by ion irradiation with a second acceleration energy lower than the first acceleration energy. Thus, as shown in FIG. 12D, a thick high resistance layer 160 in which the first high resistance layer 160a and the second high resistance layer 160b are stacked is formed.

  In the present embodiment, unlike the comparative example, since the ion irradiation is performed from the back surface 154 side, the non-element portion 164 becomes the ion passage region 162. Since the second lattice defect layer is formed in the ion passage region 162, a region having a higher resistivity than the element region 156 is provided in the non-element portion 164 adjacent to the high resistance layer 160. Therefore, the second lattice defect layer formed in the ion passage region 162 contributes to increase the thickness of the high resistance layer 160 constituted by the first lattice defect layer. Thereby, compared with the case where a high resistance layer is formed only by a 1st lattice defect layer, a thick high resistance layer can be formed.

  Further, by avoiding ion irradiation from the main surface 152 side, an increase in resistivity of the element region 156 provided on the main surface 152 can be suppressed. This is because the element region 156 in this embodiment is located at the tip of the high resistance layer 160 in the direction in which the irradiation ions travel, and the ion beam hardly reaches and is a region in which lattice defects hardly occur. Thus, according to the present embodiment, by irradiating ions from the back surface side, a thick high resistance layer can be formed in the non-element portion 164 while suppressing an increase in the resistivity of the element region 156.

  On the other hand, when ion irradiation is performed from the back surface 154 side, it is necessary to select irradiation conditions so that ions reach a deeper position than when ion irradiation is performed from the main surface 152 side. This is because the element region 156 is provided in the vicinity of the main surface 152 and is formed at a relatively shallow position compared to the thickness of the substrate 158 (the width from the main surface 152 to the back surface 154). Therefore, in this embodiment, relatively light ions are irradiated with high energy. This is because ions can reach a deep position on the substrate 158 by irradiation with ions with high energy. In addition, by using relatively light ions, ions can reach a deeper position with a small acceleration energy as compared with the case of using heavy ions.

In this embodiment, for example, light ions such as hydrogen (H) and helium (He) are irradiated with acceleration energy of 5 MeV or more and 100 MeV or less. By using such irradiation conditions, ions can reach a position having a depth of 70 μm or more and 1500 μm or less in the silicon wafer. For example, if ³ He ions are irradiated with an acceleration energy of about 60 MeV, the ions can reach a position having a depth of 800 μm. Therefore, when a silicon wafer having a thickness of 800 μm is used, if a ³ He ion is irradiated with an acceleration energy of 60 MeV or less, a high resistance layer can be formed at a position close to the main surface even when irradiation is performed from the back surface side. it can. Further, by setting the acceleration energy to 5 MeV or more, the ion beam can reach a deep position.

  Note that the semiconductor device 150 described in this embodiment is, for example, a system LSI, an SOC (System On a Chip), or an integrated circuit (IC). The substrate 158 is a low-resistance semiconductor substrate, and for example, a wafer manufactured by the CZ method is used. A wafer manufactured by the CZ method has a lower resistivity and is less expensive than a high resistance wafer manufactured by the FZ method or the like. According to the present embodiment, even when a CZ wafer is used, a high resistance layer can be formed by ion irradiation, so that an increase in manufacturing cost can be reduced compared to the case where a high resistance wafer is used. it can.

  At this time, the resistivity of the substrate 158 is adjusted to, for example, 10 Ω · cm or less, 50 Ω · cm or less, 100 Ω · cm or less, 500 Ω · cm or less, or 1000 Ω · cm or less. The high resistance layer 160 formed on the substrate 158 has a peak resistivity (see, for example, FIG. 5) larger than the substrate resistivity before the high resistance layer 160 is formed on the substrate. Therefore, the peak resistivity of the high resistance layer 160 is, for example, greater than 10 Ω · cm, greater than 50 Ω · cm, greater than 100 Ω · cm, greater than 500 Ω · cm, or greater than 1000 Ω · cm.

  Note that by using a p-type substrate in which a p-type dopant is diffused as the substrate 158 constituting the semiconductor device 150, the resistivity of the ion passage region 162 can be made higher than in the case of using an n-type substrate. . The p-type substrate here does not mean whether or not the element region 156 contains a p-type dopant, but means that the non-element portion 164 to be the ion passage region 162 contains a p-type dopant. Say. In other words, the substrate 158 serving as a base before the element region 156 is formed is a p-type substrate. By using a p-type substrate as a base, the resistivity of the ion passage region 162 can be increased, and a thicker high-resistance layer can be formed with a smaller number of ion irradiations.

(Resistivity change by heat treatment)
Next, the temperature dependence of the high resistance layer will be described. FIG. 13 is a graph schematically showing changes in resistivity due to heat treatment. “Before processing” in the figure corresponds to (c) in FIG. “Heat treatment 1” indicates the resistivity distribution after the heat treatment at 200 ° C. for 1 hour, and “Heat treatment 2” indicates the resistivity distribution after the heat treatment at 400 ° C. for 1 hour. As shown, the resistivity does not change much before and after the heat treatment in the high resistance layers 34a and 34b where the first lattice defect layer is formed. On the other hand, in the ion passage region 40 where the second lattice defect layer is formed, it can be seen that the resistivity is reduced by the heat treatment.

  For this reason, considering the change in resistivity due to heat, even if the first lattice defect layer can be used as the high resistance layer, the second lattice defect layer is difficult to use. For example, when a high resistance layer is formed by a second lattice defect layer on a semiconductor device having an operation upper limit temperature of 200 ° C., the resistivity of the high resistance layer decreases when the semiconductor device is heated to 200 ° C. depending on the use environment. This is because the intended performance at the time of design may not be maintained. Therefore, in such a semiconductor device, it is considered that a normal design concept is to form the high resistance layer only by the first lattice defect layer without using the second lattice defect layer.

  However, the present inventor decided to adopt a method of stabilizing the resistivity of the second lattice defect layer by performing a heat treatment after forming the second lattice defect layer. In other words, in the present embodiment, the second lattice defect layer is formed by ion irradiation and then subjected to heat treatment, whereby the resistivity of the second lattice defect layer is lowered and stabilized. The temperature of the heat treatment is an upper limit temperature assumed when the semiconductor device is used, and is, for example, 100 ° C. or 200 ° C. In consideration of the decrease in resistivity due to heating, a high resistance layer is formed, and by performing heat treatment in advance, the resistivity of the high resistance layer is lowered afterwards if it is within the upper operating temperature range. Can be reduced. Thereby, while utilizing the high resistance layer by the 2nd lattice defect layer, the subsequent change of resistivity by heat can be controlled, and a highly reliable semiconductor device can be provided.

  Next, a process for forming the high resistance layer will be described. FIG. 14 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the present embodiment. First, elements are formed on the prepared silicon wafer by various processes (S10), and further, wiring is formed (S12). At this time, the resistivity of the substrate may decrease due to diffusion of impurities due to heat treatment. Here, the process in which the resistivity can change includes, for example, various heat treatments performed when elements such as diodes and transistors are formed and wirings (circuits) are formed. Examples of the heat treatment include thermal oxidation, thermal diffusion, CVD, annealing, and the like. Depending on these heat treatments, the substrate may reach 400 ° C. or higher, so if a high resistance layer is formed before this step, the resistivity of the high resistance layer formed will be greatly reduced. It might be.

  Therefore, in this embodiment, after these steps, a high resistance layer is formed by ion irradiation (S14). As described above, in this embodiment, an element formation process and a wiring (circuit) formation process involving heat treatment to the semiconductor substrate are performed before the high resistance layer formation process. That is, the formation of the high resistance layer by ion irradiation is performed after a process such as heat treatment that contributes to the change in resistivity. Thereby, a semiconductor device in which a desired resistivity is guaranteed can be manufactured.

  The semiconductor substrate on which the high resistance layer is formed is formed with a protective film (S16), the back surface is polished (S18), and then processed in a post-process (S20) including heat treatment to complete a semiconductor integrated circuit. The post-process includes, for example, a process of dicing the wafer into individual pieces, a process of connecting the separated chips and the mounting substrate by wire bonding, and a process of sealing the chips with resin. In this subsequent process, a heat treatment (annealing treatment) is performed to thermally stabilize the resistivity of the high resistance layer. For example, in the step of sealing the chip with a resin, the chip is heated to a temperature necessary for resin curing, thereby performing an annealing process while also serving as a sealing process. An annealing process may be performed as a process different from the resin sealing process.

  Although it is possible to form a high resistance layer after a post-process, etc., since various layers and members are formed on the semiconductor substrate in addition to the elements and wirings, ion irradiation conditions It becomes difficult to adjust. In addition, it is difficult to position and handle the separated chips when ion irradiation is performed. Therefore, after the step of forming the high-resistance layer, by performing protective film formation, back surface polishing, post-process, etc. that do not substantially change the resistivity, it is possible to save labor in the case of ion irradiation after singulation. Can do.

  As described above, the present invention has been described with reference to the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and the present invention can be appropriately combined or replaced with the configuration of the embodiment. It is included in the present invention. In addition, modifications such as various design changes in the ion irradiation system, the accelerator, the wafer transfer device, and the like in the embodiment can be added to the embodiment based on the knowledge of those skilled in the art. Added embodiments may be included in the scope of the present invention.

  In the above-described embodiment, the case where ion irradiation is performed twice while changing the acceleration energy of ions to be irradiated has been described. In a modification, it is good also as ion irradiation 3 times or more changing irradiation conditions. When the number of irradiations is increased by changing the acceleration energy, a plurality of high resistance layers constituted by the first lattice defect layers can be shifted and stacked, so that a thicker high resistance layer can be formed. Moreover, since the amount of passage increases through the ion passage region located in front of the first lattice defect layer, the region where the resistivity is increased by the second lattice defect layer can be increased.

  The ion irradiation may be performed only once without changing the acceleration energy. Also in this case, a high resistance layer having a wide width in the depth direction can be formed by laminating a high resistance layer including the first lattice defect layer and a high resistance layer including the second lattice defect layer.

  In the above-described embodiment, the high resistance layer is formed by ion irradiation from the back surface side. However, in a modified example, the high resistance layer may be formed by combining ion irradiation from the main surface side. . For example, when it is difficult to reach the vicinity of the element region by ion irradiation from the back due to constraints such as the performance of the accelerator, a thick high-resistance layer is obtained by performing ion irradiation from the main surface side in a complementary manner. Form.

  15A to 15D show an example of a method for manufacturing the semiconductor device 170 according to the modification. As in the embodiment, as shown in FIG. 15A, a semiconductor device 170 having an element region 176 formed on the main surface 172 is prepared. Next, as shown in FIGS. 15B and 15C, the first high resistance layer 180 a and the second high resistance layer are applied to the non-element portion 184 by irradiating ions from the back surface 174 opposite to the main surface 172. 180b is formed. The high resistance layers 180a and 180b formed by ion irradiation from the back surface 174 side are formed at a position away from the element region 176 due to insufficient performance of the accelerator. At this time, a region having a high resistivity is formed in the ion passage region 182 by forming the second lattice defect layer.

  Thereafter, as shown in FIG. 15D, the third high resistance layer 180c is formed in a region near the element region 176 by ion irradiation from the main surface 152 side. Since the region where the third high resistance layer 180c is formed is far from the back surface 174 but close to the main surface 172, the third high resistance layer 180c can be formed even by ion irradiation with relatively low acceleration energy. . Thus, by combining ion irradiation from the main surface side and ion irradiation from the back surface side, the thick high resistance layer 180 can be formed even when the performance of the accelerator is limited.

  Further, by combining the ion irradiation from the main surface side and the ion irradiation from the back surface side, it passes through the element region 176 as compared with the case where all the ion irradiation is performed from the main surface side in order to form the high resistance layer 180. The amount of ions irradiated can be reduced. Thereby, the influence that the resistivity of the element region 176 increases can be suppressed. The ion irradiation may be performed by irradiating ions from the main surface side after irradiating ions to the back surface side, or irradiating ions from the back surface side after irradiating ions to the main surface side.

  34 ... High resistance layer, 38 ... Semiconductor device, 100 ... Semiconductor device, 102 ... Main surface, 104 ... Back surface, 106 ... Element region, 108 ... Substrate, 110 ... High resistance layer, 114 ... Non-element portion, 150 ... Semiconductor device , 152 ... main surface, 154 ... back surface, 156 ... element region, 158 ... substrate, 160 ... high resistance layer, 164 ... non-element part, 170 ... semiconductor device, 172 ... main surface, 174 ... back surface, 176 ... element region, 178 ... substrate, 180 ... high resistance layer, 184 ... non-element portion.

Claims (10)

  After preparing a semiconductor substrate having an element region formed on the main surface, ion irradiation is performed a plurality of times while changing acceleration energy from the back surface side of the semiconductor substrate on the opposite side of the main surface, and the main surface and the back surface A high resistance layer having a higher resistivity than the element region is formed in a non-element portion between the semiconductor elements.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion irradiation is performed with a second acceleration energy lower than the first acceleration energy after the ion irradiation is performed with the first acceleration energy.   The semiconductor device according to claim 1, wherein the ion irradiation is performed with an acceleration energy that allows the irradiated ions to reach a position closer to the main surface than the back surface in the semiconductor substrate. Method.   The method of manufacturing a semiconductor device according to claim 1, wherein the ion irradiation is performed with an acceleration energy of 5 MeV to 100 MeV.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the ion species used for the ion irradiation is an ionized hydrogen (H) or helium (He) atom. 6.   6. The method of manufacturing a semiconductor device according to claim 1, wherein ion irradiation is further performed from the main surface side to form a high resistance layer in the non-element portion.   The method for manufacturing a semiconductor device according to claim 6, wherein the ion irradiation from the main surface side is performed with an acceleration energy lower than that of the ion irradiation from the back surface side.   The method for manufacturing a semiconductor device according to claim 1, wherein a heat treatment is performed on the semiconductor substrate after the high-resistance layer is formed.   9. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a p-type substrate in which a p-type dopant is diffused in the non-element portion. A main surface comprising an element region;
A back surface opposite to the main surface;
A non-element portion between the main surface and the back surface,
The non-element portion includes a first lattice defect layer having a higher resistivity than the element region, and a second lattice defect layer having a higher resistivity than the element region and a lower resistivity than the first lattice defect layer. Prepared,
The semiconductor device according to claim 1, wherein the second lattice defect layer is provided at a position closer to the back surface than the first lattice defect layer.

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