JP2017041598A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology that enables improvement of characteristics of an inductor element formed on a semiconductor substrate.SOLUTION: In a semiconductor device 10, a semiconductor substrate 12 has a first region E1 in which an impurity diffusion layer 13 is formed on a major surface 12a and a second region E2 in which a high resistance layer 50 having higher resistivity than the impurity diffusion layer 13 is formed on the major surface 12a. A lower wiring layer 37 is formed on the major surface 12a and includes at least one layer of an interlayer insulating film. An upper wiring layer 38 is formed on the lower wiring layer 37 and includes at least one layer of an interlayer insulating film. The inductor element 40 is formed at the upper wiring layer 38 on the second region E2 and has a wiring width a larger than a thickness of the lower wiring layer 37. The high resistance layer 50 may be formed by ion irradiation being performed to the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A semiconductor integrated circuit is manufactured by performing various fine processing on a substrate such as a silicon wafer. There are various performances required for such a substrate depending on applications and manufacturing processes. For example, a high resistance substrate is used as means for blocking noise transmitted from a digital circuit to an analog circuit through the substrate, or as means for improving the characteristics of an on-chip inductor. By forming an inductor on a high-resistance substrate, an inductor having a higher Q value than that obtained when a low-resistance substrate is used can be obtained (see, for example, Patent Document 1).

Special table 2007-536759 gazette

  The inductor formed on the semiconductor substrate is optimized for various parameters such as the loop shape of the wiring, its inner diameter, and the number of turns so that the inductance and Q value at a predetermined operating frequency become desired values. The Q value can be improved by combining an inductor optimized for a low resistance substrate and a high resistance substrate. However, in order to further improve the Q value, various parameters relating to the inductor are optimized for the high resistance substrate. It is desirable.

  One exemplary object of an aspect of the present invention is to provide a technique for improving the characteristics of an inductor element formed on a semiconductor substrate.

  A semiconductor device according to an aspect of the present invention includes a first region in which an impurity diffusion layer is formed on a main surface, and a second region in which a high resistance layer having a higher resistivity than the impurity diffusion layer is formed on the main surface. A semiconductor substrate, a lower wiring layer formed on the main surface and including at least one interlayer insulating film, an upper wiring layer formed on the lower wiring layer and including at least one interlayer insulating film, and a second region And an inductor element having a wiring width larger than the thickness of the lower wiring layer.

  Another aspect of the present invention is a method for manufacturing a semiconductor device. In this method, a semiconductor substrate having a first region in which an impurity diffusion layer is formed on a main surface and a second region different from the first region on the main surface is prepared, and at least one layer of interlayer insulation is formed on the main surface. Forming a lower wiring layer including a film; forming an upper wiring layer including at least one interlayer insulating film on the lower wiring layer; and forming a thickness of the lower wiring layer on the upper wiring layer above the second region. Forming an inductor element having a large wiring width, and irradiating the second region with ions to form a high resistance layer having a higher resistivity in the semiconductor substrate than before the ion irradiation.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, the characteristics of the inductor element formed on the semiconductor substrate can be improved.

It is sectional drawing which shows typically the structure of the semiconductor device which concerns on embodiment. It is a top view which shows typically the shape of an inductor element. It is sectional drawing which shows typically the structure of the semiconductor device which concerns on a comparative example. It is the equivalent circuit schematic of the inductor element which concerns on a comparative example. (A) is a graph which shows the Q value of the inductor element on a low resistance board | substrate, (b) is a graph which shows an inductance. It is an equivalent circuit diagram of the inductor element according to the embodiment. (A) is a graph which shows the Q value of the inductor element on a low resistance board | substrate and a high resistance board | substrate, (b) is a graph which shows an inductance. (A) is a graph which shows the Q value of an inductor element with a large wiring width on a high resistance substrate, and (b) is a graph which shows an inductance. It is a figure which shows the manufacturing process of a semiconductor device typically. It is a figure which shows the manufacturing process of a semiconductor device typically. It is a graph which shows an example of the resistivity distribution of the semiconductor substrate after ion irradiation. It is a graph which shows an example of the resistivity distribution of the semiconductor substrate after ion irradiation. It is a graph which shows an example.

  Hereinafter, embodiments for carrying out the present invention will be described in detail. In addition, the structure described below is an illustration and does not limit the scope of the present invention at all. In the description of the drawings, the same elements are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. In each cross-sectional view referred to in the following description, the thickness and size of the semiconductor substrate and other layers are for convenience of description, and do not necessarily indicate actual dimensions and ratios.

  FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is an integrated circuit (IC) such as a system LSI or a system on a chip (SoC). The semiconductor device 10 includes an inductor element 40 (so-called on-chip inductor) formed on the semiconductor substrate 12.

  In the present embodiment, the high resistance layer 50 is formed under the inductor element 40 by irradiating the semiconductor substrate 12 with ions. Further, the inductor element 40 is formed so that the wiring width a is larger than the optimum value of the wiring width when the inductor element is formed on the low resistance substrate. Thereby, the Q value of the inductor element 40 is improved.

  The semiconductor device 10 includes a semiconductor substrate 12 and a multilayer wiring layer 30 formed on the main surface 12 a of the semiconductor substrate 12. The semiconductor substrate 12 is a low-resistance semiconductor substrate having a resistivity of 100 Ω · cm or less, for example, a silicon (Si) wafer manufactured by the Czochralski (CZ) method. A wafer manufactured by the CZ method has a lower resistivity and is less expensive than a high resistance wafer manufactured by a floating zone (FZ) method or the like. In this embodiment, since the high resistance layer is formed by ion irradiation to the low resistance substrate, the cost can be reduced as compared with the case where the high resistance substrate manufactured by the FZ method or the like is used.

  The semiconductor substrate 12 has a first region E1 in which the impurity diffusion layer 13 is formed on the main surface 12a, and a second region E2 in which the high resistance layer 50 is formed on the main surface 12a. The first region E1 is a region where semiconductor elements such as transistors 20 and diodes are mainly formed. The second region E2 is a region where the inductor element 40 is formed thereon. In this specification, a direction perpendicular to the main surface 12a of the semiconductor substrate 12 is referred to as a vertical direction or a thickness direction, and a direction toward the main surface 12a when viewed from the semiconductor substrate 12 is an upper direction or an upper side, and the main surface 12a. The direction toward the back surface 12b opposite to that may be referred to as a downward direction or a lower side. In addition, a direction parallel to the main surface 12a may be referred to as a horizontal direction or a horizontal direction.

  The transistor 20 is a field effect transistor (FET), and is formed by a well region 14, a source region 15, a drain region 16, a gate electrode 17, and a gate insulating film 18. For example, the impurity diffusion layers 13 such as the well region 14, the source region 15, and the drain region 16 are implanted with an impurity element such as boron (B) or phosphorus (P) into the main surface 12 a of the semiconductor substrate 12 by a technique such as ion implantation. Is formed. A gate insulating film 18 is formed on the impurity diffusion layer 13, and a gate electrode 17 is provided thereon. An element isolation region 22 that isolates semiconductor elements is provided adjacent to the impurity diffusion layer 13.

  In the present embodiment, a transistor having a lateral structure in which the source region 15 and the drain region 16 are formed in the vicinity of the main surface 12a is shown as the transistor 20, but a semiconductor element having a different structure is formed in the modification. Also good. For example, a transistor having a vertical structure in which the drain region is provided on the back surface 12b side of the semiconductor substrate 12 may be provided. As the transistor 20, a bipolar transistor may be provided instead of the FET.

  A multilayer wiring layer 30 is formed on the main surface 12 a of the semiconductor substrate 12. The multilayer wiring layer 30 includes an upper wiring layer 38 provided with the inductor element 40 and a lower wiring layer 37 positioned below the upper wiring layer 38. The multilayer wiring layer 30 includes a plurality of interlayer insulating films, and includes, for example, three layers of interlayer insulating films 31 to 33 as illustrated.

  The first insulating film 31 formed immediately above the main surface 12a has a contact 25 extending in the vertical direction and connected to the source region 15 and the drain region 16 of the transistor 20, and extending in the horizontal direction between the contacts 25. A wiring 24 to be connected is provided. The second insulating film 32 formed immediately above the first insulating film 31 is provided with wirings 24 extending in the horizontal direction and vias 26 extending in the vertical direction for connecting the wirings 24 formed in different layers. .

  A third insulating film 33 is formed on the second insulating film 32. The third insulating film 33 is the uppermost interlayer insulating film, and the inductor element 40 is formed on the second region E2. The third insulating film 33 may be provided with a wiring extending in the horizontal direction and a via extending in the vertical direction, or may be provided with a pad serving as a connection terminal with the outside of the semiconductor device 10.

  The upper wiring layer 38 is a wiring layer in which the inductor element 40 is formed, and is constituted by the third insulating film 33 as shown in the figure. The thickness d3 of the upper wiring layer 38 is, for example, about 3 to 10 μm. The lower wiring layer 37 is a wiring layer in which the inductor element 40 located below the upper wiring layer 38 is not formed, and is constituted by the first insulating film 31 and the second insulating film 32. The thickness d2 of the lower wiring layer 37 is, for example, about 5 to 10 μm.

  In the present embodiment, the case where the first insulating film 31, the second insulating film 32, and the third insulating film 33 are provided one by one is illustrated, but the lower wiring layer 37 and the upper wiring layer 38 are further increased. An interlayer insulating film may be used. For example, the lower wiring layer 37 may include a plurality of second insulating films 32, and the upper wiring layer 38 may be configured of a plurality of third insulating films 33.

  A high resistance layer 50 is provided in the second region E <b> 2 of the main surface 12 a of the semiconductor substrate 12. The high resistance layer 50 is a region having a higher resistivity than the body region 12d of the semiconductor substrate 12 and the impurity diffusion layer 13, and has a resistivity of 100 Ω · cm or more. The resistivity of the high resistance layer 50 is, for example, 500 Ω · cm or more, and preferably 1 kΩ · cm or more.

  The high resistance layer 50 is formed to have a certain thickness from the main surface 12a of the semiconductor substrate 12 toward the opposite back surface 12b. The thickness d1 of the high resistance layer 50 is formed to be larger than the thickness d2 of the lower wiring layer 37 and the thickness d3 of the upper wiring layer 38. The high resistance layer 50 has a thickness of 20 μm or more, and preferably has a thickness of about 50 μm to 200 μm. By increasing the thickness d1 of the high resistance layer 50, the Q value of the inductor element 40 formed on the high resistance layer 50 can be further increased.

  The high resistance layer 50 is formed by irradiating a low resistance substrate with an ion beam. When the wafer is irradiated with ions, the ions reach a depth corresponding to the acceleration energy of the ions. At that time, lattice defects are formed in the vicinity including the reached region, and the regularity (periodicity) of the crystal is disturbed. In such a region having many lattice defects, electrons are easily scattered, and movement of electrons is hindered. That is, the resistivity increases in a region where local lattice defects are generated by ion irradiation. In this way, the high resistance layer 50 can be formed.

  The position and range in the thickness direction where the resistivity is increased by ion irradiation can be adjusted by appropriately selecting the acceleration energy, ion species, and dose of ion irradiation. For example, the position (depth) in the thickness direction where the high resistance layer is formed can be adjusted by adjusting the acceleration energy of ions when ion irradiation is performed. Moreover, the range (half width) in the thickness direction in which the high resistance layer is formed can be adjusted by appropriately selecting the ion species used for ion irradiation. Furthermore, a thicker high-resistance layer can be formed by performing ion irradiation a plurality of times while changing the acceleration energy.

  In this embodiment, for example, light ions such as hydrogen (H) and helium (He) are irradiated with acceleration energy of 5 MeV or more and 100 MeV or less. As an apparatus for irradiating an ion beam with such acceleration energy, a cyclotron system or a bandegraph system is used. By using such irradiation conditions, ions can reach the position of the depth of 100 μm or more from the vicinity of the main surface 12a of the semiconductor substrate 12 in the silicon wafer.

  FIG. 2 is a top view schematically showing the shape of the inductor element 40. The inductor element 40 is formed of a strip-shaped conductor such as aluminum (Al) or copper (Cu) extending in a loop shape in the upper wiring layer 38. As shown in the figure, the inductor element 40 is formed so that the inner and outer shapes are square, and the number of turns of the coil is one. Therefore, the wiring length l of the inductor element 40 is expressed as 1≈4 (a + b) using the wiring width a and the inner diameter b.

  The inductor element 40 may be formed so that the outer shape of the loop is circular or octagonal, or may be formed so that the number of turns of the loop is plural. When the number of turns is plural, the strip-like conductors forming the loop may be formed on the same interlayer insulating film or different interlayer insulating films. Further, the belt-like conductor may be formed in a spiral shape or may be formed like a string spring. Various parameters such as the outer shape, the wiring width a, the inner diameter b, and the number of turns are optimized so that the inductor element 40 has desired inductance L and Q values at a predetermined operating frequency.

  The inductor element 40 according to the present embodiment improves the characteristics on the high resistance substrate by increasing the wiring width a among the parameters optimized when the inductor element is formed on the low resistance substrate. In particular, by making the wiring width a larger than the thickness d2 of the lower wiring layer 37 located between the upper wiring layer 38 on which the inductor element 40 is formed and the semiconductor substrate 12, the inductor element 40 at a predetermined operating frequency. Improve the Q value.

  Hereinafter, the reason why the Q value is increased by increasing the wiring width a of the inductor element 40 on the high resistance substrate will be described. First, frequency characteristics of an inductor element formed on a low resistance substrate will be described with reference to FIGS. Next, frequency characteristics of the inductor element formed on the high resistance substrate will be described with reference to FIGS.

  FIG. 3 is a cross-sectional view schematically showing the structure of the semiconductor device 110 according to the comparative example. In the comparative example, the high resistance layer is not provided on the semiconductor substrate 112 below the inductor element 140, and the inductor element 140 is formed in the multilayer wiring layer 130 on the body region 112d having a low resistance.

FIG. 4 is an equivalent circuit diagram of the inductor element 140 according to the comparative example. R _L represents the resistance component of the inductor element 140, and L represents the inductance component of the inductor element 140. C _OX is the capacitance component of the interlayer insulating film between the semiconductor substrate 112 and the inductor element 140, C _sub is the capacitance component of the semiconductor substrate 112 located under the inductor element 140, and R _sub is the resistance of the semiconductor substrate 112. Represents an ingredient. The frequency characteristic of the Q value of the inductor element 140 can be expressed by the following formula (1) using this equivalent circuit. _{C 0} in an expression (1) is represented by the formula (2).

  FIG. 5 is a graph showing frequency characteristics of the inductor element 140 on the low-resistance substrate, where (a) shows the Q value and (b) shows the inductance L. This figure shows the simulation results when the wiring width a is 6 μm, 9 μm, 15 μm, and 30 μm for the inductor element 140 having the shape of FIG. 2 arranged on the low resistance substrate. In the simulation shown in this figure, the parameters of the inductor element 140 are determined with a target of 5 GHz as the predetermined operating frequency. The inner diameter b is 100 μm to 150 μm, and the inner diameter b is adjusted so that the inductance L is constant with respect to the change in the wiring width a. Specifically, when the wiring width a is increased, the inner diameter b is also increased.

As shown in FIG. 5 (a), the frequency omega _Q where Q value of the inductor element 140 is maximum decreases as the wire width a is increased. Similarly, the self-resonant frequency ω _{SP at} which the Q value of the inductor element 140 becomes zero also decreases as the wiring width a increases. Further, the ratio of the frequency ω _{Q at} which the Q value is maximized to the self-resonant frequency ω _SP is ω _Q / ω _SP = 0.1 to 0.4. This is considered to be caused by the fact that the resistance component R _sub and the capacitance component C _sub related to the semiconductor substrate 112 are included in the expression (1) representing the characteristics of the inductor element 140.

  From the simulation results shown in the figure, it can be seen that the inductor element 140 having the maximum Q value at 5 GHz has a wiring width a = 15 μm. On the other hand, the Q value at 5 GHz is not so different when the wiring widths a = 6 μm, 9 μm, and 15 μm are compared. It is desirable to reduce the size of the on-chip inductor in order to reduce the area occupied on the substrate. Therefore, when there is no significant difference in the Q value, the inductor element parameter may be determined by giving priority to the reduction of the occupied area over the maximization of the Q value. Therefore, it may be desirable to select the wiring width a = 6 μm as the optimum inductor element for the operating frequency of 5 GHz.

FIG. 6 is an equivalent circuit diagram of the inductor element 40 according to the embodiment. In the present embodiment, since the high resistance layer 50 is formed under the inductor element 40, the influence of the semiconductor substrate 12 can be ignored. Therefore, in this embodiment, the inductor element 40 can be represented by the equivalent circuit of FIG. 6 in which the resistance component R _sub and the capacitance component C _sub related to the substrate are removed from the equivalent circuit according to the comparative example of FIG. At this time, the frequency characteristic of the Q value of the inductor element 40 can be expressed by the following equation (3) using the equivalent circuit of FIG. In addition, C contained in Formula (3) is _COX of FIG.

  FIG. 7 is a graph showing the frequency characteristics of the inductor elements on the low resistance substrate and the high resistance board, and shows the frequency characteristics of the inductor elements having a wiring width a = 6 μm. This figure shows a simulation result for an inductor element having the same shape as that of the wiring width a = 6 μm shown in FIG. As shown in FIG. 7A, it can be seen that the Q value increases in almost all frequency bands by using the high resistance substrate. Further, as shown in FIG. 7B, it can be seen that the inductance L at the operating frequency is the same both when the low resistance substrate is used and when the high resistance substrate is used. Thus, by switching from the low resistance substrate to the high resistance substrate, the Q value can be improved while the inductance L of the inductor element is kept constant.

On the other hand, as shown in FIG. 7A, when a high-resistance substrate is used, the self-resonant frequency ω _SP becomes the same, while the frequency at which the Q value becomes maximum is changed from ω _{Q1 of the} low-resistance substrate to the high-resistance substrate. It turns out that it becomes large at ω _Q2 . Specifically, when a low resistance substrate is used, ω _Q / ω _SP = 0.1 to 0.4, whereas when a high resistance substrate is used, ω _Q / ω _SP = 0.5 to 0.7. As a result, when a high resistance substrate is used with the same wiring width a, the frequency at which the Q value is maximized deviates from the target operating frequency (for example, 5 GHz). If the inductor element is used at an operating frequency that deviates from the frequency at which the Q value is maximized, the effect of improving the Q value by using a high-resistance substrate may be limited.

FIG. 8 is a graph showing the frequency characteristics when an inductor element having a large wiring width a is formed on a high resistance substrate. The frequency characteristics of the inductor element 40 having a wiring width a = 15 μm formed on the high resistance substrate are shown. Show. As shown in FIG. 8B, the shape of the inductor element 40 is determined so that the inductance L at the operating frequency is the same even in the wiring width a = 15 μm. As shown in FIG. 8A, the self-resonant frequency ω _SP3 at the wiring width a = 15 μm is smaller than the self-resonant frequency ω _{SP at the} wiring width a = 6 μm, and the frequency ω at which the Q value becomes maximum. _Q3 also is smaller than the frequency ω _Q2. As a result, the frequency ω _Q3 with the maximum Q value can be brought close to the target operating frequency (5 GHz), and the Q value at the operating frequency can be greatly improved.

  Thus, according to the present embodiment, the wiring width (for example, twice or more) is larger than the wiring width (for example, a = 6 μm) optimized when the inductor element is formed on the low-resistance substrate. By setting a = 15 μm), the characteristics on the high resistance substrate can be improved. Particularly, the wiring width (for example, a = 15 μm) larger than the thickness d2 (for example, 5 to 10 μm) of the lower wiring layer 37 located between the upper wiring layer 38 in which the inductor element 40 is formed and the semiconductor substrate 12 is used. By doing so, the Q value of the inductor element 40 at a predetermined operating frequency (for example, 5 GHz) can be significantly increased.

Note that the inductor element 40 formed with the wiring width a = 15 μm on the high resistance substrate shown in FIG. 8 may be used as an inductor targeting a frequency of about 10 GHz. For example, it may be used as an inductor that targets a frequency higher than the frequency ω _Q3 (about 9 GHz) at which the Q value is maximum. Even in such a frequency band, an inductor element with high performance can be provided by combining a larger wiring width and a high resistance substrate.

  Next, a method for manufacturing the semiconductor device 10 according to the present embodiment will be described.

  FIG. 9 is a diagram schematically showing the manufacturing process of the semiconductor device 10 and shows a state before the high resistance layer is formed. A well region 14, a source region 15, a drain region 16, a gate electrode 17, a gate insulating film 18, and an element isolation region 22 are formed in the first region E1 of the main surface 12a of the semiconductor substrate 12, and a semiconductor such as a transistor 20 is formed. An element is formed.

  Next, the first insulating film 31 is laminated on the main surface 12 a, the insulating film where the wiring 24 and the contact 25 are formed is removed, and a metal layer that forms the wiring 24 and the contact 25 is provided. Subsequently, the second insulating film 32 is laminated on the first insulating film 31, the insulating film where the wiring 24 and the via 26 are formed is removed, and a metal layer that forms the wiring 24 and the via 26 is provided. . Thereby, the lower wiring layer 37 is completed.

  Further, the third insulating film 33 is laminated on the second insulating film 32, the insulating film at the portion where the inductor element 40 is formed in the second region E2 is removed, and a metal layer for forming the inductor element 40 is provided. . The inductor element 40 is formed such that the wiring width a is larger than the thickness d2 of the lower wiring layer 37. Thereby, the upper wiring layer 38 is completed.

  FIG. 10 is a diagram schematically showing a manufacturing process of the semiconductor device 10 and shows a state in which the high resistance layer 50 is formed by ion irradiation. A mask 60 is disposed on the multilayer wiring layer 30 formed by the process shown in FIG. 9, and the ion beam IB is irradiated from above the mask 60 toward the semiconductor substrate 12. The mask 60 has an opening 62 in a region corresponding to the second region E2, and allows the ion beam IB toward the second region E2 to pass therethrough and shields the ion beam IB toward the first region E1. By shielding the ion beam IB toward the first region E1, the resistivity of the impurity diffusion layer 13 such as the well region 14, the source region 15, and the drain region 16 forming the transistor 20 is prevented from being increased by ion irradiation. By keeping the resistivity of the impurity diffusion layer 13 low, it is possible to prevent the characteristics of the semiconductor element such as the transistor 20 from being deteriorated.

  A high resistance layer 50 is formed in the second region E2 of the semiconductor substrate 12 irradiated with the ion beam IB. As illustrated, the high resistance layer 50 includes a plurality of high resistance regions 51 to 53. The first high resistance region 51 formed in the vicinity of the main surface 12a is formed by irradiating the ion beam IB having low acceleration energy. The third high resistance region 53 away from the main surface 12a in the thickness direction is formed by irradiating the ion beam IB having high acceleration energy. The second high resistance region 52 formed between the first high resistance region 51 and the third high resistance region 53 is formed by irradiating the ion beam IB having a medium acceleration energy. Thus, by irradiating the ion beam IB a plurality of times while changing the acceleration energy, the thickness d1 of the high resistance layer 50 can be increased. Further, by irradiating ions from the main surface 12 a side of the semiconductor substrate 12, a high resistance region can be formed in the vicinity of the main surface 12 a, that is, immediately below the multilayer wiring layer 30.

  After the high resistance layer 50 is formed by the process shown in FIG. 10, the semiconductor substrate 12 may be subjected to heat treatment. The temperature of the heat treatment is an operation upper limit temperature assumed when the semiconductor device is used, and is, for example, 100 ° C. or 200 ° C. The heat resistance causes a change in resistivity in a partial region of the high resistance layer 50, and the resistivity decreases depending on the location. By performing the heat treatment in advance, when the semiconductor device 10 is used within the range of the operation upper limit temperature, it is possible to reduce the influence that the resistivity of the high resistance layer is subsequently lowered. Thereby, a subsequent change in resistivity can be suppressed, and the reliability of the semiconductor device 10 can be improved.

  Such heat treatment includes a step of dicing the wafer into individual pieces, a step of connecting the separated chips and the mounting substrate with wire bonds, and a step of sealing the chips with a resin, so-called. You may perform in a "post process." For example, in the step of sealing the chip with a resin, the chip can be heated to a temperature necessary for resin curing to perform heat treatment while also serving as a sealing process. In addition, you may heat-process as a process different from a resin sealing process.

FIG. 11 is a graph showing an example of the resistivity distribution of the semiconductor substrate after ion irradiation. This figure shows the result when ³ He ²⁺ ions are irradiated at a dose of 10 ¹³ / cm ² at depths of 13 μm, 28 μm, and 48 μm from the main surface of the semiconductor substrate. As shown, the resistivity of the substrate increases from about 30 Ω · cm to about 3 kΩ · cm in the range from the main surface to a depth of about 60 μm. It can also be seen that a high resistance layer of about 2 kΩ · cm or more is formed with a thickness of about 60 μm even when heat treatment is applied after ion irradiation. In this way, a thick high resistance layer can be formed by irradiating the ion beam at different depth positions while changing the acceleration energy.

In order to form a thicker high-resistance layer, ion beam irradiation from the back surface may be combined. FIG. 12 is a graph showing an example of the resistivity distribution of the semiconductor substrate after ion irradiation, and shows the result when combining ion irradiation from the main surface and ion irradiation from the back surface. In this figure, ions of ³ He ²⁺ are irradiated at a dose of 10 ¹³ / cm ² at positions 40 μm and 140 μm deep from the main surface side of the semiconductor substrate, and at a position 60 μm deep from the back surface side of the semiconductor substrate. The result at the time of irradiating the ion of ³ He ^<2+ > by the dose amount of 10 < ¹³ > / cm < ² > is shown. As shown, the resistivity of the substrate increases from about 3 Ω · cm to about 1 kΩ · cm or more in the range from the main surface to a depth of about 150 μm. In addition, even after the heat treatment, it can be seen that the substrate has a high resistance layer having a resistivity of about 1 kΩ · cm in most regions from the main surface to a depth of about 150 μm. In this way, a thicker high resistance layer can be formed by irradiating the ion beam at different depth positions by changing the acceleration energy and combining the ion beam irradiation from the back surface.

  When the ion beam is irradiated from the back surface, a mask 60 as shown in FIG. 9 may be arranged on the back surface 12b so that the second region E2 is selectively irradiated with ions, or the mask 60 is not provided. May be irradiated with ions. When the ion beam is irradiated from the back surface, ions hardly reach the vicinity of the main surface 12a of the first region E1 where the semiconductor element such as the transistor 20 is formed. Therefore, even when ion irradiation is performed without providing a mask, the high resistance layer can be formed with less influence on a semiconductor element such as the transistor 20.

  Note that when irradiating an ion beam to different depth positions by changing acceleration energy, boron (B) or more than an n-type substrate in which an n-type dopant such as phosphorus (P) or arsenic (As) is diffused. A p-type substrate in which a p-type dopant such as aluminum (Al) is diffused is easier to form a high resistance layer. In other words, the amount of increase in resistivity is likely to be greater in a p-type substrate than in an n-type substrate. Therefore, a thicker high resistance layer can be formed by using a p-type substrate.

  The present invention has been described based on the embodiments. It is understood by those skilled in the art that the present invention is not limited to the above-described embodiment, and various design changes are possible, and various modifications are possible, and such modifications are within the scope of the present invention. It is a place.

  In the above-described embodiment, the case where the ion irradiation is performed three times while changing the acceleration energy of the irradiated ions has been described. In a modification, ion irradiation may be performed only once without changing acceleration energy, or ion irradiation may be performed twice or four times or more by changing irradiation conditions. By changing the acceleration energy and increasing the number of irradiations, a thicker high resistance layer can be formed and the characteristics of the inductor element can be improved. On the other hand, by reducing the number of irradiations, the cost for ion irradiation can be reduced. Therefore, it is desirable that the number of ion irradiations is appropriately adjusted according to the thickness of the high resistance layer required for the inductor element. Specifically, it is desirable to adjust the number of ion irradiations in the range of about 2 to 7 times.

  In the above embodiment, the high resistance layer is formed by irradiating the low resistance substrate with ions. In the modification, a high resistance substrate may be used as the semiconductor substrate, or a high resistance layer is formed by forming a buried oxide film (BOX) under the region where the inductor element is formed. May be. Even when such a high resistance layer is used, the Q value can be improved by increasing the wiring width of the inductor element.

  E1 ... first region, E2 ... second region, 10 ... semiconductor device, 12 ... semiconductor substrate, 12a ... main surface, 12b ... back surface, 13 ... impurity diffusion layer, 24 ... wiring, 30a ... main surface, 37 ... lower wiring Layer, 38 ... upper wiring layer, 40 ... inductor element, 50 ... high resistance layer, a ... wiring width.

Claims (12)

A semiconductor substrate having a first region in which an impurity diffusion layer is formed on a main surface and a second region in which a high-resistance layer having a higher resistivity than the impurity diffusion layer is formed on the main surface;
A lower wiring layer formed on the main surface and including at least one interlayer insulating film;
An upper wiring layer formed on the lower wiring layer and including at least one interlayer insulating film; and
A semiconductor device comprising: an inductor element formed in the upper wiring layer on the second region and having a wiring width larger than a thickness of the lower wiring layer.   The semiconductor device according to claim 1, wherein the high resistance layer is formed by ion irradiation on the semiconductor substrate.   The semiconductor device according to claim 1, wherein a thickness of the high resistance layer is larger than a thickness of the wiring layer.   4. The inductor element according to claim 1, wherein a frequency at which a Q value of the inductor element is maximum is 0.5 to 0.7 times a self-resonance frequency of the inductor element. 5. A semiconductor device according to 1.   The wiring width of the inductor element is larger than a wiring width optimized when the inductor element is formed on a low resistance substrate of 100 Ω · cm or less. The semiconductor device described. Providing a semiconductor substrate having a first region where an impurity diffusion layer is formed on a main surface and a second region different from the first region on the main surface;
Forming a lower wiring layer including at least one interlayer insulating film on the main surface;
Forming an upper wiring layer including at least one interlayer insulating film on the lower wiring layer;
Forming an inductor element having a wiring width larger than the thickness of the lower wiring layer in the upper wiring layer on the second region;
And irradiating the second region with ions to form a high resistance layer having a higher resistivity than before ion irradiation in the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 6, wherein forming the high resistance layer includes irradiating ions from the main surface side toward the semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 7, wherein forming the high resistance layer includes irradiating ions a plurality of times while changing acceleration energy from the main surface side toward the semiconductor substrate. .   9. The method of manufacturing a semiconductor device according to claim 7, wherein forming the high resistance layer further includes irradiating ions from a back surface side of the semiconductor substrate on the opposite side of the main surface. .   The semiconductor device according to claim 8, wherein forming the high resistance layer includes irradiating ions from above the upper wiring layer after forming the inductor element. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 6, further comprising performing a heat treatment on the semiconductor substrate after forming the high-resistance layer.   The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is formed using a p-type substrate formed by a Czochralski (CZ) method.

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