JPH10199894A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and manufacture thereof, wherein the reduction of the turn-off time and on-resistance rise avoidance are attained at a high level. SOLUTION: Near the interface between drift regions 102 and substrate 101, lattice defects are distributed at a high concn. to sufficiently increase the half-value width of that distribution to involve nondepletion regions 102b of the drift regions 102 in the defect regions but not to extend the defect regions to a diffusion layer 109. This reduces the turn-off time, without raising the on-resistance. Using an absorber with stepped portions, such a defect distribution can be realized by a one-time ion irradiation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device for controlling switching of a current in a thickness direction and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device having improved turn-off response while suppressing an increase in on-resistance, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a so-called insulated gate bipolar transistor (hereinafter referred to as "IGBT") in which a bipolar transistor and a field-effect transistor are integrated has been used in applications requiring high input impedance and low output impedance. Used in

The general structure of an IGBT will be described with reference to FIG. The general IGBT shown in FIG. 15 is composed of an n epitaxial layer 20 on a p ⁺ type silicon (Si) substrate 201.
The n ⁺ source region 206 formed by ion implantation or the like and the p ⁺
Body region 207 and p ⁺ body region 209 are provided. P body region 20 of n epitaxial layer 202
The portion other than 7th grade is the n drift region 202d. On the surface of the n-type epitaxial layer 202, a gate electrode 204 insulated from the n-type epitaxial layer 202 by a gate insulating film 203, insulating films 205 and 208 is provided. Gate electrode 204 has a portion of n drift region 202d, a portion of p body region 207, and a portion of n ⁺ source region 20 of the surface of n epitaxial layer 202.
6 and a part of it. Further, on the front surface side, a source electrode 210 that conducts to n ⁺ source region 206 and p ⁺ body region 209 is provided. On the back side, a drain electrode 2 for conducting to the p ⁺ substrate 201
11 are provided.

In the IGBT having this structure, the gate electrode 204, the n ⁺ source region 206, the p body region 207, and the n drift region 202d constitute a field effect transistor. That is, p body region 207 is a channel region, and n drift region 202d is a drain region. Then, the p ⁺ body region 209 and the n drift region 2
02d and the p ⁺ substrate 201 constitute a bipolar transistor (pnp). That is, p ⁺ body region 20
9 is a collector, an n drift region 202d also serving as a drain region of the field effect transistor is a base,
The p ⁺ substrate 201 is the emitter.

The operation of the IGBT having this structure is to control the switching of the current from the drain electrode 211 to the source electrode 210 by the voltage of the gate electrode 204. That is, in a state where no voltage is applied to the gate electrode 204, the drain electrode 211 is
The p body region 2
07 and p ⁺ body region 209 and n drift region 20
No current flows because the pn junction between 2d and 2d is in the opposite direction. However, when a positive voltage (vs. source electrode 210) is applied to gate electrode 204, n
A channel is formed, and the field effect transistor is turned on. For this reason, electrons flow from the n ⁺ source region 206 to the n drift region 202d via the n channel. Since thereby the carrier (electron) concentration in the n drift region 202d and resistance decreases with rising hole conducting diode composed of the n drift region 202d and the p ⁺ substrate 201. from p ⁺ substrate 201 in the n drift region 202d ( Holes) are injected. Therefore, the bipolar transistor is turned on, and the drain electrode 211 is connected to the source electrode 21.
The current in the thickness direction flows to zero.

Here, when the positive voltage of the gate electrode 204 is cut off, the IGBT returns to the off state. In the on state, the n drift region 202d is filled with both electrons and holes at a high concentration. Even if the injection of electrons from n ⁺ source region 206 is cut off by turning off the voltage, the carrier concentration in n drift region 202d does not immediately decrease. Therefore, the transient characteristics when the IGBT is turned off are shown in FIG.
As shown by the broken line in the graph, the current does not fall immediately after the switch is turned off. Therefore, there is a problem that the turn-off time is long, and techniques for improving this point have been conventionally proposed.

[0007] The proposed turn-off time shortening means basically has a problem in that a region in which recombination centers such as heavy metal atoms and lattice defects are distributed at a high concentration is provided in the IGBT and carriers are annihilated. The purpose is to reduce the carrier concentration at an early stage. For example, JP-A-64-19
No. 771 discloses that by performing proton irradiation from the back side of the IGBT (p ⁺ substrate 201 side in FIG. 15), p ⁺
Lattice defects are distributed in a narrow range near the substrate 201 (see FIG. 16).

[0008]

However, an IGBT in which lattice defects are distributed within a narrow range as disclosed in the above-mentioned publication.
Then, the reduction of the turn-off time is extremely insufficient. This is because the carrier concentration decreases slowly in the region other than the above range. Therefore, as shown by the solid line in the graph of FIG. 17, the convergence of the current is delayed in the final portion of the turn-off. In addition, since the lattice defect distribution area is narrow, there is a problem in that if the formation position is shifted due to a variation in a manufacturing process or the like, the element characteristics are greatly affected. The same applies to the case where the lattice defect distribution region is provided in the p ⁺ substrate 201. When electron beam irradiation is used instead of irradiation with ions such as protons, lattice defects can be widely distributed over the entire semiconductor and the turn-off time can be reduced sufficiently (Japanese Patent Application Laid-Open No. 3-272184). On-resistance increases due to the distribution of lattice defects also in the field effect transistor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of a conventional semiconductor device.
That is, it is a technical object of the present invention to provide a semiconductor device in which the turn-off time is sufficiently reduced without increasing the on-resistance, together with a method of manufacturing the semiconductor device.

[0010]

According to a first aspect of the present invention, a switching element is provided on a front surface side of a semiconductor layer, and the switching element is turned on and off in a thickness direction of the semiconductor layer. A semiconductor device for controlling switching of a current, wherein a part of the semiconductor layer includes:
A defect region having a higher lattice defect concentration than another portion is provided, wherein the defect region includes an entire portion of the semiconductor layer that is not depleted after switching off a current;
It is specified that the switching element is not included.

In this semiconductor device, the portion which is not depleted when the switching element is turned off when the switching element is turned on and the current flows in the thickness direction of the semiconductor layer is turned off at a higher concentration than the other portions. Lattice defects are distributed. Therefore, the life time of the carrier in this part is short. Therefore, the carrier concentration in this portion rapidly decreases after the power is turned off, and the current quickly converges to zero. On the other hand, the lattice defect concentration in the switching element portion is not particularly higher than those in other portions, so that the on-resistance is low and the characteristics during the on-operation are excellent. Here, the concentration distribution of lattice defects in the semiconductor layer is often such that the concentration of a Gaussian distribution, a Lorentz distribution, or the like changes continuously in many cases. What is necessary is just to let it be a defective area.

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, further comprising a bipolar transistor having an emitter, a base, and a collector arranged in a thickness direction of the semiconductor layer, wherein the switching element is provided. Is a field-effect transistor that injects carriers into the base of the bipolar transistor when turned on, wherein the defect region includes an entire portion of the base near the emitter that is not depleted after switching off. I do.

This semiconductor device is a so-called insulated gate bipolar transistor (IGBT). This IG
In the BT, in the on state, carriers are injected from the field-effect transistor into the base of the bipolar transistor, whereby the carrier concentration in the base increases, the bipolar transistor conducts, and current flows. When the field-effect transistor is switched off, the depletion layer expands from the pn junction between the base and the collector of the bipolar transistor. However, a non-depleted region is included in the base near the emitter in the defect region. The carrier in this part disappears quickly. Therefore, the current quickly converges to 0, and the turn-off response is excellent. On the other hand, since the lattice defect concentration in the field effect transistor portion is not particularly higher than in other portions, the on-resistance is low and the characteristics during the on-operation are excellent.

According to a third aspect of the present invention, the semiconductor layer provided with the switching element on the front surface includes a defect region having a higher lattice defect concentration than other portions and an entire portion which is not depleted when switched off. A method of manufacturing a semiconductor device having a structure formed so as not to include the switching element, wherein the defect region is formed by performing ion irradiation on the semiconductor layer through an irradiation mask,
The irradiation mask has an absorption capacity of two or more levels depending on the location, and the half width of the distribution of the irradiated ions in the semiconductor is equal to or greater than the thickness of a portion that is not depleted when the current is turned off. It is specified by the feature that it is.

In this manufacturing method, a defect region is formed by irradiating a semiconductor layer provided with a switching element on the surface side with ions through an irradiation mask. As the irradiation mask at that time, a mask having two or more levels of absorption capacity (for example, due to a difference in thickness) is used depending on the location.
Since the absorption capacity of the irradiation mask varies depending on the location, the half value width of the distribution of the arrival position of the ions in the semiconductor layer is widened, so that a single ion irradiation does not require an extremely high energy and can be switched off. In this case, a defect region that covers the entire portion that is not depleted when formed can be formed. Note that the formation of the defective region may be performed before the formation of the switching element in the semiconductor layer.

If the irradiation energy is adjusted such that the switching element is not included in the defective area, the semiconductor device according to the first aspect is manufactured. If the semiconductor layer has a bipolar transistor in which an emitter, a base, and a collector are arranged in the thickness direction, and the switching element is a field effect transistor,
The semiconductor device according to claim 2 is manufactured. The ion irradiation may be performed from either the front side or the back side of the semiconductor layer.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment shown in the drawings. In the present embodiment, the present invention is embodied in a planar n-channel IGBT.

[Structure] (Semiconductor layer) The IGBT 1 according to the present embodiment has the basic structure shown in FIG. That is, the p ⁺ substrate 101 of high concentration p-type silicon and the n epitaxial layer 102 formed thereon form the semiconductor layer 10. In this semiconductor layer 10, the side of the n epitaxial layer 102 (upper in FIG. 1) is referred to as the front side, and the side of the p ⁺ substrate 101 (lower in FIG. 1) is referred to as the back side. An n ⁺ source region 106, a p body region 107, and a p ⁺ body region 109 are formed on the surface side of the semiconductor layer 10.
These are diffusion layers formed on a part of the n-epitaxial layer 102 by ion implantation or the like. A portion other than these diffusion layers in the n epitaxial layer 102 is called an n drift region 102d.

In the vicinity of the interface between the n drift region 102d and the p ⁺ substrate 101, a defect region 112 in which lattice defects are distributed at a high concentration is formed. Defective area 112
Are mostly the n drift region 102d, but partially extend to the p ⁺ substrate 101. However, it does not extend to the diffusion layers such as the p body region 107. Further, the n drift region 102d is composed of the depletion region 102a and the non-depletion region 1
02b. Although these are not distinguished in terms of manufacturing, there is a difference in operation. That is, although details will be described later, the pn between the n drift region 102d and the p body region 107 and the p ⁺ body region 109 after the IGBT 1 is switched off.
The range in which the depletion layer extends from the junction is the depletion region 102
a and the rest is the non-depleted region 102b. The non-depleted region 102b is included in the defect region 112.

In the semiconductor layer 10 having the above-described structure, X-
FIG. 2 shows the impurity concentration (thin solid line) and the lattice defect concentration (thick solid line) on the X-ray. As shown in FIG. 2, the lattice defect concentration changes continuously and there is no clear step. The range of the defect region 112 shown in FIG. 1 is a range in which the lattice defect concentration has a half width.

(Electrode, Insulating Film) Next, electrodes, insulating films and the like provided on the front surface and the back surface of the semiconductor layer 10 will be described. First, a gate electrode 104 is formed as an electrode on the front side.
And a source electrode 110, and a gate electrode 1
A gate insulating film 103 and insulating films 105 and 108 for insulating the semiconductor device 04 from the semiconductor layer 10 and the like are provided. Gate electrode 104 is formed between n drift region 102 d and p body region 10 d on the surface of n epitaxial layer 102.
7 and an n ⁺ source region 10
6 extends above some of them. This gate electrode 104
Are insulated from the semiconductor layer 10 by the gate insulating film 103. On the other hand, source electrode 110 is provided so as to be in contact with n ⁺ source region 106 and p ⁺ body region 109 and to be electrically connected thereto. Gate electrode 1
04 and the source electrode 110, insulating films 105, 10
8 insulated. The gate electrode 104 has a gate terminal G, and the source electrode 110 has a source terminal S.
C are provided respectively.

On the other hand, a drain electrode 111 which is in contact with the p ⁺ substrate 101 and is electrically connected thereto is provided on the back surface side. The drain electrode 111 is provided with a drain terminal DE.

(Element structure) IGBT having the above structure
1, p ⁺ body region 109 and n drift region 1
02d and the p ⁺ substrate 101 constitute a pnp bipolar transistor. That is, p ⁺ body region 109 is a collector, n drift region 102d is a base, and p ⁺ substrate 101 is an emitter. Further, n ⁺ source region 106, p body region 107, and n drift region 10
2d and the gate electrode 104 constitute an n-channel field effect transistor. That is, p body region 107 is a channel formation region, and n drift region 102d is a drain. Of course, the n ⁺ source region 106 is the source, and the gate electrode 104 is the gate. Therefore, the n drift region 102d also serves as the base of the bipolar transistor and the drain of the field effect transistor.

[Operation] Next, the operation of the IGBT 1 will be described. The basic operation of the IGBT 1 is to control the switching of the current from the drain electrode 111 to the source electrode 110, that is, the current in the thickness direction of the semiconductor layer 10, by the voltage of the gate electrode 104, which is an insulated gate.

(Off State) First, a state in which no voltage is applied to the gate electrode 104 will be considered. In this state, the field-effect transistor is not turned on, and does not affect the flow of current between the drain electrode 111 and the source electrode 110. Therefore, the drain terminal DE
A voltage is applied between the drain terminal 111 and the source terminal SC so that the drain terminal DE has a higher potential.
From the source electrode 110 toward the source electrode 110,
n drift region 102d, p body region 107 and p
^Since the pn junction with ⁺ body region 109 is in the opposite direction, almost no current flows. That is, the bipolar transistor is off.

(ON state) Here, a positive voltage (vs. source electrode 110) is applied to the gate electrode 104 using the gate terminal G.
(Hereinafter referred to as gate voltage), the following occurs. First, an n-channel is generated on the surface of p body region 107 facing gate electrode 104 with gate insulating film 103 interposed therebetween by the electric field effect of the gate voltage. Therefore, electrons, which are carriers of the n ⁺ source region 106, flow through the n channel into the n drift region 102d having a higher potential. That is, the field effect transistor is turned on.

As a result, the electron concentration in n drift region 102d (both depleted region 102a and non-depleted region 102b) increases. Therefore, the resistance of the n drift region 102d decreases and the potential thereof decreases, so that the holes serving as carriers of the p ⁺ substrate 101
02d. That is, the n drift region 102
The diode constituted by d and the p ⁺ substrate 101 conducts. As a result, the n drift region 102d has a state in which not only the electron concentration but also the hole concentration is high. Some of the holes that have entered the n-drift region 102d annihilate with electrons, and flow into the p ⁺ body region 109 having a lower potential. That is, the bipolar transistor is turned on. Therefore, a current flows in the thickness direction from the drain electrode 111 to the source electrode 110.

That is, in the IGBT 1, on / off is controlled by the voltage of the insulated gate electrode 104, based on the function of a bipolar transistor in which both electrons and holes are involved in the on operation. Here, a field-effect transistor that is directly turned on and off by a gate voltage plays a role as a switching element that switches on / off of a bipolar transistor. Further, the defect region 112 in the semiconductor layer 10 where the lattice defects are distributed at a high concentration is formed in the non-depleted region 102.
Since it is limited to the vicinity of b and does not reach the diffusion layer such as the p body region 107, the on-resistance is not high.

(Switch-off) When the application of the positive voltage to the gate electrode 104 is stopped from the above-described ON state, the n-channel on the surface of the p-body region 107 disappears, and electrons are injected into the n-drift region 102d. Is cut off, so IGB
T1 returns to off. The transient operation at that time will be described.

First, n drift region 10 in ON state
2d is a state in which both electrons and holes are filled with a high concentration. When the switch is turned off, the injection of electrons is cut off and the holes flow out to the p ⁺ body region 109, so that the pn junction at the interface between the p ⁺ body region 109 and the p body region 107 causes the carrier concentration to decrease. But the depletion layer is very low. The spread of the depletion layer extends to the depletion region 102a but not to the non-depletion region 102b in the n drift region 102d. However, the non-depleted region 102b is included in the defect region 112 as described above, and has a high lattice defect concentration. Therefore, the lifetime of the carrier is short, and the electrons and holes are quickly annihilated. Since the injection of electrons is cut off and the inflow of holes from the p ⁺ substrate 101 is cut off, the carrier concentration decreases early due to the annihilation.

Therefore, in the entire n-drift region 102d, the carrier concentration is reduced early after the switch-off. Therefore, as shown in FIG. 3, the current from the drain electrode 111 to the source electrode 110 becomes zero immediately after the switch-off.
Converges to That is, the turn-off time is short and the switch-off response is excellent.

[Manufacturing Method] Next, a method of manufacturing the IGBT 1 will be described.

(Epitaxial Growth) In manufacturing the IGBT 1, a high-concentration p-type substrate is used as a silicon substrate. First, a low-concentration n-type silicon layer is formed on a well-cleaned p ⁺ substrate 101 by epitaxial growth. Thus, as shown in FIG. 4, p ⁺ substrate 101 and the n
Semiconductor layer 10 which is a laminate with epitaxial layer 102
Is formed. This p ⁺ substrate 101 serves as an emitter region of a bipolar transistor in the IGBT 1. The n-epitaxial layer 102 is a portion that becomes an n-drift region 102d and a diffusion layer.

(Formation of Gate Electrode) Subsequently, after a thermal oxide film is formed on the surface of
According to the method, a polycrystalline silicon film and a silicon oxide film are sequentially laminated. The polycrystalline silicon film contains an impurity such as phosphorus (P) for imparting conductivity. Then, when the polycrystalline silicon film and the silicon oxide film are etched into a predetermined shape while leaving the thermal oxide film, a gate electrode 104 (polycrystalline silicon film) is formed as shown in FIG. Gate electrode 104 is insulated from n epitaxial layer 102 by gate insulating film 103 (thermal oxide film). Note that the insulating film 105 (silicon oxide film) is
4 and for insulation between a source electrode 110 to be formed later.

(Formation of Diffusion Layer) Next, a diffusion layer is formed on a part of the n epitaxial layer 102. The diffusion layer formed first is the n ⁺ source region 106. For this reason, a donor element such as arsenic (As) is ion-implanted from above into the semiconductor layer 10 on which the gate electrode 104 has been formed (see FIG. 6). Then, the range in which the implanted ions are distributed becomes high-concentration n-type, and the n ⁺ source region 106 is formed. Here, since the insulating film 105 serves as a mask to block ions, no n ⁺ source region 106 is formed below the gate electrode 104 except for the peripheral portion. An n ⁺ source region 106 is formed at the peripheral portion due to ions flowing inside the n epitaxial layer 102. n ⁺
The source region 106 is a portion that becomes a source of the field effect transistor in the IGBT 1.

The diffusion layer to be formed next is the p body region 10
7 For this purpose, an acceptor element such as boron (B) is ion-implanted into the semiconductor layer 10 on which the n ⁺ source region 106 has been formed from obliquely above (see FIG. 7).
At this time, the n-epitaxial layer 10 of the implanted ions is
The range within 2 is larger than that in the case of ion implantation for forming the n ⁺ source region 106, for example, about 3 to 5 times. The greater the range, the better. However, since a larger energy is required to increase the range, in practice, the range is preferably about 3 to 5 times. The implantation dose is such that the conductivity type of the n ⁺ source region 106 is not reversed and the conductivity type of the n epitaxial layer 102 other than the n ⁺ source region 106 is reversed to the p type. Then, the region where the implanted ions are distributed and the region other than n ⁺ source region 106 becomes p-type, and p body region 107 is formed.

In the formed p body region 107, since the ion implantation is performed obliquely and the range of the implanted ions is large, the n ⁺ source region 106 is formed.
It covers the whole circumference. Therefore, n ⁺ source region 1
06 and n drift region 102d (n epitaxial layer 1
02 (the part which is not the diffusion layer in the reference numeral 02). In addition, p body region 107 has n ⁺ source region 10
Except for the lower portion of 6, the semiconductor device faces the surface of the n-type epitaxial layer 102, and the portion faces the gate electrode 104 with the gate insulating film 103 interposed therebetween. This part is IGBT
This is where a channel is formed in one field effect transistor.

Subsequently, formation of p ⁺ body region 109 is performed. Therefore, first, a silicon oxide film is deposited on the semiconductor layer 10 on which the p body region 107 has been formed by the CVD method. Since this deposition is performed isotropically, the silicon oxide also adheres to the side walls (denoted by W in FIG. 7) of the gate electrode 104 and the insulating film 105. Therefore, the deposited silicon oxide film 108 has a shape as shown in FIG. Then, the n-type epitaxial layer 102 (n ⁺ source region 106) at a position away from the gate electrode 104.
When the silicon oxide is etched back from above by anisotropic etching until the silicon oxide is exposed, the shape shown in FIG. 9 is obtained.

Then, an acceptor element such as boron is ion-implanted (see FIG. 10). At this time, the range of the implanted ions in the n-type epitaxial layer 102 is set to be substantially the same as in the case of ion implantation for forming the p-body region 107. The dose of the implantation is such that the conductivity type of the n ⁺ source region 106 is also inverted. Thereby, a part of p body region 107 and a part of n ⁺ source region 106 become p ⁺ body region 109 having a higher impurity concentration. Formed p ⁺ body region 10
9 faces the surface of the n epitaxial layer 102.
In addition, the lower portion is in direct contact with n drift region 102d without interposing p body region 107. This part is I
This is a portion to be a collector region in the bipolar transistor of the GBT1.

(Formation of Source Electrode) Next, the insulating film 10
5,108 is partially etched. The purpose of this etching, as shown in FIG. 11, n ⁺ source region 106
Is to expose a part of it. At the same time, the insulating film 1
The film thickness of 05 is also adjusted. Therefore, this etching is performed using an isotropic etching method such as wet etching. Then, when a metal such as aluminum (Al) is deposited by a sputtering method, a source electrode 110 that contacts both the p ⁺ body region 109 and the n ⁺ source region 106 is formed as shown in FIG. In addition,
The gate electrode 104 in the state of FIG.
Insulated from other parts by 3, 105, 108.

(Formation of Defect Region) Next, a defect region 112 is formed by ion irradiation. This ion irradiation is shown in Fig. 1.
As shown in FIG. 3, the process is performed from the back side of the semiconductor layer 10 (p ⁺ substrate 101 side) with an absorber 40 prepared in advance interposed. Note that the semiconductor layer 10 in FIG. 13 is upside down from FIG. Helium ions (H
e ²⁺ ) and hydrogen ions (H ⁺ ). Absorber 40
Is a foil made of a material such as aluminum, and has a groove portion 41 and a convex portion 42 formed alternately. The width of each of the groove 41 and the protrusion 42 is substantially equal to the half-value width of a lattice defect distributed in the semiconductor layer 10 due to the irradiation of ions. Further, the difference between the thickness of the groove 41 and the thickness of the protrusion 42 is set to the same value.

When the ion irradiation is performed through the absorber 40, the lattice defects formed in the semiconductor layer 10 surround the line segment S, the line segment T, and each of these line segments in FIG. A distribution as shown by a quadrilateral U is taken. That is, the line segment group S indicates a distribution peak position corresponding to the convex portion 42 of the absorber 40, and the line segment T group indicates a distribution peak position corresponding to the groove portion 41. Both are the groove 41 and the protrusion 4
The position in the depth direction is different by the difference in thickness from 2. A quadrilateral U surrounding each line segment is an area where the distribution density of lattice defects is equal to or greater than half the peak value. The actual distribution in the semiconductor layer 10 is a superposition of each of these distributions, and as shown in the graph of FIG. 13, the half width of a single distribution (He ²⁺ is 24 MeV
(In the case of irradiating with the energy of about 10 μm), the distribution in the depth direction has a half width V which is about twice as large as about 10 μm. The defect distribution in the lateral direction is almost uniform.

Thereafter, annealing is performed at a temperature of about 200 to 470 ° C. to stabilize the defect. Thus, the defect region 112 including the non-depleted region 102b in the n drift region 102d is obtained by one ion irradiation. The absorber 40 in this ion irradiation is shown in FIG.
As shown in FIG. 14, a split type in which the absorber 43 for adjusting the peak depth and the absorber 44 for adjusting the half-value width may be used separately. With the split type, it is possible to cope with various combinations of the peak depth and the half width with a smaller number of types of absorbers.

(Formation of Drain Electrode) Finally, a metal such as aluminum is deposited on the back surface (p ⁺ substrate 101) of the semiconductor layer 10 by sputtering or vapor deposition to form a drain electrode 111. When the necessary terminals (SC, G, DE) are attached to (104, 111), the IGBT 1 shown in FIG. 1 is completed.

[Summary] As described above in detail, in the IGBT 1 according to the present embodiment, the n drift region 10
In the vicinity of the interface between 2d (n epitaxial layer 102) and p ⁺ substrate 101, lattice defects are distributed at a high concentration and the half width of the distribution is increased so that n drift region 102
Non-depleted region 1 of d not depleted after switch off
02b is included in the defect region 112, so that when the gate voltage is switched off, the n drift region 1
Carriers decrease rapidly in the entire area of 02d. Therefore, the current from the drain electrode 111 to the source electrode 110 converges to 0 in a short time after the switch is turned off. That is, the turn-off time is short and the off-response is excellent.

Although the half width of the lattice defect distribution is large and the defect region 112 includes the non-depleted region 102b,
Since the defect region 112 does not reach the diffusion layer such as the p body region 107, the on-resistance is not particularly high. That is, the position and width of the defect region 112 are changed to the non-depleted region 1
By including O.sub.2b but not reaching the diffusion layer, both the reduction of the turn-off time and the prevention of the increase of the on-resistance are achieved at a high level.

Further, since the half width of the lattice defect distribution is sufficiently large, the defect region
Even if there is some variation in the formation depth position, the non-depleted region 102b hardly protrudes outside the defect region 112. Therefore, there is an advantage that the effect of reducing the turn-off time can be stably obtained.

Then, in the manufacture of this IGBT1,
Since the defect region 112 is formed by performing ion irradiation through the absorber 40 having the groove 41 and the protrusion 42 and having a difference in thickness depending on the location, a desired peak depth can be obtained by one ion irradiation. Defect region 11 having width and width
2 can be formed. Therefore, there is no need to repeatedly perform ion irradiation while changing the ion energy, the type of absorber, and the like, so that the process is simple and the production cost is low. Further, since the half width of the defect distribution is widened by the difference in thickness between the groove 41 and the projection 42, the required width of the defect region 112 can be obtained without applying excessively high acceleration energy.

It should be noted that the present invention is not limited to the above-described embodiment at all, and it is needless to say that various improvements and modifications can be made without departing from the scope of the present invention.

For example, the IGBT 1 shown in the above embodiment
In the embodiment, no particular difference in impurity concentration is provided in the n drift region 102d, but some concentration distribution may be provided. A typical example is n drift region 1
A high-concentration buffer layer may be provided especially in the non-depleted region 102b in the region 02d. In some cases, the entire non-depleted region 102b may be a buffer layer. The IGBT 1 is of a so-called planar type, but may be applied to a device having a special gate structure such as a trench gate type. Further, it is not essential to have an insulated gate, and the present invention can be applied to a conductivity modulation type semiconductor device without an insulated gate. And these p
The n-polarity may be reversed.

Also, the manufacturing method may be modified. For example, in the above-described embodiment, the formation of the defect region 112 is performed after the formation of the diffusion layer such as the p body region 107, but may be performed before the formation of the diffusion layer. In addition, defect area 1
The ion irradiation for forming 12 may be performed from the front side instead of from the back side of the semiconductor layer 10. In the case of performing from the surface side, there is a concern that the irradiation ions may pass through the part that becomes the diffusion layer, etc., but usually annealing for stabilization is performed after irradiation. Removed. Therefore, there is no problem if the irradiation is performed under the condition that the irradiation ions do not stop on the portion serving as the diffusion layer or the like. Furthermore, as long as it is a switch element, a device having a new structure other than the above can be applied.

Further, at the time of ion irradiation, instead of the absorber 40 prepared in advance, a thin film made of the same material as that of the absorber may be formed and an uneven shape may be formed by etching. In that case, it is conceivable that the film is subsequently used as an electrode.

[0053]

As apparent from the above description, according to the present invention, an appropriate peak depth and width of the lattice defect distribution in the semiconductor layer can be realized, and the turn-off time can be sufficiently increased without increasing the on-resistance. The semiconductor device which has been shortened is provided together with the manufacturing method.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor device according to an embodiment.

FIG. 2 is a diagram illustrating a concentration distribution of lattice defects and impurities in the semiconductor device of FIG. 1;

FIG. 3 is a graph showing transient characteristics after switching off of the semiconductor device of FIG. 1;

FIG. 4 is a diagram showing a semiconductor layer on which epitaxial growth has been performed.

FIG. 5 is a diagram showing a state in which formation and processing of a gate electrode have been performed.

FIG. 6 is a diagram showing formation of a source region.

FIG. 7 is a diagram showing formation of a body region (a channel formation region of a field effect transistor).

FIG. 8 is a diagram showing a state where an insulating film is formed.

FIG. 9 is a view showing a state where a part of the insulating film formed in FIG. 8 is etched;

FIG. 10 is a diagram showing formation of a high-concentration body region (collector region of a bipolar transistor).

FIG. 11 is a diagram showing a state where a part of an insulating film is etched.

FIG. 12 is a diagram showing a state where a source electrode is formed.

FIG. 13 is a diagram illustrating ion irradiation for forming a defect region.

FIG. 14 is a diagram showing another example of the shape of the absorber.

FIG. 15 is a diagram illustrating the basics of an IGBT.

FIG. 16 is a diagram illustrating a concentration distribution of lattice defects and impurities in a conventional semiconductor device.

FIG. 17 is a graph showing transient characteristics after switching off of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor layer 101 Substrate (emitter) 102b Non-depleted region 102d Drift (drain, base) region 104 Gate electrode 106 Source region 107 Body (channel) region 109 Body (collector) region 112 Defect region 40 Absorber

Claims (3)

[Claims] 1. A semiconductor device in which a switching element is provided on a front surface side of a semiconductor layer and a switching control of a current in a thickness direction of the semiconductor layer is performed by turning on and off the switching element. A defect region having a higher lattice defect concentration than that of the semiconductor layer, wherein the defect region includes an entire portion of the semiconductor layer that is not depleted after switch-off, and does not include the switching element. apparatus. 2. The semiconductor device according to claim 1, further comprising a bipolar transistor having an emitter, a base, and a collector arranged in a thickness direction of the semiconductor layer, wherein the switching element is turned on to turn on the bipolar transistor. A field effect transistor for injecting carriers into a base of the semiconductor device, wherein the defect region includes an entire portion of the base near the emitter which is not depleted after switch-off. 3. A semiconductor layer provided with a switching element on a front surface side includes a defect region having a higher lattice defect concentration than other portions and an entire portion that is not depleted when switched off, and the switching element In a method of manufacturing a semiconductor device having a structure formed so as not to include a defect, the defect region is formed by irradiating the semiconductor layer with an ion through an irradiation mask, and the irradiation mask has two or more levels depending on a place. Wherein the half width of the distribution of irradiated ions in the semiconductor is greater than the thickness of a portion that is not depleted when the current is turned off. Manufacturing method.