TW201834029A - Semiconductor device and manufacturing method of semiconductor device which can form a high-resistance region capable of withstanding heat treatment above 200 degree Celsius - Google Patents

Semiconductor device and manufacturing method of semiconductor device which can form a high-resistance region capable of withstanding heat treatment above 200 degree Celsius Download PDF

Info

Publication number
TW201834029A
TW201834029A TW106141097A TW106141097A TW201834029A TW 201834029 A TW201834029 A TW 201834029A TW 106141097 A TW106141097 A TW 106141097A TW 106141097 A TW106141097 A TW 106141097A TW 201834029 A TW201834029 A TW 201834029A
Authority
TW
Taiwan
Prior art keywords
range
heat treatment
impedance
semiconductor device
semiconductor substrate
Prior art date
Application number
TW106141097A
Other languages
Chinese (zh)
Other versions
TWI662598B (en
Inventor
井上剛
八木宏親
Original Assignee
日商住重愛特科思股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商住重愛特科思股份有限公司 filed Critical 日商住重愛特科思股份有限公司
Publication of TW201834029A publication Critical patent/TW201834029A/en
Application granted granted Critical
Publication of TWI662598B publication Critical patent/TWI662598B/en

Links

Abstract

The invention relates to a semiconductor device and manufacturing method of semiconductor device. It can form a high-resistance region capable of withstanding heat treatment above 200 degree Celsius. The manufacturing method of semiconductor device 10 comprises steps of irradiating a p-type semiconductor substrate 12 formed with the semiconductor element by hydrogen (H) ions, where the hydrogen density is in a range of above 2x10.supra.15cm.supra.-3 and below 2x10.supra.17cm.supra.-3 to form a high-resistance region 30 having the resistivity higher than that of the p-type semiconductor substrate 12 before ion irradiation, and heating at temperature of above 200 degree Celsius and below 400 degree Celsius to form the p-type semiconductor substrate 12 having the high-resistance region 30.

Description

半導體裝置及半導體裝置之製造方法Semiconductor device and method of manufacturing the same

[0001] 本發明係有關半導體裝置及半導體裝置之製造方法。[0001] The present invention relates to a semiconductor device and a method of manufacturing the same.

[0002] 近年,CMOS技術提升,而使類比電路與數位電路混載之SoC (System on a Chip)則加以使用於種種用途。在如此混載在晶片中,為了類比電路之特性提升而於半導體基板內,加以形成有高阻抗範圍。例如,經由自元件範圍的背面加速改變能量同時,複數次進行離子照射之時,加以形成為了干擾減低之高阻抗範圍(例如,參照專利文獻1)。 [先前技術文獻] [專利文獻]   [0003] [專利文獻1] 日本特開2015-119039號公報[0002] In recent years, CMOS technology has been upgraded, and SoC (System on a Chip), which mixes analog circuits and digital circuits, has been used for various purposes. In such a manner that it is mixed in the wafer, a high impedance range is formed in the semiconductor substrate for the purpose of improving the characteristics of the analog circuit. For example, when the energy is changed from the back surface of the element range, and the ion irradiation is performed plural times, a high impedance range for the disturbance reduction is formed (for example, refer to Patent Document 1). [Prior Art Document] [Patent Document] [0003] [Patent Document 1] Japanese Patent Laid-Open Publication No. 2015-119039

[發明欲解決之課題]   [0004] 在上述的文獻中,加以報告有:當於經由離子照射而形成之高阻抗範圍,加上200℃以上的熱處理時,產生有阻抗率之顯著下降者,而加以記載有:將阻抗率的安定化作為目的而加上200℃以下的熱處理者為佳之內容。但在半導體裝置之製造工程中,有加以執行伴隨200℃以上的熱處理之後工程,而此情況,成為無法維持經由離子照射而得到之高阻抗率。   [0005] 本發明之某形態的例示目的之一係提供:形成可耐200℃以上之熱處理之高阻抗範圍的技術者。 [為了解決課題之手段]   [0006] 本發明之某形態的半導體裝置之製造方法係具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為2×1015 cm-3 以上2×1017 cm-3 以下之範圍,形成阻抗率則較離子照射前之p型半導體基板為高之高阻抗範圍者,和以200℃以上400℃以下之溫度而加熱形成有高阻抗範圍之p型半導體基板者。   [0007] 本發明之另外的形態係半導體裝置。此裝置係具備:p型半導體基板,和加以設置於p型半導體基板上之半導體元件,和加以設置於p型半導體基板內之高阻抗範圍。高阻抗範圍係氫密度則成為2×1015 cm-3 以上2×1017 cm-3 以下之範圍,阻抗率則較p型半導體基板為高之範圍。   [0008] 然而,將以上之構成要素的任意組合或本發明之構成要素或表現,在方法,裝置,系統等之間相互進行置換之構成亦另外,作為本發明之形態而為有效。 [發明效果]   [0009] 如根據本發明,可形成可耐200℃以上之熱處理的高阻抗範圍。[Problem to be Solved by the Invention] [0004] In the above-mentioned literature, it is reported that when a high-impedance range formed by ion irradiation is applied and a heat treatment of 200 ° C or more is added, a significant drop in the impedance ratio occurs. It is described that it is preferable to add a heat treatment of 200 ° C or less for the purpose of setting the stability of the resistivity. However, in the manufacturing process of a semiconductor device, it is performed after heat treatment with a temperature of 200 ° C or higher, and in this case, the high impedance ratio obtained by ion irradiation cannot be maintained. [0005] One of the exemplary objects of a certain aspect of the present invention provides a technique for forming a high impedance range capable of withstanding heat treatment of 200 ° C or higher. [Means for Solving the Problem] [0006] A method of manufacturing a semiconductor device according to another aspect of the present invention includes: irradiating hydrogen (H) ions to a p-type semiconductor substrate on which a semiconductor element is formed, and having a hydrogen density of 2 × 10 15 In the range of cm -3 or more and 2 × 10 17 cm -3 or less, the impedance ratio is higher than the high-impedance range of the p-type semiconductor substrate before ion irradiation, and is formed by heating at a temperature of 200 ° C or more and 400 ° C or less. A p-type semiconductor substrate with a high impedance range. Another aspect of the present invention is a semiconductor device. This device includes a p-type semiconductor substrate, a semiconductor element provided on the p-type semiconductor substrate, and a high-impedance range provided in the p-type semiconductor substrate. In the high-impedance range, the hydrogen density is in the range of 2 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less, and the impedance ratio is higher than that of the p-type semiconductor substrate. However, any combination of the above-described constituent elements or the constituent elements or expressions of the present invention may be replaced by a method, an apparatus, a system, etc., and is also effective as an aspect of the present invention. [Effect of the Invention] According to the present invention, a high-impedance range capable of withstanding heat treatment of 200 ° C or more can be formed.

[0011] 以下,對於為了實施本發明之形態,詳細地加以說明。然而,以下所敘述之構成係為例示,而非限定任何本發明之範圍者。另外,在圖面的說明中對於同一要素,係附上同一符號而適宜省略重複之說明。另外,在以下的說明中,在參照之各剖面圖,半導體基板或其他的層之厚度或尺寸係為說明方便之構成,而未必為顯示實際尺寸或比率者。   [0012] 圖1係模式性地顯示有關實施形態的半導體裝置10之構造的剖面圖。半導體裝置10係系統LSI或單晶片系統之積體電路(IC)。半導體裝置10係具備:半導體基板12與配線層18。   [0013] 半導體基板12係阻抗率為100Ω・cm以下之低阻抗的半導體基板,而阻抗率為1~100Ω・cm程度之半導體基板。半導體基板12係例如,經由柴可拉斯基(CZ)法而加以製作之p型的矽(Si)晶圓。經由CZ法而加以製作的晶圓係與經由懸浮區熔(FZ)法等而加以製作之高阻抗晶圓作比較,阻抗率為低,且廉價。在某個實施例中,半導體基板12之阻抗率係4Ω・cm,而p型載體濃度為3.4×1015 cm-3 。   [0014] 對於半導體基板12之主面14係加以設置第1元件範圍22與第2元件範圍24。例如,對於第1元件範圍22係加以設置數位電路用之第1半導體元件26,而對於第2元件範圍24係加以設置類比電路用之第2半導體元件28。第1半導體元件26及第2半導體元件28係例如,電晶體或二極體等。對於各第1元件範圍22及第2元件範圍24係加以設置有為了形成半導體元件之阱型範圍,源極/汲極範圍,接點範圍等之不純物擴散層。   [0015] 在本說明書中,有著將正交於半導體基板12之主面14的方向,稱為上下方向或深度方向者。另外,在半導體基板12之內部中,有著將朝向主面14之方向,稱為上方向或上側,而將朝向於與主面14相反的背面16之方向,稱為下方向或下側者。另外,有著將平行於主面14之方向,稱為橫方向或水平方向者。   [0016] 對於半導體基板12之內部係加以設置有高阻抗範圍30。高阻抗範圍30係阻抗率則較半導體基板12之主體部分為高之範圍。高阻抗範圍30係具有100Ω・cm以上之阻抗率,例如具有500Ω・cm以上之阻抗率,而理想為1kΩ・cm以上。高阻抗範圍30係包含:凹槽型高阻抗範圍32與平面型高阻抗範圍34。   [0017] 凹槽型高阻抗範圍32係加以設置於第1元件範圍22與第2元件範圍24之間的分離範圍20,呈具有自半導體基板12之主面14朝向於背面16程度之深度地加以形成。凹槽型高阻抗範圍32之深度係20μm以上,而理想為50μm~200μm程度。凹槽型高阻抗範圍32係呈到達至較形成於第1元件範圍22或第2元件範圍24之不純物擴散層為深的位置地加以形成。凹槽型高阻抗範圍32係例如,具有遮斷自數位電路朝向於類比電路之干擾而使類比電路之特性提升之機能。   [0018] 平面型高阻抗範圍34係在第2元件範圍24中,延伸存在於水平方向。平面型高阻抗範圍34係自分離範圍20,遍布於第2元件範圍24而延伸存在於水平方向,呈形成與凹槽型高阻抗範圍32連續之高阻抗範圍地加以設置亦可。平面型高阻抗範圍34係由形成於類比電路之正下方者,而貢獻於類比電路之特性提升。   [0019] 在圖示的例中,於半導體基板12之內部,加以形成有凹槽型高阻抗範圍32與平面型高阻抗範圍34之雙方,但在變形例中,僅設置凹槽型高阻抗範圍32及平面型高阻抗範圍34之任一方亦可。   [0020] 高阻抗範圍30係經由照射氫(H)離子於低阻抗基板之半導體基板12的主體部分之時而加以形成。當對於晶圓進行離子照射時,離子則到達至因應離子之加速能量之深度為止。此時,在包含到達之範圍的附近中,形成有晶格缺陷,而結晶的規則性(週期性)成為混亂之狀態。在如此之晶格缺陷為多之範圍中,載體(電子或電洞)則成為被容易散亂,而阻礙載體的移動。其結果,在經由離子照射而局部性之晶格缺陷產生之範圍中,比較於照射前,阻抗率則上升。   [0021] 經由離子照射而阻抗率上升之深度方向的位置或範圍,係可由適宜選擇離子照射之加速能量或照射量而作調整。例如,由調整離子照射時之離子的加速能量者,可調整形成有高阻抗範圍之深度位置。另外,由選擇離子照射的加速能量者,可調整形成高阻抗範圍之深度位置,深度方向之範圍(半寬度)或橫方向之擴散寬度。更且,由使加速能量變化之同時,進行複數次之離子照射者,可遍布於深度方向而形成更厚之高阻抗範圍。   [0022] 在本實施形態中,以1MeV以上、100MeV以下之加速能量而照射氫(H)離子。例如,以4MeV、8MeV、17MeV之加速能量而照射1價的氫離子(1 H+ )。作為照射如此之加速能量的離子束之裝置,加以使用迴旋加速方式或凡德格拉夫方式之裝置。經由使用如此之照射條件之時,在矽晶圓中,可使離子自半導體基板12之主面14的附近到達至深度100μm以上之位置者。   [0023] 經由離子照射而加以形成之高阻抗範圍的阻抗率係依存於所生成之晶格缺陷的密度(缺陷密度)。如根據本發明者們之見解,了解到缺陷密度如為1×1017 cm-3 以上,可最佳地得到1kΩ・cm以上之阻抗率者。如此之缺陷密度係照射離子的加速能量如為4MeV~17MeV時,可由將氫離子的照射量(量數量)作為1×1013 cm-2 以上者而實現。   [0024] 由如此作為而加以形成高阻抗範圍係了解到經由加上熱處理之時,阻抗率則下降者。如根據發明者們之見解,由將離子照射後之半導體基板12加熱至200℃以上者,看到阻抗率之下降,而當將半導體基板12加熱至300℃以上或400℃以上時,阻抗率則顯著地下降。此係認為原因為經由熱處理,晶格缺陷則恢復而缺陷密度則下降者。隨之,經由離子照射而形成高阻抗範圍之情況,在之後的工程中,或許為加上200℃以上的熱處理者為佳。   [0025] 另一方面,對於為了將高阻抗範圍30位置於如同目標之分離範圍20或第2元件範圍24之位置,係在切割晶圓之前,也就是在較半導體處理之後工程為前的階段,必須執行離子照射。在後工程中,進行晶片接合或導線接合,稱為樹脂封閉之熱處理,而在此等工程中,可將半導體基板12加熱為200℃~300℃程度之溫度。為此,經由在後工程之熱處理而高阻抗範圍的阻抗率則下降,而有無法維持所期望之阻抗率(例如,500Ω・cm以上)之虞。   [0026] 因此,在本實施形態中,由經由熱處理而使經由離子照射而打入至半導體基板12的氫活性化者,即使在熱處理後,亦可作為呈維持高阻抗範圍的阻抗率。當經由熱處理而使氫活性化時,經由施體化而n型載體濃度則增加之故,而將p型之半導體基板12之多數載體(p型載體)加以中性化,導電率則下降。例如,由經由氫的活性化,而作為呈可得到與半導體基板12之p型載體濃度同程度之n型載體濃度者,可將半導體基板12作為中性化而提升阻抗率。   [0027] 圖2係顯示經由有關比較例之氦(He)離子照射及熱處理之阻抗率變化之一例的圖表。在比較例中,並非氫離子(1 H+ ),而使用氦離子(3 He2+ )。加速能量係23MeV,而量數量係1.0×1013 cm-2 ,而照射對象係約4Ω・cm之p型矽基板。圖2係顯示離子照射前,離子照射後(熱處理前)及熱處理後(200℃,250℃,300℃)之基板的深度方向之阻抗率分布。如圖示,在熱處理前中,可至60μm程度之深度為止形成1~2kΩ・cm程度之高阻抗範圍,而在200℃之熱處理後,亦可維持略同樣之阻抗率分布的高阻抗範圍。但在250℃之熱處理後中,高阻抗範圍之阻抗率為不足1kΩ・cm,而部分性來說係成為不足500Ω・cm,而在300℃之熱處理後中,高阻抗範圍之阻抗率成為不足100Ω・cm。對於如此使用氦而進行離子照射之情況,係了解到經由超過200℃之熱處理而高阻抗範圍的阻抗率則下降,而經由300℃以上之熱處理,阻抗率則明顯地下降者。   [0028] 圖3係顯示經由有關實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。本實施例係照射氫離子(1 H+ ),加速能量係8MeV,而量數量係1.0×1014 cm-2 ,而照射對象係約4Ω・cm之p型矽基板。圖3係顯示離子照射前,離子照射後(熱處理前)及熱處理後(250℃,400℃)之基板的深度方向之阻抗率分布。如圖示,在熱處理前中,可至110μm程度之深度為止形成1kΩ・cm以上之高阻抗範圍,而在250℃之熱處理後,亦可維持略同樣之阻抗率分布的高阻抗範圍。另外,在400℃之熱處理後,亦可在10μm~80μm之深度中,維持1kΩ・cm以上之高阻抗範圍者。如此,由使用氫離子者,即使在加上超過200℃之熱處理或300℃以上之熱處理的情況,亦可維持500Ω・cm以上、理想為1kΩ・cm以上之高阻抗範圍。   [0029] 圖4係顯示經由有關另外實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。本實施例中,與圖3同樣地照射氫離子(1 H+ ),加速能量係8MeV,而照射對象係約4Ω・cm之p型矽基板。本實施例係使用與圖3不同之量數量,而作為較上述之實施例為高量數量之2.6×10-14 cm-2 。圖4係顯示離子照射前,離子照射後(熱處理前)及熱處理後(200℃,300℃,400℃)之基板的深度方向之阻抗率分布。如圖示,在熱處理前中,可至45μm程度之深度為止形成1kΩ・cm以上之高阻抗範圍,而在200℃之熱處理後,亦可維持略同樣之阻抗率分布的高阻抗範圍。但在300℃之熱處理後中,深度10~30μm程度之阻抗率則成為不足1kΩ・cm,而在400℃之熱處理後中係成為不足100Ω・cm。此係認為原因為經由增加氫離子之量數量之時,氫則過剩地被施體化,導電型則自p型反轉為n型,經由成為多數載體之n型載體濃度的增大而阻抗率則下降者。   [0030] 從以上的比較例及實施例,對於在超過200℃之熱處理後中,亦為了維持高阻抗率(500Ω・cm以上),係可說必須適當地控制氫離子之量數量及熱處理之溫度者。   [0031] 圖5係顯示經由熱處理之氫的活性化率之圖表,而顯示溫度與活性化率之關係。如圖示,200℃~400℃之範圍係氫的活性化率為低,經由溫度上升之活性化率的增加亦為徐緩。另一方面,當超過400℃時,經由溫度上升之活性化率的增加率則變大,而活性化率的值亦超過10%。隨之,由使用經由溫度上升之活性化率的增加為徐緩之200℃~400℃的範圍之熱處理者,即使在對於在後工程之熱處理的溫度產生有個體差之情況,亦可抑制經由處理溫度的不同之阻抗率的顯著變化者。   [0032] 圖6係模式性地顯示經由熱處理之載體濃度變化的圖表,而對於不同之三個氫密度,模式性地顯示經由熱處理而加以施體化之n型載體濃度的值。A係氫密度為5×1016 cm-3 ,而對應於圖3之實施例(能量:8MeV,量數量:1.0×1014 cm-2 )。B係氫密度為1.3×1017 cm-3 ,而對應於圖4之實施例(能量:8MeV,量數量:2.6×1014 cm-2 )。C係氫密度為5×1015 cm-3 ,而D係氫密度為2.5×1016 cm-3 。然而,圖表中的虛線係顯示半導體基板中之p型載體濃度,而為3.4×1015 cm-3 。   [0033] A的情況,在200℃中,n型載體濃度成為1.0×1015 cm-3 程度,而在330℃程度中,成為與基板之p型載體濃度相同之3.4×1015 cm-3 程度,在400℃中,成為6.0×1015 cm-3 程度。其結果,在經由晶格缺陷之恢復的阻抗率下降成為明顯之250℃~400℃的範圍,p型載體濃度與n型載體濃度則成為相同程度,而可實現基板之中性化的高阻抗率化。其結果,如圖3所示,即使作為加上200℃~400℃之熱處理,亦可維持1kΩ・cm以上之高阻抗。   [0034] B的情況,在200℃中,n型載體濃度成為2.6×1015 cm-3 程度,而在230℃程度中,成為與基板之p型載體濃度相同之3.4×1015 cm-3 程度,在300℃程度中,成為基板之p型載體濃度的2倍之6.8×1015 cm-3 程度,在350℃以上中,成為1.0×1016 cm-3 以上。其結果,如圖4所示,當進行300℃以上之熱處理時,經由基板之n型反轉而阻抗率則下降,而進行400℃之熱處理時,基板之阻抗率則更下降。   [0035] C的情況,氫密度則為A的0.1倍之故,因氫的施體化引起之載體濃度則變少,而即使加上400℃以上之熱處理,亦未達到基板之p型載體濃度(3.4×1015 cm-3 )。其結果,認為即使作為加上200℃~400℃之熱處理,基板的中性化係亦未產生,而僅產生有經由缺陷密度減少之阻抗率的下降。D的情況亦同樣,氫密度則為A的0.5倍,而即使加上200℃~400℃之熱處理,亦未達到基板之p型載體濃度(3.4×1015 cm-3 )之故,認為未產生有基板之中性化,而僅產生有經由缺陷密度減少之阻抗率的下降。   [0036] 圖7係顯示氫密度與經由熱處理之阻抗率變化的關係之一例的圖表,而顯示對定於圖6之條件A,B,C,D之阻抗率變化。如圖示,A(氫密度:5×1016 cm-3 )之情況,在200℃~400℃之範圍中,可維持1kΩ・cm以上之高阻抗者。B(氫密度:1.3×1017 cm-3 )之情況,在200℃~300℃之範圍中,可維持500Ω・cm以上之高阻抗,但在350℃以上中,阻抗率則成為200Ω・cm以下。C(氫密度:5×1015 cm-3 )之情況,在200℃之熱處理中,可維持1kΩ・cm以上之高阻抗,但熱處理當超過200℃時,阻抗率則顯著下降,而在250℃以上之熱處理後中,成為10Ω・cm以下。此係認為原因為氫密度為少之故而為了中性化之n型載體濃度產生不足者。另外,D(氫密度:2.5×1016 cm-3 )之情況,在200℃~230℃之範圍,可維持500Ω・cm以上之高阻抗,但在250℃以上中,阻抗率則成為200Ω・cm以下。   [0037] 從以上的研究,對於即使在熱處理後亦為了維持高阻抗率,係必須在200℃~400℃之溫度範圍,實現與半導體基板12之p型載體濃度相同程度之n型載體濃度。經由200℃~400℃之熱處理的氫之活性化率係2%~10%程度之故,而如實現半導體基板12之p型載體濃度之10倍~50倍程度的氫密度即可。一般而言,低阻抗(1~100Ω・cm)之p型矽基板的p型載體濃度係從為1014 ~1016 cm-3 之情況,如可實現5×1015 cm-3 以上2×10-17 cm-3 以下之氫密度即可。例如,p型載體濃度則如為3.4×1015 cm-3 時,3.4×1016 cm-3 以上1.7×10-17 cm-3 以下之氫密度為佳。   [0038] 然而,高阻抗範圍30之至少一部分的導電型則反轉為n型時,在高阻抗範圍中,加以形成pn接合,有對於形成於半導體基板12之電路元件的動作帶來影響之虞。為了抑制如此之影響,而經由氫的活性化之n型載體濃度則呈不超過半導體基板12之p型載體濃度地,控制氫密度的值亦可。也就是,高阻抗範圍30之導電型則呈成為保持p型地,控制氫密度與熱處理溫度亦可。   [0039] 圖8係顯示氫離子照射之量數量與氫密度之關係的一例之圖表,而對於將氫離子之加速能量作為4MeV,8MeV,17MeV之情況而顯示。如圖示,氫離子之量數量與照射後之氫密度係有比例關係。另外,照射能量越低,所得到之氫密度係越高。此係當加速能量為低時,加以限定注入氫離子之深度方向的範圍,而每單位面積之氫注入量則增加之故。從圖表,對於為了實現5×1015 cm-3 以上2×10-17 cm-3 以下之氫密度,係對於4MeV之場合,如作為1×10-13 cm-2 以上2×10-14 cm-2 以下、而8MeV之情況,如作為1×10-13 cm-2 以上4×10-14 cm-2 以下、17MeV之情況,如作為3.6×10-13 cm-2 以上1×10-15 cm-2 以下即可。然而,如以此等之量數量而進行離子照射時,可得到1×1017 cm-3 以上之缺陷密度之故,而在熱處理前的狀態中,亦可實現500Ω・cm以上之高阻抗率。   [0040] 接著,對於有關本實施形態之半導體裝置10的製造方法加以敘述。圖9係模式性顯示半導體裝置10之製造方法的流程圖。首先,經由種種工程而形成元件於p型之半導體基板12(S10),在於半導體基板12上形成配線層,再形成為了保護所形成之元件或配線之保護膜(S14)。S10~S14之工程係在半導體處理中為稱為「前工程」之工程,而可進行熱氧化,熱擴散,CVD,退火等之400℃以上的高溫處理。接著,照射氫離子於半導體基板12而形成高阻抗範圍30(S16),再進行半導體基板12之背面研磨(S18)。S16及S18之工程係所謂「中間工程」或稱作「後保護處理(PPP; Post Passivation Process)」之工程。   [0041] 接著,進行含有熱處理之後工程(S20),作為半導體積體電路而完成。在S20之後工程中,係例如包含:切割晶圓而進行個片化之工程,將個片化之晶片接著於安裝基板上之接合工程,以導線接合而將安裝基板與晶片結線之工程,以樹脂而封閉晶片之工程等。例如,在晶片黏合工程,導線接合工程及樹脂封閉工程中,進行200℃~300℃程度之熱處理,在某實施例中,熱處理的最高溫度係為260℃程度。然而,進行與接合或封閉工程另外加熱半導體裝置10之退火處理亦可。此退火處理係經由以200℃以上400℃以下之特定溫度而加熱高阻抗範圍30之時,而使高阻抗範圍30之阻抗率安定化亦可。此退火處理係如進行10分鐘以下之比較短時間執行即為充分,而亦可為5分鐘以下,1分鐘以下,或30秒以下的時間。   [0042] 以上,依據實施形態而說明過本發明。本發明係不限定於上述實施形態,而可作種種的設計變更,而由該業者理解可進行種種之變形例之情況,或如此作為之變形例亦包含於本發明之範圍情況。   [0043] 在上述之實施形態中,作成僅照射氫離子而形成高阻抗範圍30者。在變形例中,經由組合氫以外之離子照射之時而形成高阻抗範圍亦可。例如,經由氫離子照射而實現上述之數值範圍的氫密度同時,經由照射氫以外的離子種之時而實現上述之數值的缺陷密度亦可。在某變形例中,經由組合氫離子與氦離子之照射之時,即使加以實施200℃以上之熱處理,亦可形成可維持高阻抗(500Ω・cm以上)之高阻抗範圍。[0011] Hereinafter, the mode for carrying out the invention will be described in detail. However, the configurations described below are illustrative and are not intended to limit the scope of the invention. In the description of the drawings, the same components are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In the following description, the thickness or size of the semiconductor substrate or other layers is a convenient description for the respective cross-sectional views, and is not necessarily the actual size or ratio. 1 is a cross-sectional view schematically showing a structure of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is an integrated circuit (IC) of a system LSI or a single wafer system. The semiconductor device 10 includes a semiconductor substrate 12 and a wiring layer 18. [0013] The semiconductor substrate 12 is a semiconductor substrate having a low-impedance semiconductor substrate having an impedance of 100 Ω·cm or less and an impedance ratio of about 1 to 100 Ω·cm. The semiconductor substrate 12 is, for example, a p-type germanium (Si) wafer produced by a Czochralski (CZ) method. The wafer produced by the CZ method is low in impedance and low in cost compared with a high-impedance wafer produced by a floating zone melting (FZ) method or the like. In one embodiment, the semiconductor substrate 12 has an impedance ratio of 4 Ω·cm and a p-type carrier concentration of 3.4×10 15 cm −3 . [0014] The first element range 22 and the second element range 24 are provided on the main surface 14 of the semiconductor substrate 12. For example, the first semiconductor element 26 for the digital circuit is provided for the first element range 22, and the second semiconductor element 28 for the analog circuit is provided for the second element range 24. The first semiconductor element 26 and the second semiconductor element 28 are, for example, a transistor or a diode. Each of the first element range 22 and the second element range 24 is provided with an impurity diffusion layer for forming a well type range, a source/drain range, and a contact range of the semiconductor element. [0015] In the present specification, a direction orthogonal to the principal surface 14 of the semiconductor substrate 12 is referred to as an up-and-down direction or a depth direction. Further, in the inside of the semiconductor substrate 12, a direction in which the direction toward the main surface 14 is referred to as an upper direction or an upper side, and a direction toward the back surface 16 opposite to the main surface 14 is referred to as a lower direction or a lower side. In addition, there is a direction parallel to the main surface 14, which is referred to as a horizontal direction or a horizontal direction. [0016] A high impedance range 30 is provided for the internal structure of the semiconductor substrate 12. The high impedance range 30-system impedance ratio is higher than the body portion of the semiconductor substrate 12. The high-impedance range 30 has an impedance ratio of 100 Ω·cm or more, and has an impedance ratio of 500 Ω·cm or more, and is preferably 1 kΩ·cm or more. The high impedance range 30 includes: a recess type high impedance range 32 and a planar high impedance range 34. [0017] The groove-type high-impedance range 32 is provided in a separation range 20 between the first element range 22 and the second element range 24, and has a depth from the main surface 14 of the semiconductor substrate 12 toward the back surface 16 Formed. The depth of the groove type high impedance range 32 is 20 μm or more, and is preferably about 50 μm to 200 μm. The groove-type high-impedance range 32 is formed to reach a position deeper than the impurity diffusion layer formed in the first element range 22 or the second element range 24. The groove type high impedance range 32 is, for example, a function of blocking the interference of the analog circuit toward the analog circuit and improving the characteristics of the analog circuit. [0018] The planar high impedance range 34 is in the second element range 24 and extends in the horizontal direction. The planar high-impedance range 34 is provided from the separation range 20, extends over the second element range 24, and extends in the horizontal direction, and is formed to have a high impedance range continuous with the groove-type high-impedance range 32. The planar high impedance range 34 is formed directly below the analog circuit and contributes to the enhancement of the characteristics of the analog circuit. [0019] In the illustrated example, both the groove type high impedance range 32 and the planar high impedance range 34 are formed inside the semiconductor substrate 12, but in the modified example, only the groove type high impedance is provided. One of the range 32 and the planar high impedance range 34 is also possible. [0020] The high impedance range 30 is formed by irradiating hydrogen (H) ions to the main portion of the semiconductor substrate 12 of the low-resistance substrate. When ionizing the wafer, the ions reach the depth of the acceleration energy of the corresponding ions. At this time, in the vicinity of the range including the arrival, lattice defects are formed, and the regularity (periodicity) of the crystal becomes a state of confusion. In such a range of lattice defects, the carrier (electrons or holes) is easily scattered and hinders the movement of the carrier. As a result, in the range in which localized lattice defects are generated by ion irradiation, the impedance ratio is increased before the irradiation. [0021] The position or range in the depth direction in which the impedance ratio is increased by ion irradiation can be adjusted by appropriately selecting the acceleration energy or the irradiation amount of the ion irradiation. For example, by adjusting the acceleration energy of the ions when the ions are irradiated, the depth position at which the high impedance range is formed can be adjusted. Further, the acceleration energy irradiated by the selected ions can be adjusted to form a depth position in the high impedance range, a range in the depth direction (half width), or a diffusion width in the lateral direction. Further, by performing the ion irradiation for a plurality of times while changing the acceleration energy, a thicker high impedance range can be formed throughout the depth direction. [0022] In the present embodiment, hydrogen (H) ions are irradiated with an acceleration energy of 1 MeV or more and 100 MeV or less. For example, a monovalent hydrogen ion ( 1 H + ) is irradiated with an acceleration energy of 4 MeV, 8 MeV, and 17 MeV. As a means for irradiating the ion beam of such an acceleration energy, a device of a cyclotron method or a Van de Graaff method is used. When such an irradiation condition is used, ions can be brought from the vicinity of the main surface 14 of the semiconductor substrate 12 to a position having a depth of 100 μm or more in the germanium wafer. [0023] The impedance ratio in the high impedance range formed by ion irradiation depends on the density (defect density) of the generated lattice defects. According to the findings of the present inventors, it has been found that if the defect density is 1 × 10 17 cm -3 or more, an impedance ratio of 1 kΩ·cm or more can be optimally obtained. When the acceleration energy of the irradiation density is 4 MeV to 17 MeV, the irradiation amount (amount) of hydrogen ions can be made 1×10 13 cm −2 or more. [0024] The high impedance range is formed by doing so, and it is understood that the impedance ratio is lowered when heat treatment is applied. According to the findings of the inventors, when the semiconductor substrate 12 after ion irradiation is heated to 200 ° C or higher, the decrease in the impedance ratio is seen, and when the semiconductor substrate 12 is heated to 300 ° C or more or 400 ° C or more, the resistivity is lowered. Then it drops significantly. This is considered to be because the loss of the lattice defect and the decrease in the defect density are caused by the heat treatment. Accordingly, in the case where a high-impedance range is formed by ion irradiation, it may be preferable to add a heat treatment of 200 ° C or more in a subsequent process. [0025] On the other hand, in order to position the high-impedance range 30 at a position like the target separation range 20 or the second element range 24, before the wafer is cut, that is, before the semiconductor processing is performed, Ion irradiation must be performed. In the post-engineering, wafer bonding or wire bonding is performed, which is called heat treatment of resin sealing, and in these processes, the semiconductor substrate 12 can be heated to a temperature of about 200 ° C to 300 ° C. For this reason, the impedance ratio in the high impedance range is lowered by the heat treatment in the subsequent process, and the desired impedance ratio (for example, 500 Ω·cm or more) cannot be maintained. Therefore, in the present embodiment, the hydrogen-activated person who is driven into the semiconductor substrate 12 by ion irradiation by the heat treatment can maintain the impedance ratio in the high impedance range even after the heat treatment. When the hydrogen is activated by the heat treatment, the concentration of the n-type carrier increases due to the donorization, and the majority of the carrier (p-type carrier) of the p-type semiconductor substrate 12 is neutralized, and the electrical conductivity is lowered. For example, by the activation of hydrogen, the n-type carrier concentration which is the same as the p-type carrier concentration of the semiconductor substrate 12 can be obtained, and the semiconductor substrate 12 can be made neutralized to increase the resistivity. 2 is a graph showing an example of a change in impedance ratio by cerium (He) ion irradiation and heat treatment according to a comparative example. In the comparative example, not hydrogen ions ( 1 H + ) but strontium ions ( 3 He 2+ ) were used. The acceleration energy system was 23 MeV, and the amount was 1.0 × 10 13 cm -2 , and the irradiation target was a p-type ruthenium substrate of about 4 Ω·cm. 2 is a graph showing the impedance ratio distribution in the depth direction of the substrate after ion irradiation (before heat treatment) and after heat treatment (200 ° C, 250 ° C, 300 ° C) before ion irradiation. As shown in the figure, a high impedance range of about 1 to 2 kΩ·cm can be formed up to a depth of about 60 μm before heat treatment, and a high impedance range of a slightly similar impedance ratio distribution can be maintained after heat treatment at 200 °C. However, in the heat treatment at 250 ° C, the impedance ratio in the high-impedance range is less than 1 kΩ·cm, and in part, it is less than 500 Ω·cm, and in the heat treatment after 300 ° C, the impedance ratio in the high-impedance range becomes insufficient. 100Ω・cm. In the case where ion irradiation is performed using ruthenium as described above, it is understood that the impedance ratio in the high impedance range is lowered by heat treatment exceeding 200 ° C, and the impedance ratio is remarkably lowered by heat treatment at 300 ° C or higher. 3 is a graph showing an example of changes in impedance ratios by hydrogen (H) ion irradiation and heat treatment according to the relevant examples. In the present embodiment, hydrogen ions ( 1 H + ) were irradiated, the acceleration energy system was 8 MeV, and the amount was 1.0 × 10 14 cm -2 , and the irradiation target was a p-type germanium substrate of about 4 Ω·cm. Fig. 3 is a graph showing the impedance ratio distribution in the depth direction of the substrate after ion irradiation (before heat treatment) and after heat treatment (250 °C, 400 °C) before ion irradiation. As shown in the figure, a high impedance range of 1 kΩ·cm or more can be formed up to a depth of about 110 μm before heat treatment, and a high impedance range of a slightly similar impedance ratio distribution can be maintained after heat treatment at 250 °C. In addition, after heat treatment at 400 ° C, a high impedance range of 1 kΩ·cm or more can be maintained at a depth of 10 μm to 80 μm. In the case where hydrogen ions are used, even when heat treatment at 200 ° C or heat treatment at 300 ° C or higher is applied, a high impedance range of 500 Ω·cm or more, preferably 1 kΩ·cm or more can be maintained. 4 is a graph showing an example of changes in impedance ratios by hydrogen (H) ion irradiation and heat treatment according to another embodiment. In this embodiment, similarly to FIG. 3 hydrogen ion irradiation (1 H +), 8 MeV acceleration energy system, the object is irradiated lines of about 4Ω · cm p-type silicon substrate. This embodiment uses a different amount from that of Fig. 3, and is a higher amount of 2.6 × 10 -14 cm -2 than the above embodiment. 4 is a graph showing the impedance ratio distribution in the depth direction of the substrate after ion irradiation (before heat treatment) and after heat treatment (200 ° C, 300 ° C, 400 ° C) before ion irradiation. As shown in the figure, a high impedance range of 1 kΩ·cm or more can be formed up to a depth of about 45 μm before heat treatment, and a high impedance range of a slightly similar impedance ratio distribution can be maintained after heat treatment at 200 °C. However, in the heat treatment at 300 ° C, the resistivity at a depth of 10 to 30 μm is less than 1 kΩ·cm, and after heat treatment at 400 ° C, it is less than 100 Ω·cm. This is because the reason is that when the amount of hydrogen ions is increased, hydrogen is excessively applied, and the conductivity type is inverted from p-type to n-type, and the impedance is increased by the concentration of the n-type carrier which becomes a majority of carriers. The rate is down. [0030] From the above comparative examples and examples, in order to maintain a high resistivity (500 Ω·cm or more) after heat treatment exceeding 200 ° C, it is necessary to appropriately control the amount of hydrogen ions and heat treatment. Temperature. [0031] FIG. 5 is a graph showing the activation rate of hydrogen by heat treatment, and shows the relationship between temperature and activation rate. As shown in the figure, the activation rate of hydrogen in the range of 200 ° C to 400 ° C is low, and the increase in the activation rate via the temperature rise is also slow. On the other hand, when it exceeds 400 ° C, the rate of increase in the activation rate via the temperature rise becomes large, and the value of the activation rate also exceeds 10%. In the heat treatment using a range of 200° C. to 400° C. which is a gentle increase in the activation rate by the temperature increase, even if there is an individual difference in the temperature of the heat treatment in the subsequent work, the treatment can be suppressed. Significant changes in the impedance ratio of different temperatures. 6 is a graph schematically showing changes in carrier concentration via heat treatment, and for different three hydrogen densities, the value of the n-type carrier concentration which is subjected to physicalization by heat treatment is schematically shown. The A system has a hydrogen density of 5 × 10 16 cm -3 and corresponds to the embodiment of Fig. 3 (energy: 8 MeV, amount: 1.0 × 10 14 cm -2 ). The B system has a hydrogen density of 1.3 × 10 17 cm -3 and corresponds to the embodiment of Fig. 4 (energy: 8 MeV, amount: 2.6 × 10 14 cm -2 ). The hydrogen density of the C system is 5 × 10 15 cm -3 , and the hydrogen density of the D system is 2.5 × 10 16 cm -3 . However, the dotted line in the graph shows the p-type carrier concentration in the semiconductor substrate, which is 3.4 × 10 15 cm -3 . In the case of A, the concentration of the n-type carrier becomes about 1.0×10 15 cm −3 at 200° C., and at the level of 330° C., it is the same as the concentration of the p-type carrier of the substrate of 3.4×10 15 cm −3 . The degree is about 6.0 × 10 15 cm -3 at 400 °C. As a result, the decrease in the resistivity through the recovery of the lattice defect becomes a significant range of 250 ° C to 400 ° C, and the p-type carrier concentration and the n-type carrier concentration are the same, and the substrate can be neutralized with high impedance. Rate. As a result, as shown in FIG. 3, even if heat treatment is applied at 200 ° C to 400 ° C, high impedance of 1 kΩ·cm or more can be maintained. [0034] In the case of B, the concentration of the n-type carrier is about 2.6×10 15 cm −3 at 200° C., and the concentration of the p-type carrier of the substrate is 3.4×10 15 cm −3 at the level of 230° C. The degree is about 6.8 × 10 15 cm -3 which is twice the concentration of the p-type carrier of the substrate, and is 1.0 × 10 16 cm -3 or more at 350 °C or higher. As a result, as shown in FIG. 4, when the heat treatment at 300 ° C or higher is performed, the impedance ratio is lowered by the n-type inversion of the substrate, and when the heat treatment is performed at 400 ° C, the impedance ratio of the substrate is further lowered. [0035] In the case of C, the hydrogen density is 0.1 times that of A, and the carrier concentration due to the hydrogenation of the hydrogen is reduced, and even if a heat treatment of 400 ° C or more is added, the p-type carrier of the substrate is not obtained. Concentration (3.4 × 10 15 cm -3 ). As a result, it is considered that even if heat treatment is applied at 200 ° C to 400 ° C, the neutralization of the substrate is not generated, and only the decrease in the resistivity due to the decrease in the defect density occurs. In the case of D, the hydrogen density is 0.5 times that of A, and even if the heat treatment at 200 ° C to 400 ° C is added, the p-type carrier concentration of the substrate (3.4 × 10 15 cm -3 ) is not obtained, and it is considered that The substrate is neutralized, and only a decrease in the impedance ratio due to the reduction in defect density occurs. 7 is a graph showing an example of the relationship between the hydrogen density and the change in the resistivity through heat treatment, and shows the change in the impedance ratio for the conditions A, B, C, and D set in FIG. 6. As shown in the figure, in the case of A (hydrogen density: 5 × 10 16 cm -3 ), it is possible to maintain a high resistance of 1 kΩ·cm or more in the range of 200 ° C to 400 ° C. In the case of B (hydrogen density: 1.3 × 10 17 cm -3 ), a high impedance of 500 Ω·cm or more can be maintained in the range of 200 ° C to 300 ° C. However, at 350 ° C or higher, the impedance ratio becomes 200 Ω·cm. the following. In the case of C (hydrogen density: 5 × 10 15 cm -3 ), high resistance of 1 kΩ·cm or more can be maintained in the heat treatment at 200 ° C, but when the heat treatment exceeds 200 ° C, the impedance ratio is remarkably lowered, and at 250 After heat treatment at a temperature above °C, it is 10 Ω·cm or less. This is considered to be due to the fact that the hydrogen density is small and the concentration of the n-type carrier which is neutralized is insufficient. In the case of D (hydrogen density: 2.5 × 10 16 cm -3 ), the high impedance of 500 Ω·cm or more can be maintained in the range of 200 ° C to 230 ° C. However, the impedance ratio is 200 Ω at 250 ° C or higher. Below cm. From the above studies, it is necessary to achieve an n-type carrier concentration which is the same as the p-type carrier concentration of the semiconductor substrate 12 in a temperature range of 200 ° C to 400 ° C even after heat treatment. The activation rate of hydrogen by heat treatment at 200 ° C to 400 ° C is about 2% to 10%, and the hydrogen density of 10 to 50 times the p-type carrier concentration of the semiconductor substrate 12 can be achieved. In general, the p-type carrier concentration of a low-impedance (1 to 100 Ω·cm) p-type germanium substrate is from 10 14 to 10 16 cm -3 , for example, 5 × 10 15 cm -3 or more and 2 × can be realized. The hydrogen density of 10 -17 cm -3 or less can be used. For example, when the concentration of the p-type carrier is 3.4 × 10 15 cm -3 , the hydrogen density of 3.4 × 10 16 cm -3 or more and 1.7 × 10 -17 cm -3 or less is preferable. [0038] However, when at least a part of the conductivity type of the high-impedance range 30 is inverted to the n-type, the pn junction is formed in the high-impedance range, which affects the operation of the circuit elements formed on the semiconductor substrate 12. Hey. In order to suppress such an influence, the concentration of the n-type carrier activated by hydrogen may not exceed the p-type carrier concentration of the semiconductor substrate 12, and the value of the hydrogen density may be controlled. That is, the conductivity type of the high-impedance range 30 is such that the p-type ground is maintained, and the hydrogen density and the heat treatment temperature can be controlled. 8 is a graph showing an example of the relationship between the amount of hydrogen ion irradiation and the hydrogen density, and is shown for the case where the acceleration energy of hydrogen ions is 4 MeV, 8 MeV, and 17 MeV. As shown, the amount of hydrogen ions is proportional to the hydrogen density after irradiation. In addition, the lower the irradiation energy, the higher the hydrogen density obtained. When the acceleration energy is low, the range of the depth direction in which the hydrogen ions are implanted is limited, and the amount of hydrogen injection per unit area is increased. From the graph, in order to achieve a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 -17 cm -3 or less, for a case of 4 MeV, for example, as 1 × 10 -13 cm -2 or more and 2 × 10 -14 cm -2 or less, and in the case of 8 MeV, as 1 × 10 -13 cm -2 or more, 4 × 10 -14 cm -2 or less, and 17 MeV, as 3.6 × 10 -13 cm -2 or more and 1 × 10 -15 Cm -2 or less. However, when ion irradiation is performed in an amount of such an amount, a defect density of 1 × 10 17 cm -3 or more can be obtained, and in a state before heat treatment, a high resistivity of 500 Ω·cm or more can be achieved. . [0040] Next, a method of manufacturing the semiconductor device 10 of the present embodiment will be described. FIG. 9 is a flow chart showing a method of manufacturing the semiconductor device 10 in a schematic manner. First, a device is formed on the p-type semiconductor substrate 12 (S10) through various processes, and a wiring layer is formed on the semiconductor substrate 12, and a protective film for protecting the formed element or wiring is formed (S14). The engineering of S10~S14 is a project called "pre-engineering" in semiconductor processing, and can perform high-temperature processing of 400 °C or higher, such as thermal oxidation, thermal diffusion, CVD, and annealing. Next, hydrogen ions are irradiated onto the semiconductor substrate 12 to form a high-impedance range 30 (S16), and the back surface of the semiconductor substrate 12 is polished (S18). The engineering of S16 and S18 is a so-called "intermediate project" or a project called "PPP (Post Passive Process)". [0041] Next, the process (S20) after the heat treatment is performed is completed as a semiconductor integrated circuit. In the post-S20 engineering, for example, the process of dicing a wafer for dicing, bonding the diced wafer to the mounting substrate, and bonding the mounting substrate to the wafer by wire bonding to The process of sealing the wafer with resin, and the like. For example, in the wafer bonding process, the wire bonding process, and the resin sealing process, heat treatment is performed at a temperature of about 200 ° C to 300 ° C. In one embodiment, the maximum temperature of the heat treatment is about 260 ° C. However, an annealing treatment for separately heating the semiconductor device 10 in conjunction with the bonding or sealing process may be performed. In the annealing treatment, when the high-impedance range 30 is heated at a specific temperature of 200 ° C or more and 400 ° C or less, the impedance ratio of the high-impedance range 30 may be stabilized. This annealing treatment is sufficient for a short period of time of 10 minutes or less, and may be 5 minutes or less, 1 minute or less, or 30 seconds or less. [0042] The present invention has been described above based on the embodiments. The present invention is not limited to the above-described embodiments, and various design changes can be made. However, it is understood by those skilled in the art that various modifications can be made, or such modifications are also included in the scope of the present invention. [0043] In the above embodiment, it is assumed that only the hydrogen ions are irradiated to form the high impedance range 30. In the modified example, a high impedance range may be formed by combining ions other than hydrogen. For example, the hydrogen density in the above numerical range can be achieved by hydrogen ion irradiation, and the defect density of the above numerical value can be realized by irradiating an ion species other than hydrogen. In a certain modification, when the irradiation of the hydrogen ions and the cerium ions is combined, even if heat treatment at 200 ° C or higher is performed, a high impedance range capable of maintaining high impedance (500 Ω·cm or more) can be formed.

[0044][0044]

10‧‧‧半導體裝置10‧‧‧Semiconductor device

12‧‧‧半導體基板12‧‧‧Semiconductor substrate

14‧‧‧主面14‧‧‧Main face

16‧‧‧背面16‧‧‧Back

18‧‧‧配線層18‧‧‧Wiring layer

20‧‧‧分離範圍20‧‧‧Separation range

22‧‧‧第1元件範圍22‧‧‧1st component range

24‧‧‧第2元件範圍24‧‧‧2nd component range

26‧‧‧第1半導體元件26‧‧‧1st semiconductor component

28‧‧‧第2半導體元件28‧‧‧2nd semiconductor component

30‧‧‧高阻抗範圍30‧‧‧High impedance range

32‧‧‧凹槽型高阻抗範圍32‧‧‧ Groove type high impedance range

34‧‧‧平面型高阻抗範圍34‧‧‧Flat type high impedance range

[0010]   圖1係模式性地顯示有關實施形態的半導體裝置之構造的剖面圖。   圖2係顯示經由有關比較例之氦(He)離子照射及熱處理之阻抗率變化之一例的圖表。   圖3係顯示經由有關實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。   圖4係顯示經由有關另外實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。   圖5係顯示經由熱處理之氫的活性化率的圖表。   圖6係模式性地顯示經由熱處理之載體濃度變化的圖表。   圖7係顯示氫密度與經由熱處理之阻抗率變化的關係之一例的圖表。   圖8係顯示氫離子照射之量數量與氫密度之關係的一例之圖表。   圖9係模式性顯示半導體裝置之製造方法的流程圖。1 is a cross-sectional view schematically showing a structure of a semiconductor device according to an embodiment. Fig. 2 is a graph showing an example of changes in impedance ratio by cerium (He) ion irradiation and heat treatment according to a comparative example. Fig. 3 is a graph showing an example of changes in impedance ratio by hydrogen (H) ion irradiation and heat treatment according to the relevant examples. Fig. 4 is a graph showing an example of changes in impedance ratios by hydrogen (H) ion irradiation and heat treatment according to another embodiment. Fig. 5 is a graph showing the activation rate of hydrogen via heat treatment. Fig. 6 is a graph schematically showing changes in carrier concentration via heat treatment. Fig. 7 is a graph showing an example of the relationship between the hydrogen density and the change in the resistivity through heat treatment. Fig. 8 is a graph showing an example of the relationship between the amount of hydrogen ion irradiation and the hydrogen density. 9 is a flow chart showing a method of manufacturing a semiconductor device in a schematic manner.

Claims (9)

一種半導體裝置之製造方法,其特徵為具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為5×1015 cm-3 以上2×1017 cm-3 以下之範圍,形成阻抗率則較離子照射前之前述p型半導體基板為高之高阻抗範圍者,   和以200℃以上400℃以下之溫度而加熱形成有前述高阻抗範圍之p型半導體基板者。A method of manufacturing a semiconductor device, comprising: irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and having a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less In the range, the impedance ratio is higher than the high-impedance range of the p-type semiconductor substrate before ion irradiation, and the p-type semiconductor substrate having the high-impedance range formed by heating at a temperature of 200 ° C or higher and 400 ° C or lower. 如申請專利範圍第1項記載之半導體裝置之製造方法,其中,前述高阻抗範圍係缺陷密度成為1×1017 cm-3 以上地加以形成者。The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the high-impedance range is formed by forming a defect density of 1 × 10 17 cm -3 or more. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,形成有前述高阻抗範圍之p型半導體基板係以200℃以上300℃以下之溫度而加以加熱者。The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the p-type semiconductor substrate having the high-impedance range is heated at a temperature of 200 ° C or more and 300 ° C or less. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,前述高阻抗範圍係經由照射能量為4MeV以上17MeV以下、量數量為2×1013 cm-2 以上2×1014 cm-2 以下之氫離子照射而加以形成者。The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the high-impedance range is 4 MeV or more and 17 MeV or less, and the quantity is 2 × 10 13 cm -2 or more and 2 × 10 14 A hydrogen ion of cm -2 or less is irradiated and formed. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,前述加熱的時間係10分鐘以下者。The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the heating time is 10 minutes or shorter. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,前述離子照射前之p型半導體基板之阻抗率係100Ωcm以下,而前述加熱後之前述高阻抗範圍的阻抗率係500Ωcm以上者。The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the impedance ratio of the p-type semiconductor substrate before the ion irradiation is 100 Ωcm or less, and the impedance ratio of the high-impedance range after the heating is 500Ωcm or more. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,前述高阻抗範圍係氫密度成為前述離子照射前之p型半導體基板的載體濃度之10倍以上50倍以下的值地加以形成者。The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the high-impedance range is such that the hydrogen density is 10 times or more and 50 times or less the carrier concentration of the p-type semiconductor substrate before the ion irradiation. The land is formed. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,前述高阻抗範圍係前述加熱後之導電型為p型者。The method of manufacturing a semiconductor device according to the first or second aspect of the invention, wherein the high-impedance range is such that the conductive type after heating is p-type. 一種半導體裝置,其特徵為具備:p型半導體基板,和加以設置於前述p型半導體基板上之半導體元件,和加以設置於前述p型半導體基板內之高阻抗範圍;   前述高阻抗範圍係氫密度則成為5×1015 cm-3 以上2× 1017 cm-3 以下之範圍,阻抗率則較前述p型半導體基板為高之範圍者。A semiconductor device comprising: a p-type semiconductor substrate; and a semiconductor element provided on the p-type semiconductor substrate; and a high-impedance range provided in the p-type semiconductor substrate; wherein the high-impedance range is hydrogen density In the range of 5 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less, the impedance ratio is higher than that of the p-type semiconductor substrate.
TW106141097A 2016-12-02 2017-11-27 Semiconductor device and manufacturing method of semiconductor device TWI662598B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2016-234920 2016-12-02
JP2016234920 2016-12-02
JP2017205248A JP7125257B2 (en) 2016-12-02 2017-10-24 Semiconductor device and method for manufacturing semiconductor device
JP2017-205248 2017-10-24

Publications (2)

Publication Number Publication Date
TW201834029A true TW201834029A (en) 2018-09-16
TWI662598B TWI662598B (en) 2019-06-11

Family

ID=62566347

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106141097A TWI662598B (en) 2016-12-02 2017-11-27 Semiconductor device and manufacturing method of semiconductor device

Country Status (2)

Country Link
JP (1) JP7125257B2 (en)
TW (1) TWI662598B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI756565B (en) * 2018-12-26 2022-03-01 日商住重愛特科思股份有限公司 Manufacturing method of semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7094840B2 (en) * 2018-09-06 2022-07-04 住重アテックス株式会社 Manufacturing method of semiconductor device
JP7169872B2 (en) * 2018-12-26 2022-11-11 住重アテックス株式会社 Semiconductor device and method for manufacturing semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202976A (en) * 1984-03-28 1985-10-14 Toshiba Corp Buried type semiconductor laser
JPH05102161A (en) * 1991-07-15 1993-04-23 Toshiba Corp Manufacture of semiconductor device, and the semiconductor device
JP4556255B2 (en) 1998-12-07 2010-10-06 株式会社デンソー Manufacturing method of semiconductor device
JP5104314B2 (en) 2005-11-14 2012-12-19 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP2009194197A (en) 2008-02-15 2009-08-27 Panasonic Corp Semiconductor device and its manufacturing method
JP6099553B2 (en) 2013-12-18 2017-03-22 住重試験検査株式会社 Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI756565B (en) * 2018-12-26 2022-03-01 日商住重愛特科思股份有限公司 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
TWI662598B (en) 2019-06-11
JP7125257B2 (en) 2022-08-24
JP2018093184A (en) 2018-06-14

Similar Documents

Publication Publication Date Title
JP6237902B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP6319454B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN105103290B (en) The manufacture method of semiconductor device
WO2016042954A1 (en) Semiconductor device and method for manufacturing semiconductor device
TW201834029A (en) Semiconductor device and manufacturing method of semiconductor device which can form a high-resistance region capable of withstanding heat treatment above 200 degree Celsius
JP2009099714A (en) Semiconductor apparatus and method of manufacturing the same
CN105321819B (en) The manufacturing method of semiconductor device
TWI682520B (en) Semiconductor device and method of manufacturing semiconductor device
US10043867B2 (en) Latchup reduction by grown orthogonal substrates
JP6557134B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP6883745B2 (en) Semiconductor devices and their manufacturing methods
TWI727422B (en) Semiconductor device and semiconductor device manufacturing method
TWI717801B (en) Manufacturing method of semiconductor device
TWI756565B (en) Manufacturing method of semiconductor device
US8093115B2 (en) Tuning of SOI substrate doping
TW201814900A (en) Semiconductor device and manufacturing method of semiconductor device capable of improving the noise blocking characteristic among a plurality of circuit regions formed on a semiconductor substrate
JP7443735B2 (en) Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device
JP2017126764A (en) Method of manufacturing semiconductor device
TW201227931A (en) Semiconductor apparatus and manufacturing method thereof
DE102008008498B4 (en) A method for reducing punch-through tilt between doped semiconductor regions and semiconductor device
GB2561391A (en) Silicon carbide transistor with UV Sensitivity
JP2009272324A (en) Method of manufacturing semiconductor device
JP2018088467A (en) Semiconductor device
JPH05218399A (en) Manufacture of semiconductor device
JP2010062463A (en) Method of manufacturing semiconductor device and semiconductor device