TWI662598B - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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TWI662598B
TWI662598B TW106141097A TW106141097A TWI662598B TW I662598 B TWI662598 B TW I662598B TW 106141097 A TW106141097 A TW 106141097A TW 106141097 A TW106141097 A TW 106141097A TW I662598 B TWI662598 B TW I662598B
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range
semiconductor substrate
hydrogen
type semiconductor
heat treatment
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TW201834029A (en
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井上剛
八木宏親
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日商住重愛特科思股份有限公司
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Abstract

本發明係一種半導體裝置及半導體裝置之製造方法,其課題為可形成可耐200℃以上之熱處理的高阻抗範圍。   解決手段為半導體裝置(10)之製造方法係具備:於形成有半導體元件之p型半導體基板(12)照射氫(H)離子,而氫密度則成為2×1015 cm-3 以上2×1017 cm-3 以下之範圍,形成阻抗率則較離子照射前之p型半導體基板(12)為高之高阻抗範圍(30)者,和以200℃以上400℃以下之溫度而加熱形成有高阻抗範圍(30)之p型半導體基板(12)者。The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The subject is to form a high-impedance range that can withstand heat treatment at 200 ° C or higher. The solution is a method for manufacturing a semiconductor device (10). The method includes: irradiating hydrogen (H) ions on a p-type semiconductor substrate (12) on which a semiconductor element is formed, and a hydrogen density of 2 × 10 15 cm −3 or more and 2 × 10 In the range of 17 cm -3 or less, the formation resistance is higher than that of the p-type semiconductor substrate (12) before ion irradiation, and the high resistance range (30) is higher than that formed by heating at a temperature of 200 ° C to 400 ° C. Those with a p-type semiconductor substrate (12) in the impedance range (30).

Description

半導體裝置及半導體裝置之製造方法Semiconductor device and manufacturing method of semiconductor device

[0001] 本發明係有關半導體裝置及半導體裝置之製造方法。[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] 近年,CMOS技術提升,而使類比電路與數位電路混載之SoC (System on a Chip)則加以使用於種種用途。在如此混載在晶片中,為了類比電路之特性提升而於半導體基板內,加以形成有高阻抗範圍。例如,經由自元件範圍的背面加速改變能量同時,複數次進行離子照射之時,加以形成為了干擾減低之高阻抗範圍(例如,參照專利文獻1)。 [先前技術文獻] [專利文獻]   [0003] [專利文獻1] 日本特開2015-119039號公報[0002] In recent years, CMOS technology has improved, and SoCs (System on a Chip) that mix analog circuits with digital circuits have been used for various purposes. A high impedance range is formed in a semiconductor substrate in such a way as to be mixed in a wafer in order to improve the characteristics of an analog circuit. For example, when the energy is changed by accelerating from the back surface of the element range, and when ion irradiation is performed a plurality of times, a high impedance range is formed to reduce interference (for example, refer to Patent Document 1). [Prior Art Document] [Patent Document] [0003] [Patent Document 1] Japanese Patent Laid-Open No. 2015-119039

[發明欲解決之課題]   [0004] 在上述的文獻中,加以報告有:當於經由離子照射而形成之高阻抗範圍,加上200℃以上的熱處理時,產生有阻抗率之顯著下降者,而加以記載有:將阻抗率的安定化作為目的而加上200℃以下的熱處理者為佳之內容。但在半導體裝置之製造工程中,有加以執行伴隨200℃以上的熱處理之後工程,而此情況,成為無法維持經由離子照射而得到之高阻抗率。   [0005] 本發明之某形態的例示目的之一係提供:形成可耐200℃以上之熱處理之高阻抗範圍的技術者。 [為了解決課題之手段]   [0006] 本發明之某形態的半導體裝置之製造方法係具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為2×1015 cm-3 以上2×1017 cm-3 以下之範圍,形成阻抗率則較離子照射前之p型半導體基板為高之高阻抗範圍者,和以200℃以上400℃以下之溫度而加熱形成有高阻抗範圍之p型半導體基板者。   [0007] 本發明之另外的形態係半導體裝置。此裝置係具備:p型半導體基板,和加以設置於p型半導體基板上之半導體元件,和加以設置於p型半導體基板內之高阻抗範圍。高阻抗範圍係氫密度則成為2×1015 cm-3 以上2×1017 cm-3 以下之範圍,阻抗率則較p型半導體基板為高之範圍。   [0008] 然而,將以上之構成要素的任意組合或本發明之構成要素或表現,在方法,裝置,系統等之間相互進行置換之構成亦另外,作為本發明之形態而為有效。 [發明效果]   [0009] 如根據本發明,可形成可耐200℃以上之熱處理的高阻抗範圍。[Problems to be Solved by the Invention] [0004] In the above literature, it is reported that when a high resistance range formed by ion irradiation is added to a heat treatment at 200 ° C or higher, a significant decrease in the resistivity occurs, In addition, it is described that it is preferable to use a heat treatment at 200 ° C or lower for the purpose of stabilization of the resistivity. However, in the manufacturing process of the semiconductor device, there is a process after performing a heat treatment at 200 ° C or higher. In this case, it is impossible to maintain a high resistivity obtained by ion irradiation. [0005] One of the exemplified objects of one aspect of the present invention is to provide a technician who forms a high impedance range that can withstand heat treatment at 200 ° C or higher. [Means for Solving the Problem] [0006] A method for manufacturing a semiconductor device according to one aspect of the present invention includes irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and the hydrogen density is 2 × 10 15 cm -3 or more, 2 × 10 17 cm -3 or less, the formation impedance is higher than that of the p-type semiconductor substrate before ion irradiation, and the high resistance range is formed by heating at a temperature of 200 ° C to 400 ° C. High-impedance p-type semiconductor substrate. [0007] Another aspect of the present invention is a semiconductor device. This device includes a p-type semiconductor substrate, a semiconductor element provided on the p-type semiconductor substrate, and a high impedance range provided in the p-type semiconductor substrate. The high impedance range means that the hydrogen density is in the range of 2 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less, and the resistivity is in a range higher than that of the p-type semiconductor substrate. [0008] However, a configuration in which any combination of the above constituent elements or the constituent elements or expressions of the present invention are replaced with each other among methods, devices, systems, etc. is also effective as a form of the present invention. [Effects of the Invention] [0009] According to the present invention, a high impedance range capable of withstanding heat treatment at 200 ° C or higher can be formed.

[0011] 以下,對於為了實施本發明之形態,詳細地加以說明。然而,以下所敘述之構成係為例示,而非限定任何本發明之範圍者。另外,在圖面的說明中對於同一要素,係附上同一符號而適宜省略重複之說明。另外,在以下的說明中,在參照之各剖面圖,半導體基板或其他的層之厚度或尺寸係為說明方便之構成,而未必為顯示實際尺寸或比率者。   [0012] 圖1係模式性地顯示有關實施形態的半導體裝置10之構造的剖面圖。半導體裝置10係系統LSI或單晶片系統之積體電路(IC)。半導體裝置10係具備:半導體基板12與配線層18。   [0013] 半導體基板12係阻抗率為100Ω・cm以下之低阻抗的半導體基板,而阻抗率為1~100Ω・cm程度之半導體基板。半導體基板12係例如,經由柴可拉斯基(CZ)法而加以製作之p型的矽(Si)晶圓。經由CZ法而加以製作的晶圓係與經由懸浮區熔(FZ)法等而加以製作之高阻抗晶圓作比較,阻抗率為低,且廉價。在某個實施例中,半導體基板12之阻抗率係4Ω・cm,而p型載體濃度為3.4×1015 cm-3 。   [0014] 對於半導體基板12之主面14係加以設置第1元件範圍22與第2元件範圍24。例如,對於第1元件範圍22係加以設置數位電路用之第1半導體元件26,而對於第2元件範圍24係加以設置類比電路用之第2半導體元件28。第1半導體元件26及第2半導體元件28係例如,電晶體或二極體等。對於各第1元件範圍22及第2元件範圍24係加以設置有為了形成半導體元件之阱型範圍,源極/汲極範圍,接點範圍等之不純物擴散層。   [0015] 在本說明書中,有著將正交於半導體基板12之主面14的方向,稱為上下方向或深度方向者。另外,在半導體基板12之內部中,有著將朝向主面14之方向,稱為上方向或上側,而將朝向於與主面14相反的背面16之方向,稱為下方向或下側者。另外,有著將平行於主面14之方向,稱為橫方向或水平方向者。   [0016] 對於半導體基板12之內部係加以設置有高阻抗範圍30。高阻抗範圍30係阻抗率則較半導體基板12之主體部分為高之範圍。高阻抗範圍30係具有100Ω・cm以上之阻抗率,例如具有500Ω・cm以上之阻抗率,而理想為1kΩ・cm以上。高阻抗範圍30係包含:凹槽型高阻抗範圍32與平面型高阻抗範圍34。   [0017] 凹槽型高阻抗範圍32係加以設置於第1元件範圍22與第2元件範圍24之間的分離範圍20,呈具有自半導體基板12之主面14朝向於背面16程度之深度地加以形成。凹槽型高阻抗範圍32之深度係20μm以上,而理想為50μm~200μm程度。凹槽型高阻抗範圍32係呈到達至較形成於第1元件範圍22或第2元件範圍24之不純物擴散層為深的位置地加以形成。凹槽型高阻抗範圍32係例如,具有遮斷自數位電路朝向於類比電路之干擾而使類比電路之特性提升之機能。   [0018] 平面型高阻抗範圍34係在第2元件範圍24中,延伸存在於水平方向。平面型高阻抗範圍34係自分離範圍20,遍布於第2元件範圍24而延伸存在於水平方向,呈形成與凹槽型高阻抗範圍32連續之高阻抗範圍地加以設置亦可。平面型高阻抗範圍34係由形成於類比電路之正下方者,而貢獻於類比電路之特性提升。   [0019] 在圖示的例中,於半導體基板12之內部,加以形成有凹槽型高阻抗範圍32與平面型高阻抗範圍34之雙方,但在變形例中,僅設置凹槽型高阻抗範圍32及平面型高阻抗範圍34之任一方亦可。   [0020] 高阻抗範圍30係經由照射氫(H)離子於低阻抗基板之半導體基板12的主體部分之時而加以形成。當對於晶圓進行離子照射時,離子則到達至因應離子之加速能量之深度為止。此時,在包含到達之範圍的附近中,形成有晶格缺陷,而結晶的規則性(週期性)成為混亂之狀態。在如此之晶格缺陷為多之範圍中,載體(電子或電洞)則成為被容易散亂,而阻礙載體的移動。其結果,在經由離子照射而局部性之晶格缺陷產生之範圍中,比較於照射前,阻抗率則上升。   [0021] 經由離子照射而阻抗率上升之深度方向的位置或範圍,係可由適宜選擇離子照射之加速能量或照射量而作調整。例如,由調整離子照射時之離子的加速能量者,可調整形成有高阻抗範圍之深度位置。另外,由選擇離子照射的加速能量者,可調整形成高阻抗範圍之深度位置,深度方向之範圍(半寬度)或橫方向之擴散寬度。更且,由使加速能量變化之同時,進行複數次之離子照射者,可遍布於深度方向而形成更厚之高阻抗範圍。   [0022] 在本實施形態中,以1MeV以上、100MeV以下之加速能量而照射氫(H)離子。例如,以4MeV、8MeV、17MeV之加速能量而照射1價的氫離子(1 H+ )。作為照射如此之加速能量的離子束之裝置,加以使用迴旋加速方式或凡德格拉夫方式之裝置。經由使用如此之照射條件之時,在矽晶圓中,可使離子自半導體基板12之主面14的附近到達至深度100μm以上之位置者。   [0023] 經由離子照射而加以形成之高阻抗範圍的阻抗率係依存於所生成之晶格缺陷的密度(缺陷密度)。如根據本發明者們之見解,了解到缺陷密度如為1×1017 cm-3 以上,可最佳地得到1kΩ・cm以上之阻抗率者。如此之缺陷密度係照射離子的加速能量如為4MeV~17MeV時,可由將氫離子的照射量(量數量)作為1×1013 cm-2 以上者而實現。   [0024] 由如此作為而加以形成高阻抗範圍係了解到經由加上熱處理之時,阻抗率則下降者。如根據發明者們之見解,由將離子照射後之半導體基板12加熱至200℃以上者,看到阻抗率之下降,而當將半導體基板12加熱至300℃以上或400℃以上時,阻抗率則顯著地下降。此係認為原因為經由熱處理,晶格缺陷則恢復而缺陷密度則下降者。隨之,經由離子照射而形成高阻抗範圍之情況,在之後的工程中,或許為加上200℃以上的熱處理者為佳。   [0025] 另一方面,對於為了將高阻抗範圍30位置於如同目標之分離範圍20或第2元件範圍24之位置,係在切割晶圓之前,也就是在較半導體處理之後工程為前的階段,必須執行離子照射。在後工程中,進行晶片接合或導線接合,稱為樹脂封閉之熱處理,而在此等工程中,可將半導體基板12加熱為200℃~300℃程度之溫度。為此,經由在後工程之熱處理而高阻抗範圍的阻抗率則下降,而有無法維持所期望之阻抗率(例如,500Ω・cm以上)之虞。   [0026] 因此,在本實施形態中,由經由熱處理而使經由離子照射而打入至半導體基板12的氫活性化者,即使在熱處理後,亦可作為呈維持高阻抗範圍的阻抗率。當經由熱處理而使氫活性化時,經由施體化而n型載體濃度則增加之故,而將p型之半導體基板12之多數載體(p型載體)加以中性化,導電率則下降。例如,由經由氫的活性化,而作為呈可得到與半導體基板12之p型載體濃度同程度之n型載體濃度者,可將半導體基板12作為中性化而提升阻抗率。   [0027] 圖2係顯示經由有關比較例之氦(He)離子照射及熱處理之阻抗率變化之一例的圖表。在比較例中,並非氫離子(1 H+ ),而使用氦離子(3 He2+ )。加速能量係23MeV,而量數量係1.0×1013 cm-2 ,而照射對象係約4Ω・cm之p型矽基板。圖2係顯示離子照射前,離子照射後(熱處理前)及熱處理後(200℃,250℃,300℃)之基板的深度方向之阻抗率分布。如圖示,在熱處理前中,可至60μm程度之深度為止形成1~2kΩ・cm程度之高阻抗範圍,而在200℃之熱處理後,亦可維持略同樣之阻抗率分布的高阻抗範圍。但在250℃之熱處理後中,高阻抗範圍之阻抗率為不足1kΩ・cm,而部分性來說係成為不足500Ω・cm,而在300℃之熱處理後中,高阻抗範圍之阻抗率成為不足100Ω・cm。對於如此使用氦而進行離子照射之情況,係了解到經由超過200℃之熱處理而高阻抗範圍的阻抗率則下降,而經由300℃以上之熱處理,阻抗率則明顯地下降者。   [0028] 圖3係顯示經由有關實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。本實施例係照射氫離子(1 H+ ),加速能量係8MeV,而量數量係1.0×1014 cm-2 ,而照射對象係約4Ω・cm之p型矽基板。圖3係顯示離子照射前,離子照射後(熱處理前)及熱處理後(250℃,400℃)之基板的深度方向之阻抗率分布。如圖示,在熱處理前中,可至110μm程度之深度為止形成1kΩ・cm以上之高阻抗範圍,而在250℃之熱處理後,亦可維持略同樣之阻抗率分布的高阻抗範圍。另外,在400℃之熱處理後,亦可在10μm~80μm之深度中,維持1kΩ・cm以上之高阻抗範圍者。如此,由使用氫離子者,即使在加上超過200℃之熱處理或300℃以上之熱處理的情況,亦可維持500Ω・cm以上、理想為1kΩ・cm以上之高阻抗範圍。   [0029] 圖4係顯示經由有關另外實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。本實施例中,與圖3同樣地照射氫離子(1 H+ ),加速能量係8MeV,而照射對象係約4Ω・cm之p型矽基板。本實施例係使用與圖3不同之量數量,而作為較上述之實施例為高量數量之2.6×10-14 cm-2 。圖4係顯示離子照射前,離子照射後(熱處理前)及熱處理後(200℃,300℃,400℃)之基板的深度方向之阻抗率分布。如圖示,在熱處理前中,可至45μm程度之深度為止形成1kΩ・cm以上之高阻抗範圍,而在200℃之熱處理後,亦可維持略同樣之阻抗率分布的高阻抗範圍。但在300℃之熱處理後中,深度10~30μm程度之阻抗率則成為不足1kΩ・cm,而在400℃之熱處理後中係成為不足100Ω・cm。此係認為原因為經由增加氫離子之量數量之時,氫則過剩地被施體化,導電型則自p型反轉為n型,經由成為多數載體之n型載體濃度的增大而阻抗率則下降者。   [0030] 從以上的比較例及實施例,對於在超過200℃之熱處理後中,亦為了維持高阻抗率(500Ω・cm以上),係可說必須適當地控制氫離子之量數量及熱處理之溫度者。   [0031] 圖5係顯示經由熱處理之氫的活性化率之圖表,而顯示溫度與活性化率之關係。如圖示,200℃~400℃之範圍係氫的活性化率為低,經由溫度上升之活性化率的增加亦為徐緩。另一方面,當超過400℃時,經由溫度上升之活性化率的增加率則變大,而活性化率的值亦超過10%。隨之,由使用經由溫度上升之活性化率的增加為徐緩之200℃~400℃的範圍之熱處理者,即使在對於在後工程之熱處理的溫度產生有個體差之情況,亦可抑制經由處理溫度的不同之阻抗率的顯著變化者。   [0032] 圖6係模式性地顯示經由熱處理之載體濃度變化的圖表,而對於不同之三個氫密度,模式性地顯示經由熱處理而加以施體化之n型載體濃度的值。A係氫密度為5×1016 cm-3 ,而對應於圖3之實施例(能量:8MeV,量數量:1.0×1014 cm-2 )。B係氫密度為1.3×1017 cm-3 ,而對應於圖4之實施例(能量:8MeV,量數量:2.6×1014 cm-2 )。C係氫密度為5×1015 cm-3 ,而D係氫密度為2.5×1016 cm-3 。然而,圖表中的虛線係顯示半導體基板中之p型載體濃度,而為3.4×1015 cm-3 。   [0033] A的情況,在200℃中,n型載體濃度成為1.0×1015 cm-3 程度,而在330℃程度中,成為與基板之p型載體濃度相同之3.4×1015 cm-3 程度,在400℃中,成為6.0×1015 cm-3 程度。其結果,在經由晶格缺陷之恢復的阻抗率下降成為明顯之250℃~400℃的範圍,p型載體濃度與n型載體濃度則成為相同程度,而可實現基板之中性化的高阻抗率化。其結果,如圖3所示,即使作為加上200℃~400℃之熱處理,亦可維持1kΩ・cm以上之高阻抗。   [0034] B的情況,在200℃中,n型載體濃度成為2.6×1015 cm-3 程度,而在230℃程度中,成為與基板之p型載體濃度相同之3.4×1015 cm-3 程度,在300℃程度中,成為基板之p型載體濃度的2倍之6.8×1015 cm-3 程度,在350℃以上中,成為1.0×1016 cm-3 以上。其結果,如圖4所示,當進行300℃以上之熱處理時,經由基板之n型反轉而阻抗率則下降,而進行400℃之熱處理時,基板之阻抗率則更下降。   [0035] C的情況,氫密度則為A的0.1倍之故,因氫的施體化引起之載體濃度則變少,而即使加上400℃以上之熱處理,亦未達到基板之p型載體濃度(3.4×1015 cm-3 )。其結果,認為即使作為加上200℃~400℃之熱處理,基板的中性化係亦未產生,而僅產生有經由缺陷密度減少之阻抗率的下降。D的情況亦同樣,氫密度則為A的0.5倍,而即使加上200℃~400℃之熱處理,亦未達到基板之p型載體濃度(3.4×1015 cm-3 )之故,認為未產生有基板之中性化,而僅產生有經由缺陷密度減少之阻抗率的下降。   [0036] 圖7係顯示氫密度與經由熱處理之阻抗率變化的關係之一例的圖表,而顯示對定於圖6之條件A,B,C,D之阻抗率變化。如圖示,A(氫密度:5×1016 cm-3 )之情況,在200℃~400℃之範圍中,可維持1kΩ・cm以上之高阻抗者。B(氫密度:1.3×1017 cm-3 )之情況,在200℃~300℃之範圍中,可維持500Ω・cm以上之高阻抗,但在350℃以上中,阻抗率則成為200Ω・cm以下。C(氫密度:5×1015 cm-3 )之情況,在200℃之熱處理中,可維持1kΩ・cm以上之高阻抗,但熱處理當超過200℃時,阻抗率則顯著下降,而在250℃以上之熱處理後中,成為10Ω・cm以下。此係認為原因為氫密度為少之故而為了中性化之n型載體濃度產生不足者。另外,D(氫密度:2.5×1016 cm-3 )之情況,在200℃~230℃之範圍,可維持500Ω・cm以上之高阻抗,但在250℃以上中,阻抗率則成為200Ω・cm以下。   [0037] 從以上的研究,對於即使在熱處理後亦為了維持高阻抗率,係必須在200℃~400℃之溫度範圍,實現與半導體基板12之p型載體濃度相同程度之n型載體濃度。經由200℃~400℃之熱處理的氫之活性化率係2%~10%程度之故,而如實現半導體基板12之p型載體濃度之10倍~50倍程度的氫密度即可。一般而言,低阻抗(1~100Ω・cm)之p型矽基板的p型載體濃度係從為1014 ~1016 cm-3 之情況,如可實現5×1015 cm-3 以上2×10-17 cm-3 以下之氫密度即可。例如,p型載體濃度則如為3.4×1015 cm-3 時,3.4×1016 cm-3 以上1.7×10-17 cm-3 以下之氫密度為佳。   [0038] 然而,高阻抗範圍30之至少一部分的導電型則反轉為n型時,在高阻抗範圍中,加以形成pn接合,有對於形成於半導體基板12之電路元件的動作帶來影響之虞。為了抑制如此之影響,而經由氫的活性化之n型載體濃度則呈不超過半導體基板12之p型載體濃度地,控制氫密度的值亦可。也就是,高阻抗範圍30之導電型則呈成為保持p型地,控制氫密度與熱處理溫度亦可。   [0039] 圖8係顯示氫離子照射之量數量與氫密度之關係的一例之圖表,而對於將氫離子之加速能量作為4MeV,8MeV,17MeV之情況而顯示。如圖示,氫離子之量數量與照射後之氫密度係有比例關係。另外,照射能量越低,所得到之氫密度係越高。此係當加速能量為低時,加以限定注入氫離子之深度方向的範圍,而每單位面積之氫注入量則增加之故。從圖表,對於為了實現5×1015 cm-3 以上2×10-17 cm-3 以下之氫密度,係對於4MeV之場合,如作為1×10-13 cm-2 以上2×10-14 cm-2 以下、而8MeV之情況,如作為1×10-13 cm-2 以上4×10-14 cm-2 以下、17MeV之情況,如作為3.6×10-13 cm-2 以上1×10-15 cm-2 以下即可。然而,如以此等之量數量而進行離子照射時,可得到1×1017 cm-3 以上之缺陷密度之故,而在熱處理前的狀態中,亦可實現500Ω・cm以上之高阻抗率。   [0040] 接著,對於有關本實施形態之半導體裝置10的製造方法加以敘述。圖9係模式性顯示半導體裝置10之製造方法的流程圖。首先,經由種種工程而形成元件於p型之半導體基板12(S10),在於半導體基板12上形成配線層,再形成為了保護所形成之元件或配線之保護膜(S14)。S10~S14之工程係在半導體處理中為稱為「前工程」之工程,而可進行熱氧化,熱擴散,CVD,退火等之400℃以上的高溫處理。接著,照射氫離子於半導體基板12而形成高阻抗範圍30(S16),再進行半導體基板12之背面研磨(S18)。S16及S18之工程係所謂「中間工程」或稱作「後保護處理(PPP; Post Passivation Process)」之工程。   [0041] 接著,進行含有熱處理之後工程(S20),作為半導體積體電路而完成。在S20之後工程中,係例如包含:切割晶圓而進行個片化之工程,將個片化之晶片接著於安裝基板上之接合工程,以導線接合而將安裝基板與晶片結線之工程,以樹脂而封閉晶片之工程等。例如,在晶片黏合工程,導線接合工程及樹脂封閉工程中,進行200℃~300℃程度之熱處理,在某實施例中,熱處理的最高溫度係為260℃程度。然而,進行與接合或封閉工程另外加熱半導體裝置10之退火處理亦可。此退火處理係經由以200℃以上400℃以下之特定溫度而加熱高阻抗範圍30之時,而使高阻抗範圍30之阻抗率安定化亦可。此退火處理係如進行10分鐘以下之比較短時間執行即為充分,而亦可為5分鐘以下,1分鐘以下,或30秒以下的時間。   [0042] 以上,依據實施形態而說明過本發明。本發明係不限定於上述實施形態,而可作種種的設計變更,而由該業者理解可進行種種之變形例之情況,或如此作為之變形例亦包含於本發明之範圍情況。   [0043] 在上述之實施形態中,作成僅照射氫離子而形成高阻抗範圍30者。在變形例中,經由組合氫以外之離子照射之時而形成高阻抗範圍亦可。例如,經由氫離子照射而實現上述之數值範圍的氫密度同時,經由照射氫以外的離子種之時而實現上述之數值的缺陷密度亦可。在某變形例中,經由組合氫離子與氦離子之照射之時,即使加以實施200℃以上之熱處理,亦可形成可維持高阻抗(500Ω・cm以上)之高阻抗範圍。[0011] Hereinafter, aspects of the present invention will be described in detail. However, the constitutions described below are examples and are not intended to limit the scope of the present invention. In addition, in the description of the drawings, the same elements are denoted by the same reference numerals, and overlapping descriptions are suitably omitted. In the following description, the thickness or size of a semiconductor substrate or other layer is a structure for convenience of explanation in each cross-sectional view referred to, and it is not necessarily a display of actual size or ratio. 1 is a cross-sectional view schematically showing a structure of a semiconductor device 10 according to an embodiment. The semiconductor device 10 is an integrated circuit (IC) of a system LSI or a single-chip system. The semiconductor device 10 includes a semiconductor substrate 12 and a wiring layer 18. [0013] The semiconductor substrate 12 is a low-resistance semiconductor substrate having an impedance of 100 Ω ・ cm or less, and a semiconductor substrate having an impedance of approximately 1 to 100 Ω ・ cm. The semiconductor substrate 12 is, for example, a p-type silicon (Si) wafer manufactured by the Chakrasky (CZ) method. The wafers produced by the CZ method are compared with high-impedance wafers produced by the suspension zone melting (FZ) method or the like, and have a low impedance ratio and are inexpensive. In one embodiment, the resistivity of the semiconductor substrate 12 is 4Ω ・ cm, and the p-type carrier concentration is 3.4 × 10 15 cm -3 . [0014] The main surface 14 of the semiconductor substrate 12 is provided with a first element range 22 and a second element range 24. For example, the first element range 22 is provided with a first semiconductor element 26 for a digital circuit, and the second element range 24 is provided with a second semiconductor element 28 for an analog circuit. The first semiconductor element 26 and the second semiconductor element 28 are, for example, a transistor or a diode. Impurity diffusion layers are formed in each of the first element range 22 and the second element range 24 to form a well type range, a source / drain range, a contact range, and the like for forming a semiconductor element. [0015] In this specification, a direction orthogonal to the main surface 14 of the semiconductor substrate 12 is referred to as a vertical direction or a depth direction. In the semiconductor substrate 12, a direction toward the main surface 14 is referred to as an upward direction or an upper side, and a direction toward the back surface 16 opposite to the main surface 14 is referred to as a lower direction or a lower side. It should be noted that a direction parallel to the main surface 14 is referred to as a horizontal direction or a horizontal direction. [0016] The internal system of the semiconductor substrate 12 is provided with a high impedance range 30. The high impedance range 30 is a range in which the resistivity is higher than that of the main body portion of the semiconductor substrate 12. The high impedance range 30 has a resistivity of 100 Ω ・ cm or more, for example, a resistivity of 500 Ω ・ cm or more, and preferably 1 kΩ ・ cm or more. The high-impedance range 30 includes a groove-type high-impedance range 32 and a flat-type high-impedance range 34. [0017] The groove-type high-impedance range 32 is provided in a separation range 20 between the first element range 22 and the second element range 24, and has a depth from the main surface 14 of the semiconductor substrate 12 toward the back surface 16 to a depth. To form. The depth of the groove-type high-impedance range 32 is more than 20 μm, and it is preferably about 50 μm to 200 μm. The groove-type high-impedance range 32 is formed so as to reach a position deeper than the impurity diffusion layer formed in the first element range 22 or the second element range 24. The notch type high impedance range 32 has, for example, a function of blocking the interference from the digital circuit toward the analog circuit and improving the characteristics of the analog circuit. [0018] The planar high-impedance range 34 extends in the second element range 24 and extends in the horizontal direction. The planar high-impedance range 34 is a self-separating range 20, extends across the second element range 24, and extends in the horizontal direction. The high-impedance range 34 may be provided in a continuous high-impedance range continuous with the recessed high-impedance range 32. The planar high impedance range 34 is formed directly below the analog circuit, and contributes to the improvement of the characteristics of the analog circuit. [0019] In the illustrated example, both the grooved high-impedance range 32 and the planar high-impedance range 34 are formed inside the semiconductor substrate 12. However, in the modified example, only the grooved high-impedance range is provided. Either the range 32 or the planar high-impedance range 34 may be used. [0020] The high-impedance range 30 is formed by irradiating hydrogen (H) ions on the main portion of the semiconductor substrate 12 of the low-resistance substrate. When the wafer is subjected to ion irradiation, the ions reach a depth corresponding to the acceleration energy of the ions. At this time, lattice defects are formed in the vicinity of the range including the reach, and the regularity (periodic) of the crystals is in a state of confusion. In such a range where there are many lattice defects, the carrier (electron or hole) becomes easily scattered, which hinders the movement of the carrier. As a result, in a range where local lattice defects are generated by ion irradiation, the resistivity increases compared to before irradiation. [0021] The position or range of the depth direction in which the resistivity increases by ion irradiation can be adjusted by appropriately selecting the acceleration energy or irradiation amount of ion irradiation. For example, a person who adjusts the acceleration energy of ions during ion irradiation can adjust the depth position where a high impedance range is formed. In addition, those accelerating energy by selective ion irradiation can adjust the depth position forming a high impedance range, the range in the depth direction (half width), or the diffusion width in the horizontal direction. Furthermore, a person who performs ion irradiation multiple times while changing acceleration energy can spread in the depth direction to form a thicker high-impedance range. [0022] In this embodiment, hydrogen (H) ions are irradiated with an acceleration energy of 1 MeV or more and 100 MeV or less. For example, monovalent hydrogen ions ( 1 H + ) are irradiated with acceleration energies of 4 MeV, 8 MeV, and 17 MeV. As a device for irradiating an ion beam having such an acceleration energy, a device using a cyclotron method or a van der Graaff method is used. By using such an irradiation condition, in a silicon wafer, ions can be reached from the vicinity of the main surface 14 of the semiconductor substrate 12 to a position having a depth of 100 μm or more. [0023] The resistivity in a high impedance range formed by ion irradiation depends on the density (defect density) of the lattice defects generated. According to the findings of the present inventors, it is understood that if the defect density is 1 × 10 17 cm -3 or more, it is possible to obtain the resistivity of 1 kΩ ・ cm or more optimally. Such a defect density is achieved when the acceleration energy of the irradiated ions is 4 MeV to 17 MeV, and the irradiation amount (quantity) of the hydrogen ions can be realized as 1 × 10 13 cm -2 or more. [0024] Forming a high-impedance range by doing this means that when the heat treatment is added, the resistivity decreases. According to the inventors' opinion, the resistivity decreases when the semiconductor substrate 12 heated by the ion is heated to 200 ° C or higher, and the resistivity is reduced when the semiconductor substrate 12 is heated to 300 ° C or higher than 400 ° C. It is significantly reduced. This is considered to be caused by the heat treatment, the lattice defects are recovered, and the defect density is decreased. Accordingly, in the case where a high impedance range is formed by ion irradiation, it may be better to add a heat treatment at 200 ° C or higher in subsequent processes. [0025] On the other hand, in order to position the high-impedance range 30 at the target separation range 20 or the second element range 24, it is before the wafer is diced, that is, a stage ahead of the process after semiconductor processing. It is necessary to perform ion irradiation. In the post-process, wafer bonding or wire bonding is performed, which is called a heat treatment of resin sealing, and in these processes, the semiconductor substrate 12 can be heated to a temperature of about 200 ° C to 300 ° C. For this reason, the resistivity in the high-impedance range is lowered by the heat treatment in the subsequent process, and the desired resistivity (for example, 500 Ω500cm or more) may not be maintained. [0026] Therefore, in this embodiment, a person who activates hydrogen that is driven into the semiconductor substrate 12 via ion irradiation through heat treatment can also act as a resistivity that maintains a high impedance range even after the heat treatment. When hydrogen is activated by heat treatment, the concentration of the n-type carrier increases through donorization. However, the majority of the carriers of the p-type semiconductor substrate 12 (p-type carriers) are neutralized, and the conductivity decreases. For example, as a result of activation via hydrogen, the semiconductor substrate 12 can be neutralized to increase the resistivity as an n-type carrier concentration that can obtain the same level as the p-type carrier concentration of the semiconductor substrate 12. [0027] FIG. 2 is a graph showing an example of changes in resistivity through helium (He) ion irradiation and heat treatment in a comparative example. In the comparative example, instead of hydrogen ion ( 1 H + ), helium ion ( 3 He 2+ ) was used. The acceleration energy is 23 MeV, the quantity is 1.0 × 10 13 cm -2 , and the irradiation target is a p-type silicon substrate of about 4Ω ・ cm. FIG. 2 shows the resistivity distribution in the depth direction of the substrate before ion irradiation, after ion irradiation (before heat treatment), and after heat treatment (200 ° C, 250 ° C, 300 ° C). As shown in the figure, before the heat treatment, a high impedance range of about 1 to 2 kΩ ・ cm can be formed up to a depth of about 60 μm, and after the heat treatment at 200 ° C., a high impedance range with a similar impedance distribution can be maintained. However, after the heat treatment at 250 ° C, the resistivity in the high-impedance range is less than 1 kΩ 而 cm, and in some cases it is less than 500Ω ・ cm, and after the heat treatment at 300 ° C, the resistivity in the high-resistance range becomes insufficient. 100Ω ・ cm. In the case of ion irradiation using helium in this way, it is understood that the resistivity in the high-impedance range decreases through a heat treatment in excess of 200 ° C, and the resistivity significantly decreases in a heat treatment above 300 ° C. [0028] FIG. 3 is a graph showing an example of changes in resistivity through hydrogen (H) ion irradiation and heat treatment according to the embodiment. This embodiment is irradiated with hydrogen ions ( 1 H + ), the acceleration energy is 8 MeV, the quantity is 1.0 × 10 14 cm -2 , and the irradiation target is a p-type silicon substrate of about 4Ω ・ cm. Fig. 3 shows the resistivity distribution in the depth direction of the substrate before ion irradiation, after ion irradiation (before heat treatment), and after heat treatment (250 ° C, 400 ° C). As shown in the figure, before the heat treatment, a high impedance range of 1 kΩ ・ cm or more can be formed up to a depth of about 110 μm, and after the heat treatment at 250 ° C., the high impedance range with the same impedance ratio distribution can be maintained. In addition, after a heat treatment at 400 ° C, a high impedance range of 1 kΩ ・ cm or more can be maintained in a depth of 10 μm to 80 μm. In this way, a person using hydrogen ions can maintain a high impedance range of 500 Ω ・ cm or more, ideally 1 kΩ ・ cm or more, even when a heat treatment exceeding 200 ° C or a heat treatment over 300 ° C is added. [0029] FIG. 4 is a graph showing an example of a change in resistivity through hydrogen (H) ion irradiation and heat treatment according to another embodiment. In this embodiment, the hydrogen ion ( 1 H + ) is irradiated in the same manner as in FIG. 3, the acceleration energy is 8 MeV, and the irradiation target is a p-type silicon substrate of about 4Ω ・ cm. This embodiment uses a quantity different from that in FIG. 3, and is a high quantity of 2.6 × 10 -14 cm −2 as compared with the above-mentioned embodiment. FIG. 4 shows the resistivity distribution in the depth direction of the substrate before ion irradiation, after ion irradiation (before heat treatment), and after heat treatment (200 ° C, 300 ° C, 400 ° C). As shown in the figure, before the heat treatment, a high impedance range of 1 kΩ ・ cm or more can be formed to a depth of about 45 μm, and after the heat treatment at 200 ° C., the high impedance range with a similar impedance ratio distribution can be maintained. However, after a heat treatment at 300 ° C, the resistivity at a depth of about 10 to 30 μm becomes less than 1 kΩ ・ cm, and after a heat treatment at 400 ° C, the middle resistance becomes less than 100 Ω ・ cm. This is considered to be due to the fact that when the amount of hydrogen ions is increased, hydrogen is donated excessively, the conductivity type is reversed from p-type to n-type, and resistance is increased by the increase in the concentration of the n-type carrier that becomes the majority carrier. The rate is down. [0030] From the above comparative examples and examples, in order to maintain a high resistivity (500 Ω ・ cm or more) after the heat treatment exceeding 200 ° C, it can be said that the amount of hydrogen ions and the heat treatment must be appropriately controlled. Temperature person. [0031] FIG. 5 is a graph showing the activation rate of hydrogen through heat treatment, and shows the relationship between temperature and activation rate. As shown in the figure, the activation rate of hydrogen in the range of 200 ° C to 400 ° C is low, and the increase of the activation rate by temperature rise is also slow. On the other hand, when it exceeds 400 ° C., the increase rate of the activation rate by temperature rise becomes large, and the value of the activation rate also exceeds 10%. Accordingly, by using a heat treatment in which the increase in the activation rate through a temperature rise is gradually in the range of 200 ° C to 400 ° C, even if there is an individual difference in the temperature of the heat treatment of the subsequent process, the heat treatment can be suppressed. Significant change in resistivity at different temperatures. [0032] FIG. 6 is a graph schematically showing a change in the carrier concentration through heat treatment, and for three different hydrogen densities, it schematically shows the value of the n-type carrier concentration that is donorized through heat treatment. The A-series hydrogen density is 5 × 10 16 cm -3 , and corresponds to the embodiment of FIG. 3 (energy: 8 MeV, quantity: 1.0 × 10 14 cm -2 ). The B-system hydrogen density is 1.3 × 10 17 cm -3 , and corresponds to the embodiment of FIG. 4 (energy: 8 MeV, quantity: 2.6 × 10 14 cm -2 ). The C-system hydrogen density is 5 × 10 15 cm -3 , and the D-system hydrogen density is 2.5 × 10 16 cm -3 . However, the dotted line in the graph shows the p-type carrier concentration in the semiconductor substrate, and it is 3.4 × 10 15 cm -3 . [0033] In the case of A, at 200 ° C, the n-type carrier concentration becomes about 1.0 × 10 15 cm -3 , and at 330 ° C, it becomes 3.4 × 10 15 cm -3 the same as the p-type carrier concentration of the substrate. The degree was about 6.0 × 10 15 cm -3 at 400 ° C. As a result, in the range of 250 ° C to 400 ° C, where the resistivity reduction through the recovery of the lattice defect becomes noticeable, the p-type carrier concentration and the n-type carrier concentration become the same, and the substrate can be neutralized with high impedance. Rate. As a result, as shown in FIG. 3, even if heat treatment is performed at 200 ° C. to 400 ° C., a high impedance of 1 kΩ ・ cm or more can be maintained. [0034] In the case of B, at 200 ° C, the n-type carrier concentration becomes about 2.6 × 10 15 cm -3 , and at 230 ° C, it becomes 3.4 × 10 15 cm -3 which is the same as the p-type carrier concentration of the substrate. The degree is about 6.8 × 10 15 cm −3 which is twice the concentration of the p-type carrier of the substrate at about 300 ° C., and about 1.0 × 10 16 cm −3 or more at 350 ° C. or higher. As a result, as shown in FIG. 4, when the heat treatment is performed at a temperature higher than 300 ° C., the resistivity decreases through the n-type inversion of the substrate, and when the heat treatment is performed at 400 ° C., the resistivity decreases further. [0035] In the case of C, the hydrogen density is 0.1 times that of A. The carrier concentration due to the donorization of hydrogen is reduced, and the p-type carrier of the substrate is not reached even if a heat treatment above 400 ° C is added. Concentration (3.4 × 10 15 cm -3 ). As a result, it is considered that the neutralization system of the substrate is not generated even if the heat treatment is added at 200 ° C. to 400 ° C., and only the decrease in the resistivity through the decrease in the defect density is considered. The same is true for D. The hydrogen density is 0.5 times that of A. Even if the heat treatment at 200 ° C to 400 ° C is added, the p-type carrier concentration (3.4 × 10 15 cm -3 ) of the substrate is not reached. Neutralization of the substrate occurs, and only a decrease in resistivity through reduction in defect density occurs. [0036] FIG. 7 is a graph showing an example of the relationship between the hydrogen density and the change in resistivity through heat treatment, and shows the change in resistivity for conditions A, B, C, and D specified in FIG. 6. As shown in the figure, in the case of A (hydrogen density: 5 × 10 16 cm -3 ), a high impedance of 1 kΩ ・ cm or higher can be maintained in the range of 200 ° C to 400 ° C. In the case of B (hydrogen density: 1.3 × 10 17 cm -3 ), a high impedance of 500 Ω ・ cm or higher can be maintained in a range of 200 ° C to 300 ° C, but the resistivity becomes 200 Ω ・ cm at 350 ° C or higher. the following. In the case of C (hydrogen density: 5 × 10 15 cm -3 ), a high resistance of 1 kΩ ℃ cm or higher can be maintained in a 200 ° C heat treatment, but when the heat treatment exceeds 200 ° C, the resistivity decreases significantly, and at 250 ° C After heat treatment at a temperature higher than or equal to 10 ° C, the temperature becomes 10 Ω ・ cm or less. This is considered to be because the hydrogen density is low and the concentration of the n-type carrier is insufficient for neutralization. In the case of D (hydrogen density: 2.5 × 10 16 cm -3 ), a high impedance of 500 Ω ・ cm or higher can be maintained in a range of 200 ° C to 230 ° C, but the resistivity becomes 200 Ω at 250 ° C or higher. cm or less. [0037] From the above research, in order to maintain a high resistivity even after the heat treatment, it is necessary to achieve an n-type carrier concentration in the temperature range of 200 ° C. to 400 ° C. to the same degree as the p-type carrier concentration of the semiconductor substrate 12. The activation rate of hydrogen through the heat treatment at 200 ° C to 400 ° C is about 2% to 10%, and the hydrogen density of the semiconductor substrate 12 may be about 10 to 50 times the p-type carrier concentration. Generally speaking, the p-type carrier concentration of a low-resistance (1 ~ 100Ω ・ cm) p-type silicon substrate is from 10 14 to 10 16 cm -3 . For example, 5 × 10 15 cm -3 or more 2 × A hydrogen density of 10 -17 cm -3 or less is sufficient. For example, when the p-type carrier concentration is 3.4 × 10 15 cm -3 , a hydrogen density of 3.4 × 10 16 cm -3 or more and 1.7 × 10 -17 cm -3 or less is preferred. [0038] However, when the conductivity type of at least a part of the high-impedance range 30 is inverted to an n-type, the formation of a pn junction in the high-impedance range has an effect on the operation of circuit elements formed on the semiconductor substrate 12. Yu. In order to suppress such an influence, the concentration of the n-type carrier through the activation of hydrogen does not exceed the concentration of the p-type carrier of the semiconductor substrate 12, and the value of the hydrogen density may be controlled. That is, the conductive type in the high impedance range 30 is a p-type ground, and the hydrogen density and the heat treatment temperature can be controlled. [0039] FIG. 8 is a graph showing an example of the relationship between the amount of hydrogen ion irradiation and the hydrogen density. The acceleration energy of hydrogen ions is shown as 4MeV, 8MeV, and 17MeV. As shown, the amount of hydrogen ions is proportional to the hydrogen density after irradiation. In addition, the lower the irradiation energy, the higher the hydrogen density obtained. This is because when the acceleration energy is low, the depth range of the hydrogen ion implantation is limited, and the hydrogen injection amount per unit area is increased. From the chart, for the purpose of achieving a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 -17 cm -3 or less, for 4MeV, such as 1 × 10 -13 cm -2 or more 2 × 10 -14 cm -2 or less and 8 MeV, such as 1 × 10 -13 cm -2 or more 4 × 10 -14 cm -2 or less, 17 MeV, such as 3.6 × 10 -13 cm -2 or more 1 × 10 -15 cm -2 or less is sufficient. However, if ion irradiation is performed in such an amount, a defect density of 1 × 10 17 cm -3 or more can be obtained, and a high resistivity of 500Ω ・ cm or more can be achieved in a state before heat treatment. . [0040] Next, a method for manufacturing the semiconductor device 10 according to this embodiment will be described. FIG. 9 is a flowchart schematically showing a manufacturing method of the semiconductor device 10. First, elements are formed on the p-type semiconductor substrate 12 through various processes (S10), a wiring layer is formed on the semiconductor substrate 12, and a protective film (S14) is formed to protect the formed elements or wiring. The process of S10 ~ S14 is a process called "pre-engineering" in semiconductor processing, and it can perform high temperature processing above 400 ° C such as thermal oxidation, thermal diffusion, CVD, and annealing. Next, the semiconductor substrate 12 is irradiated with hydrogen ions to form a high impedance range 30 (S16), and then the back surface of the semiconductor substrate 12 is polished (S18). The projects of S16 and S18 are the so-called "intermediate projects" or "PPP (Post Passivation Process)" projects. [0041] Next, a process including heat treatment (S20) is performed to complete the semiconductor integrated circuit. The processes after S20 include, for example, a process of dicing a wafer and singulating the wafer, a process of bonding the singulated wafer to a mounting substrate, and a process of bonding the mounting substrate to the wafer by wire bonding. Resin and wafer sealing process. For example, in a wafer bonding process, a wire bonding process, and a resin sealing process, a heat treatment of about 200 ° C. to 300 ° C. is performed. In an embodiment, the maximum temperature of the heat treatment is about 260 ° C. However, an annealing process may be performed in which the semiconductor device 10 is additionally heated by bonding and sealing. In this annealing treatment, when the high impedance range 30 is heated at a specific temperature of 200 ° C. to 400 ° C., the resistivity of the high impedance range 30 may be stabilized. This annealing treatment is sufficient if it is performed for a relatively short time of 10 minutes or less, but it may also be 5 minutes or less, 1 minute or less, or 30 seconds or less. [0042] The present invention has been described based on the embodiments. The present invention is not limited to the above-mentioned embodiments, but various design changes can be made. It is understood by those skilled in the art that various modifications can be made, or such modifications are also included in the scope of the present invention. [0043] In the above-mentioned embodiment, those having a high impedance range of 30 are formed by irradiating only hydrogen ions. In the modification, a high impedance range may be formed when irradiated with ions other than hydrogen. For example, the hydrogen density in the above-mentioned numerical range may be achieved by irradiation with hydrogen ions, and the defect density may be achieved in the above-mentioned numerical range by irradiation with ion species other than hydrogen. In a modification, when combined with hydrogen ion and helium ion irradiation, a high impedance range capable of maintaining high impedance (500 Ω 阻抗 cm or more) can be formed even if heat treatment is performed at 200 ° C or higher.

[0044][0044]

10‧‧‧半導體裝置10‧‧‧Semiconductor device

12‧‧‧半導體基板12‧‧‧ semiconductor substrate

14‧‧‧主面14‧‧‧ main face

16‧‧‧背面16‧‧‧ back

18‧‧‧配線層18‧‧‧ wiring layer

20‧‧‧分離範圍20‧‧‧ separation range

22‧‧‧第1元件範圍22‧‧‧The first component range

24‧‧‧第2元件範圍24‧‧‧ 2nd component range

26‧‧‧第1半導體元件26‧‧‧The first semiconductor element

28‧‧‧第2半導體元件28‧‧‧Second semiconductor element

30‧‧‧高阻抗範圍30‧‧‧High impedance range

32‧‧‧凹槽型高阻抗範圍32‧‧‧ Notch type high impedance range

34‧‧‧平面型高阻抗範圍34‧‧‧Planar high impedance range

[0010]   圖1係模式性地顯示有關實施形態的半導體裝置之構造的剖面圖。   圖2係顯示經由有關比較例之氦(He)離子照射及熱處理之阻抗率變化之一例的圖表。   圖3係顯示經由有關實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。   圖4係顯示經由有關另外實施例之氫(H)離子照射及熱處理之阻抗率變化之一例的圖表。   圖5係顯示經由熱處理之氫的活性化率的圖表。   圖6係模式性地顯示經由熱處理之載體濃度變化的圖表。   圖7係顯示氫密度與經由熱處理之阻抗率變化的關係之一例的圖表。   圖8係顯示氫離子照射之量數量與氫密度之關係的一例之圖表。   圖9係模式性顯示半導體裝置之製造方法的流程圖。1 is a cross-sectional view schematically showing a structure of a semiconductor device according to an embodiment. FIG. 2 is a graph showing an example of a change in resistivity through helium (He) ion irradiation and heat treatment in a comparative example. FIG. 3 is a graph showing an example of changes in resistivity through hydrogen (H) ion irradiation and heat treatment in the examples. FIG. 4 is a graph showing an example of changes in resistivity by irradiation with hydrogen (H) ions and heat treatment in another example. FIG. 5 is a graph showing the activation rate of hydrogen through heat treatment. FIG. 6 is a graph schematically showing a change in the concentration of a carrier through heat treatment. FIG. 7 is a graph showing an example of the relationship between the hydrogen density and the change in resistivity through heat treatment. FIG. 8 is a graph showing an example of the relationship between the amount of hydrogen ion irradiation and the hydrogen density. FIG. 9 is a flowchart schematically showing a method of manufacturing a semiconductor device.

Claims (7)

一種半導體裝置之製造方法,其特徵為具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為5×1015cm-3以上2×1017cm-3以下之範圍,形成阻抗率則較離子照射前之前述p型半導體基板為高之高阻抗範圍,和以200℃以上400℃以下之溫度而加熱形成有前述高阻抗範圍之p型半導體基板;前述離子照射前之p型半導體基板之阻抗率係100Ωcm以下,而前述加熱後之前述高阻抗範圍的阻抗率係500Ωcm以上。A method for manufacturing a semiconductor device, comprising: irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less In the range, the formation resistivity is higher than that of the aforementioned p-type semiconductor substrate before ion irradiation, and the p-type semiconductor substrate having the aforementioned high resistance range is formed by heating at a temperature of 200 ° C to 400 ° C; The resistivity of the p-type semiconductor substrate before irradiation is 100 Ωcm or less, and the resistivity of the aforementioned high impedance range after the heating is 500 Ωcm or more. 一種半導體裝置之製造方法,其特徵為具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為5×1015cm-3以上2×1017cm-3以下之範圍,形成阻抗率則較離子照射前之前述p型半導體基板為高之高阻抗範圍,和以200℃以上400℃以下之溫度而加熱形成有前述高阻抗範圍之p型半導體基板;前述高阻抗範圍係缺陷密度成為1×1017cm-3以上地加以形成者。A method for manufacturing a semiconductor device, comprising: irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and a hydrogen density of 5 × 10 1 5cm -3 or more and 2 × 10 17 cm -3 or less The range of formation impedance is higher than that of the aforementioned p-type semiconductor substrate before ion irradiation, and the p-type semiconductor substrate having the aforementioned high impedance range is formed by heating at a temperature of 200 ° C to 400 ° C; The impedance range is formed by a defect density of 1 × 10 17 cm -3 or more. 如申請專利範圍第1項或第2項記載之半導體裝置之製造方法,其中,形成有前述高阻抗範圍之p型半導體基板係以200℃以上300℃以下之溫度而加以加熱者。For example, the method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, wherein the p-type semiconductor substrate having the aforementioned high impedance range is heated at a temperature of 200 ° C to 300 ° C. 一種半導體裝置之製造方法,其特徵為具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為5×1015cm-3以上2×1017cm-3以下之範圍,形成阻抗率則較離子照射前之前述p型半導體基板為高之高阻抗範圍,和以200℃以上400℃以下之溫度而加熱形成有前述高阻抗範圍之p型半導體基板;前述高阻抗範圍係經由照射能量為4MeV以上17MeV以下、量數量為2×1013cm-2以上2×1014cm-2以下之氫離子照射而加以形成者。A method for manufacturing a semiconductor device, comprising: irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less The range of formation impedance is higher than that of the aforementioned p-type semiconductor substrate before ion irradiation, and the p-type semiconductor substrate with the aforementioned high-resistance range is formed by heating at a temperature of 200 ° C to 400 ° C; The impedance range is formed by irradiation of hydrogen ions with an irradiation energy of 4 MeV or more and 17 MeV or less, and a quantity of 2 × 10 13 cm -2 or more and 2 × 10 14 cm -2 or less. 如申請專利範圍第1項或第4項記載之半導體裝置之製造方法,其中,前述加熱的時間係10分鐘以下者。For example, the method for manufacturing a semiconductor device according to item 1 or item 4 of the scope of patent application, wherein the heating time is 10 minutes or less. 一種半導體裝置之製造方法,其特徵為具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為5×1015cm-3以上2×1017cm-3以下之範圍,形成阻抗率則較離子照射前之前述p型半導體基板為高之高阻抗範圍,和以200℃以上400℃以下之溫度而加熱形成有前述高阻抗範圍之p型半導體基板;前述高阻抗範圍係氫密度成為前述離子照射前之p型半導體基板的載體濃度之10倍以上50倍以下的值地加以形成者。A method for manufacturing a semiconductor device, comprising: irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less The range of formation impedance is higher than that of the aforementioned p-type semiconductor substrate before ion irradiation, and the p-type semiconductor substrate with the aforementioned high-resistance range is formed by heating at a temperature of 200 ° C to 400 ° C; The impedance range is a value obtained by forming the hydrogen density at a value that is 10 times or more and 50 times or less the carrier concentration of the p-type semiconductor substrate before the ion irradiation. 一種半導體裝置之製造方法,其特徵為具備:於形成有半導體元件之p型半導體基板照射氫(H)離子,而氫密度則成為5×1015cm-3以上2×1017cm-3以下之範圍,形成阻抗率則較離子照射前之前述p型半導體基板為高之高阻抗範圍,和以200℃以上400℃以下之溫度而加熱形成有前述高阻抗範圍之p型半導體基板;前述高阻抗範圍係前述加熱後之導電型為p型者。A method for manufacturing a semiconductor device, comprising: irradiating hydrogen (H) ions on a p-type semiconductor substrate on which a semiconductor element is formed, and a hydrogen density of 5 × 10 15 cm -3 or more and 2 × 10 17 cm -3 or less The range of formation impedance is higher than that of the aforementioned p-type semiconductor substrate before ion irradiation, and the p-type semiconductor substrate with the aforementioned high-resistance range is formed by heating at a temperature of 200 ° C to 400 ° C; The impedance range is the p-type conductivity type after heating.
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