TWI555061B - Semiconductor device manufacturing method and semiconductor device - Google Patents
Semiconductor device manufacturing method and semiconductor device Download PDFInfo
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- TWI555061B TWI555061B TW102111878A TW102111878A TWI555061B TW I555061 B TWI555061 B TW I555061B TW 102111878 A TW102111878 A TW 102111878A TW 102111878 A TW102111878 A TW 102111878A TW I555061 B TWI555061 B TW I555061B
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- 239000004065 semiconductor Substances 0.000 title claims description 114
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 239000000758 substrate Substances 0.000 claims description 115
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- 230000001133 acceleration Effects 0.000 description 13
- 230000001965 increasing effect Effects 0.000 description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 229910052732 germanium Inorganic materials 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
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- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
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- 229910052707 ruthenium Inorganic materials 0.000 description 3
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- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 230000032258 transport Effects 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 229910052786 argon Inorganic materials 0.000 description 1
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- 238000011068 loading method Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
- H01J37/3171—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation for ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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- Semiconductor Integrated Circuits (AREA)
Description
本發明係有關一種半導體裝置的製造方法及半導體裝置。 The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.
習知，藉由對矽晶圓等基板實施各種微細加工來製造半導體積體電路。該種基板所要求之性能根據用途或製造製程而多種多樣。例如，作為屏蔽從數位電路經由基板向類比電路傳達之噪聲之手段，或者作為提高晶片上電感器的Q值之手段，使用高電阻基板(例如參閱專利文獻1。)。作為高電阻基板，例如使用SOI(Silicon On Insulator：矽絕緣體)基板，或藉由雜質較少的FZ(Floating Zone：浮區)法製造出之基板。 Conventionally, a semiconductor integrated circuit is manufactured by performing various microfabrication on a substrate such as a germanium wafer. The properties required for such substrates vary depending on the application or manufacturing process. For example, a high-resistance substrate is used as a means for shielding noise transmitted from the digital circuit to the analog circuit via the substrate, or as a means for increasing the Q value of the inductor on the wafer (see, for example, Patent Document 1). As the high-resistance substrate, for example, an SOI (Silicon On Insulator) substrate or a substrate manufactured by FZ (Floating Zone) method with less impurities is used.
專利文獻1：日本特開2005-93828號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-93828
然而，SOI基板或藉由FZ法製造出之高電阻基板的價格較高，導致半導體裝置的製造成本上升。並且，即使採用電阻率較高的基板，有時亦會因在電晶體或二極體等元件製造過程中被注入之雜質在之後的熱處理過程中擴散而降低基板的電阻率。其結果，即使使用將電阻率調整為較高之高價基板，亦有在半導體裝置的製造過程中電阻率發生變化而無法獲得作為原本目標之電阻率之情況。 However, the price of the SOI substrate or the high-resistance substrate manufactured by the FZ method is high, resulting in an increase in the manufacturing cost of the semiconductor device. Further, even if a substrate having a high resistivity is used, the resistivity of the substrate may be lowered by diffusion of impurities implanted in the manufacturing process of a device such as a transistor or a diode during the subsequent heat treatment. As a result, even if a high-priced substrate having a high resistivity is used, there is a case where the resistivity changes during the manufacturing process of the semiconductor device, and the original resistivity cannot be obtained.
本發明的一態樣的例示性的目的之一為提供一種實現確保了所希望的電阻率之半導體裝置之技術。 One of the illustrative purposes of one aspect of the present invention is to provide a technique for implementing a semiconductor device that ensures a desired resistivity.
並且，本發明的其他態樣的例示性的目的之一為提供一種實現具有高電阻層之半導體裝置之技術。 Moreover, one of the exemplary objects of other aspects of the present invention is to provide a technique for realizing a semiconductor device having a high resistance layer.
為了解決上述課題，本發明的一態樣的半導體裝置的製造方法具有高電阻層形成製程，在該高電阻層形成製程中，對經過了電阻率可能產生變化之製程之半導體基板的預定區域進行離子照射，並在該預定區域形成電阻率高於周圍的高電阻層。 In order to solve the above problems, a method of manufacturing a semiconductor device according to an aspect of the present invention has a high resistance layer forming process in which a predetermined region of a semiconductor substrate subjected to a process in which a resistivity may vary is performed in the high resistance layer forming process. The ions are irradiated, and a high-resistance layer having a higher resistivity than the surrounding is formed in the predetermined region.
依本發明的其他態樣，提供一種半導體裝置的製造方法，其具備在半導體基板的主面或其相反側的背面準備遮罩之製程，前述半導體基板在前述主面具備元件區域，在前述主面與前述背面之間具備非元件部份，本方法還具備從前述遮罩側向前述遮罩及前述半導體基板進行離子照射，以在前述非元件部份形成電阻率高於前述元件區域的 高電阻層之製程。 According to another aspect of the present invention, a method of manufacturing a semiconductor device including a process of preparing a mask on a back surface of a main surface of a semiconductor substrate or an opposite side thereof, wherein the semiconductor substrate includes an element region on the main surface, Providing a non-element portion between the surface and the back surface, the method further includes performing ion irradiation on the mask and the semiconductor substrate from the mask side to form a resistivity higher than the element region in the non-element portion. Process of high resistance layer.
依本發明的其他態樣，提供如下半導體裝置的製造方法，其具備：在低電阻半導體基板的背面形成遮罩圖案之製程；從遮罩圖案側向前述遮罩圖案及前述半導體基板進行離子照射，以在前述半導體基板的內部形成高電阻層之製程；及從前述背面去除前述遮罩圖案之製程。 According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a process of forming a mask pattern on a back surface of a low-resistance semiconductor substrate; and ion-illuminating the mask pattern and the semiconductor substrate from a mask pattern side a process of forming a high-resistance layer inside the semiconductor substrate; and a process of removing the mask pattern from the back surface.
依本發明的其他態樣，提供有如下半導體裝置，其特徵為，具備：具備元件區域之主面；前述主面的相反側的背面；及存在於前述主面與前述背面之間之非元件部份，前述非元件部份具備電阻率高於前述元件區域的第1晶格缺陷層及第2晶格缺陷層，前述第1晶格缺陷層在第1區域中形成在第1深度，前述第2晶格缺陷層在與前述第1區域不同之第2區域中形成在與前述第1深度不同之第2深度。 According to another aspect of the present invention, there is provided a semiconductor device comprising: a main surface including an element region; a back surface opposite to the main surface; and a non-element existing between the main surface and the back surface The first non-element portion includes a first lattice defect layer and a second lattice defect layer having a higher resistivity than the element region, and the first lattice defect layer is formed at a first depth in the first region, and the The second lattice defect layer is formed at a second depth different from the first depth in the second region different from the first region.
另外，將以上構成要件的任意組合或本發明的構成要件或表現，在方法、裝置、系統等之間進行相互替換者，作為本發明的態樣亦有效。 Further, any combination of the above constituent elements or constituent elements or expressions of the present invention, which are mutually substituted between methods, apparatuses, systems, etc., is also effective as an aspect of the present invention.
依本發明的一態樣，能夠製造確保了所希望的電阻率之半導體裝置。並且，依本發明的其他態樣，提供具有高電阻層之半導體裝置。 According to an aspect of the present invention, a semiconductor device in which a desired resistivity is secured can be manufactured. Further, according to other aspects of the present invention, a semiconductor device having a high resistance layer is provided.
10‧‧‧離子照射系統 10‧‧‧Ion Irradiation System
12‧‧‧加速器 12‧‧‧Accelerator
14‧‧‧晶圓傳送裝置 14‧‧‧ wafer transfer device
16‧‧‧射束傳輸導管 16‧‧‧beam transmission catheter
18‧‧‧傳送板 18‧‧‧Transport board
20‧‧‧照射腔室 20‧‧‧ illumination chamber
22‧‧‧移動機構 22‧‧‧Mobile agencies
24‧‧‧晶圓 24‧‧‧ wafer
26‧‧‧搭載部 26‧‧‧Loading Department
34‧‧‧高電阻層 34‧‧‧High resistance layer
36‧‧‧阻尼器 36‧‧‧damper
38‧‧‧半導體裝置 38‧‧‧ semiconductor devices
50‧‧‧高電阻層 50‧‧‧High resistance layer
51‧‧‧半導體裝置 51‧‧‧Semiconductor device
52‧‧‧數位電路 52‧‧‧Digital Circuit
54‧‧‧類比電路 54‧‧‧ analog circuit
56、58‧‧‧高電阻層 56, 58‧‧‧ high resistance layer
100‧‧‧半導體裝置 100‧‧‧Semiconductor device
200‧‧‧半導體基板 200‧‧‧Semiconductor substrate
202‧‧‧主面 202‧‧‧Main face
204‧‧‧背面 204‧‧‧Back
206‧‧‧元件區域 206‧‧‧Component area
212‧‧‧遮罩 212‧‧‧ mask
214‧‧‧開口部 214‧‧‧ openings
216‧‧‧遮罩圖案 216‧‧‧ mask pattern
222‧‧‧高電阻層 222‧‧‧High resistance layer
224‧‧‧離子束 224‧‧‧Ion Beam
226‧‧‧第1高電阻層 226‧‧‧1st high resistance layer
228‧‧‧第2高電阻層 228‧‧‧2nd high resistance layer
第1圖係模式表示離子照射系統的概略結構之圖。 Fig. 1 is a view showing a schematic configuration of an ion irradiation system.
第2圖係表示傳送板的一例之圖。 Fig. 2 is a view showing an example of a transfer plate.
第3圖係模式表示離子束的照射圖像之圖。 Fig. 3 is a view showing an image of an irradiation of an ion beam.
第4圖係模式表示形成有高電阻層之晶圓的剖面圖之圖。 Fig. 4 is a view showing a cross-sectional view of a wafer in which a high resistance layer is formed.
第5圖係表示自離子照射後的矽晶圓的表面的深度與電阻率的關係的一例之曲線圖。 Fig. 5 is a graph showing an example of the relationship between the depth of the surface of the tantalum wafer after ion irradiation and the specific resistance.
第6圖(a)係表示電阻率峰值的深度不同之3個高電阻層的曲線圖之圖，第6圖(b)係表示半值幅不同之3個高電阻層的曲線圖之圖。 Fig. 6(a) is a graph showing a graph of three high-resistance layers having different depths of the resistivity peak, and Fig. 6(b) is a graph showing graphs of three high-resistance layers having different half-value widths.
第7圖係表示本實施形態之半導體裝置的製造方法的一例之流程圖。 Fig. 7 is a flow chart showing an example of a method of manufacturing the semiconductor device of the embodiment.
第8圖(a)係表示習知之半導體裝置的一例之剖面圖，第8圖(b)係表示本實施形態之半導體裝置的一例之剖面圖。 Fig. 8(a) is a cross-sectional view showing an example of a conventional semiconductor device, and Fig. 8(b) is a cross-sectional view showing an example of the semiconductor device of the embodiment.
第9圖(a)係表示半導體裝置的其他一例之俯視圖，第9圖(b)係第9圖(a)所示之半導體裝置的A-A剖面圖。 Fig. 9(a) is a plan view showing another example of the semiconductor device, and Fig. 9(b) is a cross-sectional view taken along line A-A of the semiconductor device shown in Fig. 9(a).
第10圖(a)至第10圖(d)表示本發明的一實施形態之半導體裝置的製造方法的一例。 10(a) to 10(d) show an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
第11圖(a)表示本發明的一實施形態之半導體裝置的製造方法的其他一例，第11圖(b)表示本發明的一實施形態之半導體裝置的製造方法的另一其他一例。 Fig. 11(a) shows another example of the method of manufacturing the semiconductor device according to the embodiment of the present invention, and Fig. 11(b) shows still another example of the method of manufacturing the semiconductor device according to the embodiment of the present invention.
第12圖(a)係例示在本發明的一實施形態之高電阻 層形成製程中所使用之遮罩之俯視圖，第12圖(b)係第12圖(a)所示之遮罩的B-B剖面圖。 Fig. 12(a) is a view showing a high resistance in an embodiment of the present invention. A plan view of the mask used in the layer forming process, and Fig. 12(b) is a B-B cross-sectional view of the mask shown in Fig. 12(a).
第13圖(a)係例示在本發明的一實施形態之高電阻層形成製程中所使用之遮罩之俯視圖，第13圖(b)係第13圖(a)所示之遮罩的C-C剖面圖。 Fig. 13(a) is a plan view showing a mask used in a high resistance layer forming process according to an embodiment of the present invention, and Fig. 13(b) is a CC of the mask shown in Fig. 13(a). Sectional view.
第14圖(a)係例示在本發明的一實施形態之高電阻層形成製程中所使用之遮罩之俯視圖，第14圖(b)係第14圖(a)所示之遮罩的D-D剖面圖。 Fig. 14(a) is a plan view showing a mask used in a high resistance layer forming process according to an embodiment of the present invention, and Fig. 14(b) is a DD of the mask shown in Fig. 14(a). Sectional view.
第15圖係用於說明本發明的一實施形態之離子照射製程之圖。 Fig. 15 is a view for explaining an ion irradiation process according to an embodiment of the present invention.
第16圖係用於說明本發明的一實施形態之離子照射製程之圖。 Fig. 16 is a view for explaining an ion irradiation process according to an embodiment of the present invention.
第17圖係表示本發明的一實施形態之遮罩之圖。 Fig. 17 is a view showing a mask according to an embodiment of the present invention.
本發明形態之半導體裝置的製造方法具有高電阻層形成製程，在該高電阻層形成製程中，對經過了電阻率可能產生變化之製程之半導體基板的預定區域進行離子照射，並在該預定區域形成電阻高於周圍的高電阻層。 The method for fabricating a semiconductor device according to the aspect of the invention has a high-resistance layer forming process in which ion irradiation is performed on a predetermined region of a semiconductor substrate subjected to a process in which a resistivity may vary, and in the predetermined region A high resistance layer having a higher resistance than the surrounding is formed.
其中，電阻率可能產生變化之製程例如可舉出在形成二極體或電晶體等元件或形成配線(電路)時進行之各種熱處理。作為熱處理，例如可舉出熱氧化、熱擴散、CVD、退火等。藉由該些熱處理，有時基板成為400℃以上。經過了該些處理之半導體基板，即使在那之前係電阻 率較高者，亦由於雜質的擴散等而局部或整體的電阻率往往下降。因此，很難將所希望的較高的電阻率維持至製造製程的最後，並且還難以精確度良好地確保預定區域的電阻率。 Among them, a process in which the resistivity may vary may be, for example, various heat treatments performed when a device such as a diode or a transistor is formed or a wiring (circuit) is formed. Examples of the heat treatment include thermal oxidation, thermal diffusion, CVD, annealing, and the like. Due to these heat treatments, the substrate may be at least 400 °C. The semiconductor substrate that has undergone the treatment, even before that The higher the rate, the local or overall resistivity tends to decrease due to the diffusion of impurities and the like. Therefore, it is difficult to maintain the desired higher resistivity to the end of the manufacturing process, and it is also difficult to accurately ensure the resistivity of the predetermined region.
然而，本實施形態之製造方法在半導體基板的電阻率可能產生變化之製程之後，藉由離子照射在預定區域形成高電阻層。因此，即使電阻率藉由高電阻層形成製程之前的處理而發生變化，亦能夠在預定區域精確度良好地形成高電阻層。亦即，能夠比較輕鬆地製造確保了所希望的電阻率之半導體裝置。 However, in the manufacturing method of the present embodiment, after the process in which the resistivity of the semiconductor substrate is likely to change, a high-resistance layer is formed in a predetermined region by ion irradiation. Therefore, even if the resistivity is changed by the process before the high resistance layer forming process, the high resistance layer can be formed accurately in a predetermined region. That is, it is possible to relatively easily manufacture a semiconductor device that secures a desired resistivity.
以下，對用於實施本發明之形態進行詳細說明。另外，以下敘述之結構為例示，並非對本發明的範圍進行任何限定者。並且，在附圖說明中對相同要件附加相同元件符號，適當省略重複說明。並且，在說明製造方法時所示之各剖面圖中，半導體基板或其他層的厚度或大小係方便說明者，並非一定表示實際的尺寸或比例者。 Hereinafter, the form for carrying out the invention will be described in detail. In addition, the structures described below are exemplified, and are not intended to limit the scope of the invention. In the description of the drawings, the same reference numerals will be given to the same elements, and the repeated description will be omitted as appropriate. Further, in each cross-sectional view shown in the description of the manufacturing method, the thickness or size of the semiconductor substrate or other layers is convenient for explanation, and does not necessarily indicate the actual size or ratio.
首先，關於對半導體基板進行離子照射之離子照射系統進行說明。第1圖係模式表示離子照射系統的概略結構之圖。離子照射系統10具備：加速器12；晶圓傳送裝置14，保持並傳送半導體晶圓；及射束傳輸導管16，將從加速器12射出之離子束引導至晶圓傳送裝置14。 First, an ion irradiation system that performs ion irradiation on a semiconductor substrate will be described. Fig. 1 is a view showing a schematic configuration of an ion irradiation system. The ion irradiation system 10 includes an accelerator 12, a wafer transfer device 14 that holds and transports a semiconductor wafer, and a beam transfer conduit 16 that guides the ion beam emitted from the accelerator 12 to the wafer transfer device 14.
加速器12對離子進行加速並將其作為離子束向外部 射出。作為加速器12，例如使用迴旋加速器方式或凡德格拉夫(Van de Graaff)方式的裝置。晶圓傳送裝置14具備：容納部(未圖示)，容納複數個傳送板18；照射腔室20，對傳送板18所搭載之晶圓照射離子束；移動機構22，在容納部與照射腔室20之間移動傳送板18。在射束傳輸導管16的中途設置有將內部維持成真空之真空泵或對射束方向進行校正之電磁線圈等。 Accelerator 12 accelerates the ions and acts as an ion beam to the outside Shoot out. As the accelerator 12, for example, a cyclotron method or a Van de Graaff type device is used. The wafer transfer device 14 includes a housing portion (not shown) that accommodates a plurality of transfer plates 18, an irradiation chamber 20 that irradiates an ion beam to a wafer mounted on the transfer plate 18, and a moving mechanism 22 in the housing portion and the irradiation chamber The transfer plate 18 is moved between the chambers 20. In the middle of the beam transfer conduit 16, a vacuum pump that maintains the inside of the vacuum or an electromagnetic coil that corrects the beam direction is provided.
第2圖係表示傳送板的一例之圖。傳送板18具有搭載複數個晶圓24之搭載部26。晶圓24以搭載於搭載部26之狀態被保持在預定位置。移動機構22向搭載於一個傳送板18之所有晶圓24依次照射離子束，若離子照射處理結束，則使傳送用軸28的端部28a卡合於設置在傳送板18的端部之被卡合部30，使傳送板18返回到容納部。並且，使下一個傳送板18向照射腔室20移動。 Fig. 2 is a view showing an example of a transfer plate. The transfer plate 18 has a mounting portion 26 on which a plurality of wafers 24 are mounted. The wafer 24 is held at a predetermined position in a state of being mounted on the mounting portion 26 . The moving mechanism 22 sequentially irradiates the ion beam to all the wafers 24 mounted on one of the transfer plates 18, and when the ion irradiation process is completed, the end portion 28a of the transfer shaft 28 is engaged with the card set at the end of the transfer plate 18. The joint 30 returns the conveying plate 18 to the accommodating portion. Further, the next transfer plate 18 is moved to the irradiation chamber 20.
第3圖係模式表示離子束的照射圖像之圖。從加速器12射出之離子束B，其方向藉由磁鐵32的移動而發生變化。並且，藉由以離子束B依次掃描晶圓24的表面，在晶圓24的預定區域進行離子照射來形成高電阻層34。另外，在晶圓24的照射面的前方，為了調整離子束的加速能而配設有鋁製的阻尼器36。阻尼器36例如使用鋁箔等金屬箔。 Fig. 3 is a view showing an image of an irradiation of an ion beam. The direction of the ion beam B emitted from the accelerator 12 changes by the movement of the magnet 32. Further, the high resistance layer 34 is formed by sequentially scanning the surface of the wafer 24 with the ion beam B and performing ion irradiation on a predetermined region of the wafer 24. Further, a damper 36 made of aluminum is disposed in front of the irradiation surface of the wafer 24 in order to adjust the acceleration energy of the ion beam. The damper 36 is, for example, a metal foil such as an aluminum foil.
接著，對高電阻層34進行說明。第4圖係模式表示形成有高電阻層之晶圓的剖面圖之圖。如第4圖所示，藉由離子束B而在晶圓24的預定深度形成高電阻層34。藉 由離子照射形成高電阻層之機理(mechanism)可以如下考慮。 Next, the high resistance layer 34 will be described. Fig. 4 is a view showing a cross-sectional view of a wafer in which a high resistance layer is formed. As shown in FIG. 4, the high resistance layer 34 is formed at a predetermined depth of the wafer 24 by the ion beam B. borrow The mechanism for forming a high resistance layer by ion irradiation can be considered as follows.
若對晶圓進行離子照射，則離子到達至與離子的加速能對應之深度。此時，在包含到達之區域之附近形成晶格缺陷，晶體的規則性(周期性)成為混亂之狀態。在該種晶格缺陷較多的區域中電子易散射，電子的移動受阻。亦即，在藉由離子照射而產生局部性地晶格缺陷之區域中，電阻率上升。 When the wafer is ion-irradiated, the ions reach a depth corresponding to the acceleration energy of the ions. At this time, a lattice defect is formed in the vicinity of the region including the arrival, and the regularity (periodicity) of the crystal becomes a state of confusion. In such a region where there are many lattice defects, electrons are easily scattered, and the movement of electrons is hindered. That is, in a region where localized lattice defects are generated by ion irradiation, the resistivity increases.
第5圖係表示離子照射後的自矽晶圓表面的深度與電阻率的關係的一例之曲線圖。其中，已測定之矽晶圓係對藉由CZ(Czochralski：切克勞斯基)法製作出之N型的單晶矽(基板電阻率4Ω．cm)進行切片者。另外，作為本實施形態之晶圓，除了矽(Si)以外，還能夠使用碳化矽(SiC)、氮化鎵(GaN)等。 Fig. 5 is a graph showing an example of the relationship between the depth of the surface of the wafer and the specific resistance after ion irradiation. Among them, the measured tantalum wafer was subjected to slicing of N-type single crystal germanium (substrate resistivity: 4 Ω.cm) produced by the CZ (Czochralski: Czochralski) method. Further, as the wafer of the present embodiment, in addition to germanium (Si), tantalum carbide (SiC), gallium nitride (GaN), or the like can be used.
對於該N型的CZ矽晶圓，將藉由迴旋加速器以能量-23MeV進行加速，並通過減速材(鋁箔)調整為離子打入深度9μm之3He+離子，以劑量1.0E+13cm-2的照射量進行照射。 For the N-type CZ 矽 wafer, it will be accelerated by the cyclotron at an energy of -23 MeV, and adjusted to a depth of 9 μm of 3 He + ions by a decelerating material (aluminum foil) at a dose of 1.0E+13 cm -2 . The amount of exposure is irradiated.
其結果，如第5圖所示，電阻率的深度方向的變化為在深度9.5微米的位置成為峰值電阻率1000Ω．cm之山型函數。並且，電阻率成為峰值的一半之半值幅為9.2μm左右。在此，將包含於該半值幅之區域稱為高電阻層34。另外，高電阻層34的定義不一定限定於此，亦可為電阻率高於周圍的預定區域。 As a result, as shown in Fig. 5, the change in the depth direction of the resistivity is a peak resistivity of 1000 Ω at a position of a depth of 9.5 μm. The mountain type function of cm. Further, the resistivity is half the value of half of the peak value of about 9.2 μm. Here, the region included in the half-value width is referred to as a high resistance layer 34. Further, the definition of the high resistance layer 34 is not necessarily limited to this, and may be a predetermined region in which the specific resistance is higher than the surroundings.
另外，為了在預定區域形成高電阻層，能夠藉由適當選擇離子照射的加速能或離子種類、照射量來實現。第6圖(a)係表示電阻率峰值的深度不同之3個高電阻層的曲線圖之圖，第6圖(b)係表示半值幅不同之3個高電阻層的曲線圖之圖。 Further, in order to form a high-resistance layer in a predetermined region, it can be realized by appropriately selecting the acceleration energy, the ion species, and the irradiation amount of the ion irradiation. Fig. 6(a) is a graph showing a graph of three high-resistance layers having different depths of the resistivity peak, and Fig. 6(b) is a graph showing graphs of three high-resistance layers having different half-value widths.
如第6圖(a)所示，例如能夠藉由調整離子照射時的離子的加速能來自由設定形成高電阻層之深度。例如，可以以0.001MeV以上的加速能進行離子照射。或者，亦可以以0.1MeV以上的加速能進行。並且，可以以100MeV以下的加速能進行離子照射。或者，亦可以以30MeV以下的加速能進行。 As shown in Fig. 6(a), for example, the depth of the high-resistance layer can be set by adjusting the acceleration energy of ions during ion irradiation. For example, ion irradiation can be performed with an acceleration energy of 0.001 MeV or more. Alternatively, it can be carried out with an acceleration energy of 0.1 MeV or more. Further, ion irradiation can be performed with an acceleration energy of 100 MeV or less. Alternatively, it can be carried out with an acceleration energy of 30 MeV or less.
並且，如第6圖(b)所示，例如能夠藉由適當選擇使用於離子照射之離子種類來形成半值幅不同之高電阻層。使用於離子照射之離子種類可舉出選自由H、He、B、C、N、O、Ne、Si、Ar、Kr、Xe構成之群中之至少1種原子被離子化者。具體地，例如可舉出1H+、2H+、3He2+、4He2+等。 Further, as shown in FIG. 6(b), for example, a high-resistance layer having a different half-value width can be formed by appropriately selecting the ion species used for ion irradiation. The ion species used for ion irradiation may be one in which at least one atom selected from the group consisting of H, He, B, C, N, O, Ne, Si, Ar, Kr, and Xe is ionized. Specifically, for example, 1 H + , 2 H + , 3 He 2+ , 4 He 2+ , and the like can be given.
如此，在離子照射系統10中，能夠藉由調整離子種類、加速能、離子照射量(射束電流、照射時間)來適當設定形成在晶圓中的預定區域之高電阻層的位置或寬度、電阻率的大小。 As described above, in the ion irradiation system 10, the position or width of the high-resistance layer formed in a predetermined region in the wafer can be appropriately set by adjusting the ion type, the acceleration energy, the ion irradiation amount (beam current, and the irradiation time), The size of the resistivity.
接著，對適於執行形成高電阻層之製程的時間點進行說明。如前所述，半導體基板的電阻率會因製造半導體裝置時的熱處理等發生變化。 Next, a description will be given of a time point suitable for performing a process of forming a high resistance layer. As described above, the electrical resistivity of the semiconductor substrate changes due to heat treatment or the like in the case of manufacturing a semiconductor device.
第7圖係表示本實施形態之半導體裝置的製造方法的一例之流程圖。首先，藉由各種製程，在已準備之矽晶圓上形成元件(S10)，進一步形成配線(S12)。此時，藉由因熱處理而產生之雜質的擴散等，基板的電阻率下降。因此，本實施形態中，在該些製程之後，藉由離子照射形成高電阻層(S14)。如此，本實施形態中，在高電阻層形成製程之前，進行伴隨對半導體基板的熱處理之元件形成製程或配線(電路)形成製程。亦即，在成為電阻率發生變化之原因之一之熱處理等製程之後，藉由離子照射形成高電阻層。藉此，能夠製造確保了所希望的電阻率之半導體裝置。 Fig. 7 is a flow chart showing an example of a method of manufacturing the semiconductor device of the embodiment. First, an element (S10) is formed on a prepared wafer by various processes, and wiring (S12) is further formed. At this time, the resistivity of the substrate is lowered by the diffusion of impurities generated by the heat treatment or the like. Therefore, in the present embodiment, after the processes, the high resistance layer is formed by ion irradiation (S14). As described above, in the present embodiment, before the high-resistance layer forming process, an element forming process or a wiring (circuit) forming process accompanying heat treatment of the semiconductor substrate is performed. That is, after the heat treatment or the like which is one of the causes of the change in the electrical resistivity, the high resistance layer is formed by ion irradiation. Thereby, it is possible to manufacture a semiconductor device in which a desired resistivity is secured.
已形成高電阻層之半導體基板，在形成保護膜(S16)並研磨背面(S18)後，在後製程(S20)中進行處理，從而作為半導體積體電路而完成。後製程包含例如切割晶圓來單片化之製程、將單片化之晶片與安裝基板以引線結合(wire bond)進行接線之製程、及以樹脂密封晶片之製程。 The semiconductor substrate having the high resistance layer formed thereon is formed as a semiconductor integrated circuit after the protective film (S16) is formed and the back surface is polished (S18), and then processed in the subsequent process (S20). The post-process includes, for example, a process of dicing a wafer to singulate, a process of wiring a singulated wafer and a mounting substrate by wire bonding, and a process of sealing the wafer with a resin.
雖然亦能夠在後製程等之後形成高電阻層，但由於係以在半導體基板上除了元件或配線以外，形成有各種層或構件之狀態進行離子照射，因此調整離子照射的照射條件變得困難。並且，單片化之晶片難以進行離子照射時的定位或操作。因此，在形成高電阻層之製程之後，進行電阻率實際上不產生變化之保持膜的形成、背面的研磨、後製程等，從而不會產生如前所述的問題。 Although the high-resistance layer can be formed after the post-process or the like, since the ion irradiation is performed in a state in which various layers or members are formed on the semiconductor substrate except for the element or the wiring, it is difficult to adjust the irradiation conditions of the ion irradiation. Moreover, it is difficult for the singulated wafer to be positioned or operated during ion irradiation. Therefore, after the process of forming the high-resistance layer, the formation of the holding film in which the resistivity does not substantially change, the polishing of the back surface, the post-process, and the like are performed, so that the problem as described above does not occur.
接著，對於藉由本實施形態之製造方法製造出之半導體裝置的特性的改善進行說明。第8圖(a)係表示習知之半導體裝置的一例之剖面圖，第8圖(b)係表示本實施形態之半導體裝置的一例之剖面圖。 Next, the improvement of the characteristics of the semiconductor device manufactured by the manufacturing method of this embodiment will be described. Fig. 8(a) is a cross-sectional view showing an example of a conventional semiconductor device, and Fig. 8(b) is a cross-sectional view showing an example of the semiconductor device of the embodiment.
通常，IC所使用之矽基板為n型或p型的基板，電阻率為數十Ωcm，較小，因此電導率較高。若已接收之電訊號經由電感等接收元件或寄生元件而進入到矽基板內，則藉由矽基板的電阻成份成為焦耳熱而被消耗，並產生訊號損失。 Generally, the germanium substrate used in the IC is an n-type or p-type substrate, and the resistivity is several tens of Ωcm, which is small, and thus the electrical conductivity is high. If the received electrical signal enters the germanium substrate via a receiving element or a parasitic element such as an inductor, the resistance component of the germanium substrate becomes Joule heat and is consumed, and signal loss occurs.
因此，若提高基板的電阻率則訊號損失(流過基板之信號)減少，因此Q值上升。換言之，Q值越高訊號損失越少，從而成為持有優異特性之電感。 Therefore, if the resistivity of the substrate is increased, the signal loss (signal flowing through the substrate) is reduced, and thus the Q value is increased. In other words, the higher the Q value, the less the signal loss, and thus the inductance with excellent characteristics.
因此，能夠藉由提高設置有電感之區域的下層的基板的電阻率來提高電感的Q值。例如，如第8圖(a)所示之半導體裝置100，在作為高電阻基板之晶圓101的表面側設置有電感形成區域102，在背面側設置有元件形成區域104。電感形成區域102與元件形成區域104之間的中間區域106係未實施有特殊處理，接近於晶圓最初的電阻率的區域。 Therefore, the Q value of the inductance can be increased by increasing the resistivity of the lower substrate of the region in which the inductance is provided. For example, in the semiconductor device 100 shown in FIG. 8(a), the inductor forming region 102 is provided on the surface side of the wafer 101 as the high-resistance substrate, and the element forming region 104 is provided on the back surface side. The intermediate region 106 between the inductor forming region 102 and the element forming region 104 is not subjected to a special process and is close to the region of the initial resistivity of the wafer.
半導體裝置100中，元件形成區域104及中間區域106均為具有接近於晶圓最初的電阻率的較高電阻率之高電阻層108。亦即，形成有電晶體等之元件形成區域104的電阻率始終較高。由於該種電阻率的大小，易發生IC(積體電路)中的閂鎖，易引起電路中的故障。因此，提 高基板整體的電阻率對於IC而言為不佳。 In the semiconductor device 100, the element formation region 104 and the intermediate region 106 are high resistance layers 108 having a relatively high resistivity close to the initial resistivity of the wafer. That is, the resistivity of the element formation region 104 in which the transistor or the like is formed is always high. Due to the magnitude of such resistivity, latch-up in the IC (integrated circuit) is liable to occur, which is liable to cause malfunction in the circuit. Therefore, mention The resistivity of the high substrate as a whole is not good for the IC.
因此，本實施形態之半導體裝置例如能夠藉由採用第8圖(b)所示之結構來降低IC中之故障。半導體裝置60使用藉由CZ法製作出之晶圓62。藉由CZ法製作出之晶圓62與藉由FZ法等製作出之高電阻晶圓相比，電阻率較低，且價格較低。 Therefore, the semiconductor device of the present embodiment can reduce the failure in the IC by, for example, adopting the configuration shown in Fig. 8(b). The semiconductor device 60 uses the wafer 62 fabricated by the CZ method. The wafer 62 produced by the CZ method has a lower resistivity and a lower price than a high-resistance wafer produced by the FZ method or the like.
半導體裝置60中，在晶圓62的表面側設置有電感形成區域64，在背面側設置有元件形成區域66。電感形成區域64與元件形成區域66之間的中間區域68係藉由所述之離子照射來提高電阻率之高電阻層70。藉由該種離子照射，不提高晶圓62整體的電阻率就能夠使中間區域68成為高電阻層70。亦即，由於能夠不提高無需高電阻化的元件形成區域66的電阻率就能夠在電感形成區域64的下部形成高電阻層70，因此能夠在提高電感的Q值的同時，抑制元件形成區域66中之電路中的閂鎖的發生。 In the semiconductor device 60, an inductor forming region 64 is provided on the surface side of the wafer 62, and an element forming region 66 is provided on the back surface side. The intermediate region 68 between the inductor forming region 64 and the element forming region 66 is a high resistance layer 70 which is increased in resistivity by the ion irradiation described above. By this type of ion irradiation, the intermediate portion 68 can be made into the high resistance layer 70 without increasing the resistivity of the entire wafer 62. In other words, since the high-resistance layer 70 can be formed in the lower portion of the inductor forming region 64 without increasing the resistivity of the element forming region 66 which does not require high resistance, the element forming region 66 can be suppressed while increasing the Q value of the inductor. The occurrence of a latch in the circuit.
第9圖(a)係表示半導體裝置的其他例子之俯視圖，第9圖(b)係第9圖(a)中所示之半導體裝置的A-A剖面圖。 Fig. 9(a) is a plan view showing another example of the semiconductor device, and Fig. 9(b) is a cross-sectional view taken along line A-A of the semiconductor device shown in Fig. 9(a).
半導體裝置51中，在晶圓24的上部藉由周知的技術形成有數位電路52與類比電路54。如第9圖(a)所示，在數位電路52及類比電路54的周圍藉由本實施形態之離子照射形成有高電阻層56。並且，如第9圖(b)所示，在數位電路52及類比電路54的下部，藉由本實施形態之離子照射形成有高電阻層58。 In the semiconductor device 51, a digital circuit 52 and an analog circuit 54 are formed on the upper portion of the wafer 24 by a well-known technique. As shown in Fig. 9(a), the high resistance layer 56 is formed by ion irradiation of the present embodiment around the digital circuit 52 and the analog circuit 54. Further, as shown in Fig. 9(b), in the lower portion of the digital circuit 52 and the analog circuit 54, the high-resistance layer 58 is formed by ion irradiation in the present embodiment.
該些高電阻層56、58作為抑制從數位電路52產生之噪聲(訊號)在晶圓24內傳播之噪聲屏蔽層而發揮功能。因此，半導體裝置51中，在水平/垂直兩個方向上屏蔽從數位電路52發生之噪聲，因此可抑制數位電路52發生之噪聲侵入到類比電路54。 The high resistance layers 56 and 58 function as noise shielding layers that suppress noise (signals) generated from the digital circuit 52 from propagating in the wafer 24. Therefore, in the semiconductor device 51, noise generated from the digital circuit 52 is shielded in both the horizontal/vertical directions, and therefore noise generated by the digital circuit 52 can be suppressed from intruding into the analog circuit 54.
第10圖(a)至第10圖(d)表示本發明的一實施形態之半導體裝置的製造方法的一例。半導體裝置例如為系統LSI、SOC(System On a Chip)或積體電路(IC)。該方法具備使用遮罩212形成高電阻層222之製程。在半導體基板200的背面204準備遮罩212。詳細內容如後述，高電阻層形成製程具備：在半導體基板200的背面204形成遮罩圖案216之製程(參閱第10圖(a)及第10圖(b))、從遮罩圖案側向遮罩圖案216及半導體基板200進行離子照射，以在半導體基板200的內部形成高電阻層222之製程(參閱第10圖(c))、及從半導體基板200的背面204去除遮罩圖案216之製程(參閱第10圖(d))。 10(a) to 10(d) show an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device is, for example, a system LSI, an SOC (System On a Chip), or an integrated circuit (IC). This method has a process of forming a high resistance layer 222 using a mask 212. A mask 212 is prepared on the back surface 204 of the semiconductor substrate 200. As will be described later, the high-resistance layer forming process includes a process of forming a mask pattern 216 on the back surface 204 of the semiconductor substrate 200 (see FIGS. 10( a ) and 10 ( b )), and shielding from the mask pattern side. The mask pattern 216 and the semiconductor substrate 200 are subjected to ion irradiation to form a high resistance layer 222 inside the semiconductor substrate 200 (see FIG. 10( c )), and a process of removing the mask pattern 216 from the back surface 204 of the semiconductor substrate 200 . (See Figure 10 (d)).
其中，半導體基板200為低電阻的半導體基板，基板電阻率調整為例如10Ω．cm以下、50Ω．cm以下、100Ω．cm以下、500Ω．cm以下或1000Ω．cm以下。形成於該半導體基板200之高電阻層222具有比在該基板上形成高電阻層222之前的基板電阻率更大的峰值電阻率(例如參閱第5 圖)。因此，高電阻層222的峰值電阻率例如大於10Ω．cm、大於50Ω．cm、大於100Ω．cm、大於500Ω．cm或大於1000Ω．cm。 The semiconductor substrate 200 is a low-resistance semiconductor substrate, and the substrate resistivity is adjusted to, for example, 10 Ω. Below cm, 50Ω. Below cm, 100Ω. Below cm, 500Ω. Below cm or 1000Ω. Below cm. The high resistance layer 222 formed on the semiconductor substrate 200 has a peak resistivity greater than that of the substrate before the high resistance layer 222 is formed on the substrate (for example, see the fifth Figure). Therefore, the peak resistivity of the high resistance layer 222 is, for example, greater than 10 Ω. Cm, greater than 50Ω. Cm, greater than 100Ω. Cm, greater than 500Ω. Cm or greater than 1000 Ω. Cm.
第10圖(a)至第10圖(d)中示有半導體基板200的部份側剖面圖。如第10圖(a)所示，首先，準備半導體基板200(以下簡稱為基板200)。基板200具備主面202及其相反側的背面204。 A partial side cross-sectional view of the semiconductor substrate 200 is shown in Figs. 10(a) to 10(d). As shown in Fig. 10(a), first, a semiconductor substrate 200 (hereinafter simply referred to as a substrate 200) is prepared. The substrate 200 includes a main surface 202 and a back surface 204 on the opposite side.
以下說明中，有時將沿主面202(或背面204)之基板200的面內方向稱為橫向(圖中為左右方向)。並且，有時將垂直於主面202(或背面204)之方向稱為縱向或深度方向(圖中為上下方向)。將在半導體基板200的縱向上接近於主面202側稱為上方，遠離主面202側稱為下方。 In the following description, the in-plane direction of the substrate 200 along the main surface 202 (or the back surface 204) may be referred to as a lateral direction (left-right direction in the drawing). Further, the direction perpendicular to the main surface 202 (or the back surface 204) is sometimes referred to as a longitudinal direction or a depth direction (upward and downward directions in the drawing). The side closer to the main surface 202 in the longitudinal direction of the semiconductor substrate 200 is referred to as the upper side, and the side away from the main surface 202 is referred to as the lower side.
在包含主面202之基板表層部份設置有元件區域206。因此，主面202還能夠稱為程序形成面。元件區域206為包含元件和/或配線層之電路區域。元件區域206在半導體基板200的主面側沿橫向擴展，在縱向具有一定深度。元件區域206可以具有根據橫向位置不同之深度(例如參閱第11圖(b))。 An element region 206 is provided on a portion of the surface layer of the substrate including the main surface 202. Therefore, the main surface 202 can also be referred to as a program forming surface. Component region 206 is a circuit region that includes components and/or wiring layers. The element region 206 is laterally expanded on the main surface side of the semiconductor substrate 200 and has a certain depth in the longitudinal direction. The element region 206 may have a different depth depending on the lateral position (see, for example, FIG. 11(b)).
當已進行元件形成製程(第7圖的S10)時，元件區域206至少具備1個電路元件(例如主動元件或被動元件)。元件區域206可以具備例如RF-CMOS的電感。元件區域206亦可以具備具有沿橫向形成之電流路徑之所謂臥式半導體元件。元件區域206可以至少具備1個電子電 路(例如類比電路54或數位電路52(參閱第9圖(a)及第9圖(b)))。當尚未進行元件形成製程(第7圖的S10)時，元件區域206為應在以後的元件形成製程中形成元件之區域。另外，如第8圖(a)及第8圖(b)所示，可以在基板的背面設置另1個元件區域。 When the component forming process (S10 of FIG. 7) has been performed, the element region 206 has at least one circuit component (for example, an active component or a passive component). The element region 206 may be provided with an inductance such as RF-CMOS. The element region 206 may also be provided with a so-called horizontal semiconductor element having a current path formed in the lateral direction. The component area 206 can have at least one electronic power Circuit (for example, analog circuit 54 or digital circuit 52 (see Figures 9(a) and 9(b))). When the element forming process (S10 of Fig. 7) has not been performed, the element region 206 is an area where the element should be formed in the subsequent element forming process. Further, as shown in Figs. 8(a) and 8(b), another element region may be provided on the back surface of the substrate.
半導體基板200在主面202與背面204之間具備基體208。基體208對元件區域206提供機械支撐。基體208在主面202與背面204之間具備非元件部份210。非元件部份210存在於元件區域206的下方，因此存在於元件區域206與背面204之間。 The semiconductor substrate 200 is provided with a base 208 between the main surface 202 and the back surface 204. The base 208 provides mechanical support to the component region 206. The base 208 is provided with a non-element portion 210 between the main surface 202 and the back surface 204. The non-element portion 210 exists below the element region 206 and thus exists between the element region 206 and the back surface 204.
本實施形態之方法可以具備使背面204平坦化之製程。該平坦化製程中，為了使半導體基板200的厚度均勻化而可以包含例如研磨背面204之製程。如此，能夠將作為離子束224(參閱第10圖(c))的入射面之背面204用作具有基準高度之基準面。藉此，能夠使藉由離子束224形成之缺陷區域(亦即，高電阻層的電阻率峰值)，準確地對位於以背面204為基準之設計上的深度位置。另外，例如在不要求高電阻層的嚴格定位時，或背面204的平坦度例如藉由在本方法之前進行之其他處理而已確保時，可以不進行該平坦化製程。 The method of the present embodiment may include a process of flattening the back surface 204. In the planarization process, in order to make the thickness of the semiconductor substrate 200 uniform, for example, a process of polishing the back surface 204 may be included. In this manner, the back surface 204 of the incident surface as the ion beam 224 (see FIG. 10(c)) can be used as the reference surface having the reference height. Thereby, the defect region formed by the ion beam 224 (that is, the peak value of the resistivity of the high resistance layer) can be accurately positioned on the depth position of the design based on the back surface 204. Further, for example, when the strict positioning of the high-resistance layer is not required, or the flatness of the back surface 204 is ensured by, for example, other processing performed before the method, the planarization process may not be performed.
如第10圖(b)所示，半導體基板200的背面204上形成有遮罩212。遮罩212具備具有凹部之遮罩圖案216。其中，遮罩212的凹部為開口部214，因此背面204在開口部214露出。遮罩圖案216覆蓋背面204。其他實 施形態中，遮罩212的凹部可以具有比遮罩圖案216更薄的遮罩材料層。 As shown in FIG. 10(b), a mask 212 is formed on the back surface 204 of the semiconductor substrate 200. The mask 212 is provided with a mask pattern 216 having a concave portion. However, since the concave portion of the mask 212 is the opening portion 214, the back surface 204 is exposed at the opening portion 214. The mask pattern 216 covers the back side 204. Other real In the embodiment, the recess of the mask 212 may have a thinner layer of masking material than the mask pattern 216.
遮罩圖案216可以由任意材料形成，可以為例如金屬或抗蝕劑。當遮罩圖案216為金屬膜時，遮罩圖案216由包含濕式電鍍或乾式電鍍(例如真空蒸鍍)之任意周知的成膜方法形成。此時，相當於開口部214之基板200的表面為了避免遮罩材料的附著而以薄膜或膠帶等保護構件進行包覆。當遮罩圖案216為抗蝕膜時，遮罩圖案216可由任意周知的抗蝕劑塗佈方法形成。 The mask pattern 216 may be formed of any material, such as a metal or a resist. When the mask pattern 216 is a metal film, the mask pattern 216 is formed by any well-known film forming method including wet plating or dry plating (for example, vacuum evaporation). At this time, the surface of the substrate 200 corresponding to the opening 214 is covered with a protective member such as a film or a tape in order to avoid adhesion of the mask material. When the mask pattern 216 is a resist film, the mask pattern 216 can be formed by any well-known resist coating method.
通常要求在元件區域206的正下方的必要區域218局部設置高電阻層222(參閱第10圖(c))。在背面204準備遮罩212時，對準該必要區域218形成開口部214。遮罩圖案216對準不必要區域220而形成。在此，不必要區域220如同文字，可以意味無需設置高電阻層222之區域。或者，不必要區域220亦可以意味並非如必要區域218那樣在元件區域206的正下方設置高電阻層222，而係要求在與必要區域218中之高電阻層222縱向上不同之位置設置高電阻層222之區域。 It is generally required to partially place the high resistance layer 222 in the necessary region 218 directly under the element region 206 (see Fig. 10(c)). When the mask 212 is prepared on the back surface 204, the necessary portion 218 is aligned to form the opening portion 214. The mask pattern 216 is formed by aligning the unnecessary regions 220. Here, the unnecessary area 220 is like a character, which may mean that it is not necessary to provide an area of the high resistance layer 222. Alternatively, the unnecessary region 220 may also mean that the high resistance layer 222 is not disposed directly under the element region 206 as in the necessary region 218, and it is required to set a high resistance at a position different from the longitudinal direction of the high resistance layer 222 in the necessary region 218. The area of layer 222.
遮罩圖案216以使離子束224透過之方式形成。遮罩圖案216的厚度設定為，將不必要區域220中之高電阻層222形成在相對於必要區域218中之高電阻層222在縱向上具有所希望的間隔之深度。藉由調整遮罩圖案216的厚度，能夠控制從離子束224朝向基板200的入射面，至藉由離子束224形成之缺陷區域的距離。因此，藉由對遮罩 圖案216照射離子束224，能夠在不必要區域220中，在所希望的深度形成高電阻層222。如此，遮罩212製作成高電阻層222在基板200的面內方向的不同部位上形成在不同之深度。 The mask pattern 216 is formed to allow the ion beam 224 to pass therethrough. The thickness of the mask pattern 216 is set such that the high resistance layer 222 in the unnecessary region 220 is formed at a depth having a desired interval in the longitudinal direction with respect to the high resistance layer 222 in the necessary region 218. By adjusting the thickness of the mask pattern 216, it is possible to control the distance from the incident surface of the ion beam 224 toward the substrate 200 to the defect region formed by the ion beam 224. Therefore, by masking The pattern 216 illuminates the ion beam 224 to form the high resistance layer 222 at a desired depth in the unnecessary region 220. In this manner, the mask 212 is formed such that the high resistance layer 222 is formed at different depths in different portions of the in-plane direction of the substrate 200.
可以代替對遮罩圖案216的厚度的調整，或在進行厚度調整的同時，將遮罩圖案216的材料規定為將高電阻層222形成在預定的深度。如此亦能夠藉由橫向位置來將高電阻層222形成在不同之深度。 Instead of adjusting the thickness of the mask pattern 216, or while performing thickness adjustment, the material of the mask pattern 216 is defined to form the high resistance layer 222 at a predetermined depth. It is also possible to form the high resistance layer 222 at different depths by the lateral position.
或者，可以以遮罩圖案216屏蔽離子束224之方式來規定遮罩圖案216的厚度和/或材料。此時，不必要區域220中不形成高電阻層222。但是，在如本實施形態那樣藉由離子照射來形成電阻率較高的晶格缺陷層時，由於離子束224包含高能量離子，因此對屏蔽離子束224之遮罩圖案216進行設計也許並不容易。 Alternatively, the thickness and/or material of the mask pattern 216 can be specified in a manner that the mask pattern 216 shields the ion beam 224. At this time, the high resistance layer 222 is not formed in the unnecessary region 220. However, when a lattice defect layer having a high resistivity is formed by ion irradiation as in the present embodiment, since the ion beam 224 contains high energy ions, the mask pattern 216 of the shield ion beam 224 may not be designed. easily.
如第10圖(c)所示，從遮罩212側向基板200進行離子照射。對在開口部214露出之背面204的部份與遮罩圖案216照射離子束224，在特定的深度形成顯著包含晶格缺陷之局部區域。這樣形成之晶格缺陷層為電阻率高於周圍(例如元件區域206)的高電阻層222。 As shown in Fig. 10(c), ion irradiation is performed on the substrate 200 from the side of the mask 212. The portion of the back surface 204 exposed at the opening portion 214 and the mask pattern 216 are irradiated with the ion beam 224 to form a local region significantly including a lattice defect at a specific depth. The lattice defect layer thus formed is a high resistance layer 222 having a higher resistivity than the surrounding (e.g., element region 206).
離子束224的照射條件規定為，在開口部214(亦即必要區域218)中在所希望的深度(例如元件區域206的正下方)形成高電阻層222。離子束224的照射條件如上述，包含例如離子種類、加速能、離子照射量(射束電流、照射時間)。本實施形態中，離子的加速能對準必要 區域218中之高電阻層222的目標深度進行了預先調整。 The irradiation condition of the ion beam 224 is defined such that the high resistance layer 222 is formed at a desired depth (for example, directly under the element region 206) in the opening portion 214 (that is, the necessary region 218). The irradiation conditions of the ion beam 224 include, for example, ion species, acceleration energy, and ion irradiation amount (beam current, irradiation time). In this embodiment, the acceleration of ions can be aligned The target depth of the high resistance layer 222 in the region 218 is pre-adjusted.
這樣，作為離子照射的結果，在非元件部份210形成高電阻層222。具體地，半導體基板200在必要區域218中元件區域206的正下方具備第1高電阻層226。並且，半導體基板200在不必要區域220中比第1高電阻層226更深的位置具備第2高電阻層228。高電阻層222形成於元件區域206外側的非元件部份210，因此元件區域206的電阻率保持為原本的低電阻基板的電阻率。 Thus, as a result of the ion irradiation, the high resistance layer 222 is formed in the non-element portion 210. Specifically, the semiconductor substrate 200 includes the first high resistance layer 226 directly under the element region 206 in the necessary region 218. Further, the semiconductor substrate 200 includes the second high resistance layer 228 at a position deeper than the first high resistance layer 226 in the unnecessary region 220. The high resistance layer 222 is formed on the non-element portion 210 outside the element region 206, so the resistivity of the element region 206 is maintained as the resistivity of the original low resistance substrate.
第1高電阻層226與元件區域206建立關連來使用。例如，第1高電阻層226相當於在電感形成區域64的下部形成之高電阻層70(參閱第8圖(b))。或者，第1高電阻層226相當於在電路52、54的下部形成之高電阻層58(參閱第9圖(b))。另一方面，第2高電阻層228僅單純存在於非元件部份210而並不使用。 The first high resistance layer 226 is associated with the element region 206 for use. For example, the first high resistance layer 226 corresponds to the high resistance layer 70 formed under the inductance forming region 64 (see FIG. 8(b)). Alternatively, the first high resistance layer 226 corresponds to the high resistance layer 58 formed under the circuits 52 and 54 (see FIG. 9(b)). On the other hand, the second high resistance layer 228 is simply used in the non-element portion 210 and is not used.
藉此，依本實施形態，藉由使用遮罩212，能夠在必要區域218選擇性地形成高電阻層222。如此，不僅能夠在橫向的任意部位形成高電阻層222，還能夠藉由調整遮罩圖案216的厚度和/或材料，在縱向任意部位形成高電阻層222。因此，能夠在半導體基板200中在縱向及橫向的任意部位自如地配置高電阻層222。 Thereby, according to the present embodiment, the high resistance layer 222 can be selectively formed in the necessary region 218 by using the mask 212. Thus, not only the high-resistance layer 222 can be formed in any portion in the lateral direction, but also the high-resistance layer 222 can be formed in any position in the longitudinal direction by adjusting the thickness and/or material of the mask pattern 216. Therefore, the high resistance layer 222 can be freely disposed in the semiconductor substrate 200 at any position in the vertical direction and the lateral direction.
並且，在主面202(程序形成面)與相反側的背面204準備遮罩212並從遮罩側進行離子照射，且將藉由離子照射形成之缺陷區域固定在非元件部份210，因此能夠避免朝向元件區域206的離子照射。不進行朝向元件或電 路(例如電晶體等半導體元件或數位電路部份等)的離子照射就能夠形成高電阻層222。能夠從可能藉由高能量的離子衝突而產生在元件及電路上之不可預料的損傷或劣化中保護元件及電路。 Further, the mask 212 is prepared on the main surface 202 (program forming surface) and the back surface 204 on the opposite side, and ion irradiation is performed from the mask side, and the defective region formed by ion irradiation is fixed to the non-element portion 210, thereby enabling Ion irradiation towards the element region 206 is avoided. Not facing the component or electricity The high resistance layer 222 can be formed by ion irradiation of a circuit such as a semiconductor element such as a transistor or a digital circuit portion. It is possible to protect components and circuits from unpredictable damage or degradation on components and circuits that may result from high energy ion collisions.
如第10圖(d)所示，本實施形態之方法可以在進行離子照射之製程之後，還具備對背面204進行研磨或磨削來去除遮罩圖案216之製程。本實施形態中，背面204為非元件部份210，因此允許對背面204進行研磨或磨削。如此，能夠輕易地除掉遮罩212。半導體裝置的製造方法通常為了使基板200變薄至規定的厚度，在後製程(第7圖的S20)之前(或在後製程中)，具備對背面204進行研磨或磨削之製程。藉由將該種已有的製程利用於遮罩的去除，不對基板200的主面202帶來任何影響且不需要追加成本就能夠去除遮罩212。 As shown in FIG. 10(d), the method of the present embodiment may further include a process of polishing or grinding the back surface 204 to remove the mask pattern 216 after the ion irradiation process. In the present embodiment, the back surface 204 is the non-element portion 210, so that the back surface 204 is allowed to be ground or ground. In this way, the mask 212 can be easily removed. In the method of manufacturing a semiconductor device, in order to thin the substrate 200 to a predetermined thickness, a process for polishing or grinding the back surface 204 is provided before (or in the subsequent process of) the post-process (S20 in FIG. 7). By using such an existing process for the removal of the mask, the mask 212 can be removed without any influence on the main surface 202 of the substrate 200 and without additional cost.
第11圖(a)表示本發明的一實施形態之半導體裝置的製造方法的其他一例。如第11圖(a)所示，可以在主面202準備遮罩212。此時為了形成與第10圖所示之高電阻層222相同的結構，開口部214及遮罩圖案216與必要區域218及不必要區域220的位置關係成相反。亦即，開口部214形成於不必要區域220，遮罩區域216形成於必要區域218。離子照射條件規定為在必要區域218中在所希望的深度形成高電阻層222。由於主面202在開口部214露出，因此不必要區域220中之高電阻層222形成在比必要區域218更深處。另外，離子束224可在不必要區 域220中貫穿半導體基板200。 Fig. 11(a) shows another example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown in Fig. 11(a), a mask 212 can be prepared on the main surface 202. At this time, in order to form the same structure as the high resistance layer 222 shown in FIG. 10, the positional relationship between the opening portion 214 and the mask pattern 216 and the necessary region 218 and the unnecessary region 220 is reversed. That is, the opening portion 214 is formed in the unnecessary region 220, and the mask region 216 is formed in the necessary region 218. The ion irradiation conditions are defined to form the high resistance layer 222 at a desired depth in the necessary region 218. Since the main surface 202 is exposed at the opening portion 214, the high resistance layer 222 in the unnecessary region 220 is formed deeper than the necessary region 218. In addition, the ion beam 224 can be in an unnecessary area The semiconductor substrate 200 is penetrated in the domain 220.
第11圖(b)表示本發明的一實施形態之半導體裝置的製造方法的另一其他一例。第11圖(b)中亦與第11圖(a)相同地在主面202準備遮罩212。但是，第11圖(a)中使離子束224透過遮罩圖案216，相對於此，第11圖(b)中所示之遮罩212具備屏蔽離子束224之遮罩圖案216。藉此，遮罩212的開口部214形成於必要區域218，遮罩圖案216形成於不必要區域220。 Fig. 11(b) shows still another example of the method of manufacturing the semiconductor device according to the embodiment of the present invention. Similarly to Fig. 11(a), in Fig. 11(b), a mask 212 is prepared on the main surface 202. However, in FIG. 11(a), the ion beam 224 is transmitted through the mask pattern 216, whereas the mask 212 shown in FIG. 11(b) is provided with the mask pattern 216 for shielding the ion beam 224. Thereby, the opening portion 214 of the mask 212 is formed in the necessary region 218, and the mask pattern 216 is formed in the unnecessary region 220.
並且，第11圖(b)中，元件區域206在較淺側具備配線層240，在較深側具備元件形成區域242。配線層240在必要區域218具備例如電感形成區域64(參閱第8圖(b))。並且，配線層240在不必要區域220具備用於將元件形成區域242的元件相互連接來形成電路之配線或電感等。元件形成區域242具備例如電晶體、二極體、電阻、電容等元件。因此，如圖示，元件區域206具有根據橫向位置不同之深度。 Further, in FIG. 11(b), the element region 206 includes the wiring layer 240 on the shallow side and the element formation region 242 on the deep side. The wiring layer 240 includes, for example, an inductor forming region 64 in the necessary region 218 (see FIG. 8(b)). Further, the wiring layer 240 includes wirings, inductors, and the like for forming circuits in the unnecessary region 220 to connect the elements of the element formation region 242 to each other. The element formation region 242 includes elements such as a transistor, a diode, a resistor, and a capacitor. Thus, as illustrated, the component regions 206 have different depths depending on the lateral position.
離子照射條件規定為在必要區域218中在配線層240的正下方形成高電阻層222。必要區域218上形成有開口部214，因此離子束224照射於非元件部份210，在配線層240的正下方形成高電阻層222。在不必要區域220中，藉由遮罩圖案216屏蔽離子束224，不形成高電阻層222。其結果，在與元件形成區域242橫向上相鄰之部位選擇性地形成高電阻層222。如此，能夠在所希望的部位配置高電阻層222。 The ion irradiation condition is defined as forming the high resistance layer 222 directly under the wiring layer 240 in the necessary region 218. The opening portion 214 is formed in the necessary region 218, so that the ion beam 224 is irradiated to the non-element portion 210, and the high resistance layer 222 is formed directly under the wiring layer 240. In the unnecessary region 220, the ion beam 224 is shielded by the mask pattern 216, and the high resistance layer 222 is not formed. As a result, the high resistance layer 222 is selectively formed at a portion laterally adjacent to the element formation region 242. In this way, the high resistance layer 222 can be disposed at a desired portion.
在主面202準備遮罩212時，遮罩212可以構成為能夠從主面202裝卸自如地與其接觸(例如參閱第17圖)。或者，遮罩212可以從主面202隔著一定間隙來配置。如此一來，不會對元件區域206帶來較大的影響就能夠將遮罩212從基板200卸下。 When the main surface 202 prepares the mask 212, the mask 212 may be configured to be detachably contactable from the main surface 202 (see, for example, Fig. 17). Alternatively, the mask 212 can be disposed from the main surface 202 with a certain gap therebetween. In this way, the mask 212 can be detached from the substrate 200 without greatly affecting the element region 206.
第12圖(a)、第13圖(a)及第14圖(a)係例示在本發明的一實施形態之高電阻層形成製程中所使用之遮罩之俯視圖，第12圖(b)、第13圖(b)及第14圖(b)係表示第12圖(a)、第13圖(a)及第14圖(a)所示之遮罩的剖面圖。 FIGS. 12(a), 13(a) and 14(a) are plan views showing a mask used in a high-resistance layer forming process according to an embodiment of the present invention, and FIG. 12(b) FIGS. 13(b) and 14(b) are cross-sectional views showing the masks shown in FIGS. 12(a), 13(a) and 14(a).
第12圖(a)及第12圖(b)所示之遮罩300例如如第8圖(b)所示之半導體裝置60那樣，為了在電感的背後形成高電阻層而使用。遮罩300形成於矽基板302的背面側。遮罩300係具有幾個(圖中為4個)凹部304之金屬膜306。金屬膜306例如為鋁。金屬膜306的厚度例如為10μm~50μm左右。矽基板302的背面在凹部304露出。凹部304例如為一邊的長度為100μm~500μm左右的長方形。凹部304分別以與用於各電感之高電阻層對應之方式形成。 The mask 300 shown in FIGS. 12(a) and 12(b) is used to form a high-resistance layer behind the inductor, for example, as in the semiconductor device 60 shown in FIG. 8(b). The mask 300 is formed on the back side of the ruthenium substrate 302. The mask 300 is a metal film 306 having a plurality of (four in the drawing) recesses 304. The metal film 306 is, for example, aluminum. The thickness of the metal film 306 is, for example, about 10 μm to 50 μm. The back surface of the crucible substrate 302 is exposed in the concave portion 304. The concave portion 304 is, for example, a rectangular shape having a length of one side of about 100 μm to 500 μm. The recesses 304 are formed so as to correspond to the high resistance layers for the respective inductors.
第13圖(a)及第13圖(b)所示之遮罩308例如如第9圖(a)及第9圖(b)所示之半導體裝置51，為了形成用於隔離一個電路與其他電路之高電阻層56、58而使用。遮罩308形成於矽基板310的背面側。遮罩308為具有凹部312之金屬膜314。金屬膜314的厚度及材料例 如可以與第12圖(a)及第12圖(b)所示之金屬膜306相同。矽基板310在凹部312露出。 The mask 308 shown in FIGS. 13(a) and 13(b) is, for example, the semiconductor device 51 shown in FIGS. 9(a) and 9(b), in order to form a circuit for isolating one another. The high resistance layers 56, 58 of the circuit are used. A mask 308 is formed on the back side of the ruthenium substrate 310. The mask 308 is a metal film 314 having a recess 312. The thickness and material example of the metal film 314 It can be the same as the metal film 306 shown in Figs. 12(a) and 12(b). The germanium substrate 310 is exposed at the recess 312.
凹部312沿著一個電路區域316及與其相鄰之另一電路區域318的邊界細長地延伸。電路區域316、318在圖中以虛線表示。藉由凹部312，金屬膜314分離成覆蓋一側的電路區域316之部份與覆蓋另一側的電路區域318之部份。凹部312的寬度比2個電路區域316、318之間的距離更窄。凹部312的寬度例如為10μm~250μm左右，電路區域316、318之間的距離例如為約300μm。 The recess 312 extends elongately along the boundary of one circuit region 316 and another circuit region 318 adjacent thereto. Circuit regions 316, 318 are indicated by dashed lines in the figure. With the recess 312, the metal film 314 is separated into a portion covering the circuit region 316 on one side and a portion of the circuit region 318 covering the other side. The width of the recess 312 is narrower than the distance between the two circuit regions 316, 318. The width of the concave portion 312 is, for example, about 10 μm to 250 μm, and the distance between the circuit regions 316 and 318 is, for example, about 300 μm.
第14圖(a)及第14圖(b)所示之遮罩320與第13圖(a)及第13圖(b)所示之遮罩308相同地，為了形成用於電路間的隔離之高電阻層而使用。遮罩320形成於矽基板322的背面側。遮罩320為具有凹部324之金屬膜326。金屬膜326的厚度及材料例如可以與第12圖(a)及第12圖(b)所示之金屬膜306相同。矽基板322在凹部324露出。 The mask 320 shown in Figs. 14(a) and 14(b) is identical to the mask 308 shown in Figs. 13(a) and 13(b) in order to form isolation for use between circuits. Use as a high resistance layer. The mask 320 is formed on the back side of the ruthenium substrate 322. The mask 320 is a metal film 326 having a recess 324. The thickness and material of the metal film 326 can be the same as, for example, the metal film 306 shown in FIGS. 12(a) and 12(b). The germanium substrate 322 is exposed in the recess 324.
凹部324沿電路區域的外周形成為矩形的環狀。藉由凹部324，覆蓋電路區域之金屬膜326的島狀的部份從在其外側包圍島狀部份之金屬膜326的部份分離。凹部324的外周的一邊的長度例如為300μm~1000μm左右，凹部324的寬度例如為5μm~50μm左右。 The concave portion 324 is formed in a rectangular ring shape along the outer circumference of the circuit region. By the concave portion 324, the island-like portion of the metal film 326 covering the circuit region is separated from the portion of the metal film 326 which surrounds the island portion on the outer side thereof. The length of one side of the outer circumference of the concave portion 324 is, for example, about 300 μm to 1000 μm, and the width of the concave portion 324 is, for example, about 5 μm to 50 μm.
一實施形態中，遮罩300、308、320的凹部304、312、324可以形成為凹部的深度(亦即金屬膜的厚度)成為凹部的寬度的2倍至3倍。當凹部304、312、324採 取此種縱橫尺寸比時，具有易於使用既有之方法形成遮罩300、308、320的優點。 In one embodiment, the recesses 304, 312, and 324 of the masks 300, 308, and 320 may be formed such that the depth of the recess (that is, the thickness of the metal film) is two to three times the width of the recess. When the recesses 304, 312, 324 are taken When such an aspect ratio is taken, there is an advantage that it is easy to use the existing method to form the masks 300, 308, and 320.
第15圖係用於說明本發明的一實施形態之離子照射製程之圖。該離子照射製程中，為了以包圍元件區域206之方式形成高電阻層222，進行複數次離子照射。其中，元件區域206至少具備1個電路。使用同一遮罩212以不同之離子照射條件進行複數次離子照射。藉由複數次離子照射，在縱向不同之深度形成之複數個高電阻層222在橫向連接。 Fig. 15 is a view for explaining an ion irradiation process according to an embodiment of the present invention. In the ion irradiation process, in order to form the high resistance layer 222 so as to surround the element region 206, a plurality of ion irradiations are performed. Among them, the element region 206 has at least one circuit. Multiple ion irradiations were performed using the same mask 212 under different ion irradiation conditions. A plurality of high resistance layers 222 formed at different depths in the longitudinal direction are connected in the lateral direction by a plurality of ion irradiations.
第15圖所示之半導體基板200中，與第10圖所示之半導體基板200不同，非元件部份210的一部份抵達主面202。因此，形成於必要區域218之第1高電阻層226亦抵達主面202。第1高電阻層226形成於元件區域206的外周。並且，形成於不必要區域220之第2高電阻層228形成於元件區域206的背後。 In the semiconductor substrate 200 shown in Fig. 15, unlike the semiconductor substrate 200 shown in Fig. 10, a part of the non-element portion 210 reaches the main surface 202. Therefore, the first high resistance layer 226 formed in the necessary region 218 also reaches the main surface 202. The first high resistance layer 226 is formed on the outer circumference of the element region 206. Further, the second high resistance layer 228 formed in the unnecessary region 220 is formed behind the element region 206.
第2高電阻層228並非單純存在於非元件部份210，而係為了將元件區域206從來自其外部的噪聲屏蔽而與第1高電阻層226相同地使用。因此，必要區域218及不必要區域220亦能夠分別改稱為第1必要區域及第2必要區域。因此，遮罩212的開口部214與第1高電阻層226對應地形成於第1必要區域218，遮罩圖案216與第2高電阻層228對應地形成於第2必要區域220。 The second high resistance layer 228 is not simply present in the non-element portion 210, but is used in the same manner as the first high resistance layer 226 in order to shield the element region 206 from noise from the outside. Therefore, the necessary area 218 and the unnecessary area 220 can also be referred to as the first necessary area and the second necessary area, respectively. Therefore, the opening 214 of the mask 212 is formed in the first necessary region 218 corresponding to the first high resistance layer 226, and the mask pattern 216 is formed in the second necessary region 220 corresponding to the second high resistance layer 228.
第15圖中例示進行3次離子照射之情況。每次的離子照射從基板200的背面204進行。由於使用同一遮罩 212，因此連續依次進行複數次離子照射。每次的離子照射中之離子加速能以上方部份230、中間部份232及下方部份234相互在縱向連接之方式階段性地調整。例如，以第1次離子照射形成高電阻層222的上方部份230，以第2次離子照射形成高電阻層222的中間部份232，以第3次離子照射形成高電阻層222的下方部份234。此時，離子加速能在第1次照射時最大，第2次比第1次小，第3次最小。 Fig. 15 illustrates a case where ion irradiation is performed three times. Each ion irradiation is performed from the back surface 204 of the substrate 200. Due to the use of the same mask 212, therefore, multiple ion irradiations are sequentially performed in sequence. The ion acceleration in each ion irradiation can be adjusted stepwise in such a manner that the upper portion 230, the intermediate portion 232, and the lower portion 234 are longitudinally connected to each other. For example, the upper portion 230 of the high resistance layer 222 is formed by the first ion irradiation, the intermediate portion 232 of the high resistance layer 222 is formed by the second ion irradiation, and the lower portion of the high resistance layer 222 is formed by the third ion irradiation. 234. At this time, the ion acceleration energy is the largest at the time of the first irradiation, the second time is smaller than the first time, and the third time is the smallest.
藉由第3次離子照射，第1高電阻層226抵達第2高電阻層228的深度，第1高電阻層226與第2高電阻層228在橫向連接。在第15圖中，將第1高電阻層226與第2高電阻層228的連接部份以元件符號230表示。如此，形成包圍元件區域206的外周及背後之高電阻層222。由於能夠使用同一遮罩212來形成高電阻層222，因此處理輕鬆。 By the third ion irradiation, the first high resistance layer 226 reaches the depth of the second high resistance layer 228, and the first high resistance layer 226 and the second high resistance layer 228 are connected in the lateral direction. In Fig. 15, the connection portion between the first high resistance layer 226 and the second high resistance layer 228 is denoted by reference numeral 230. In this manner, the outer periphery and the high resistance layer 222 surrounding the element region 206 are formed. Since the same mask 212 can be used to form the high resistance layer 222, the processing is easy.
第16圖係用於說明本發明的一實施形態之離子照射製程之圖。此時，藉由第1次離子照射所形成之高電阻層I與藉由第2次離子照射所形成之高電阻層II分別使用不同的遮罩形成。第1次離子照射在元件區域206的外周與背後形成高電阻層I。但是，外周的高電阻層並未與背後的高電阻層相連。第1次的遮罩被去除，形成第2次的遮罩。第2次離子照射以連接高電阻層I的該2個部份之方式在元件區域206的外周在較深地位置形成高電阻層II。如此，還能夠形成包圍元件區域206的外周及背後之高電 阻層222。 Fig. 16 is a view for explaining an ion irradiation process according to an embodiment of the present invention. At this time, the high-resistance layer I formed by the first ion irradiation and the high-resistance layer II formed by the second ion irradiation are respectively formed using different masks. The first ion irradiation forms the high resistance layer I on the outer circumference and the back surface of the element region 206. However, the outer high resistance layer is not connected to the high resistance layer on the back. The first mask is removed to form a second mask. The second ion irradiation forms the high resistance layer II at a deep position on the outer periphery of the element region 206 so as to connect the two portions of the high resistance layer 1. In this way, it is also possible to form the outer circumference of the surrounding component region 206 and the high power behind it. Resistive layer 222.
另外，例如如第5圖及第6圖(b)所示那樣，使用半值幅較寬的離子種類時，能夠形成縱向較寬的高電阻層222，因此能夠以1次離子照射形成包圍元件區域206的外周及背後之高電阻層222。 Further, for example, as shown in FIG. 5 and FIG. 6(b), when an ion type having a wide half-value width is used, a high-resistance layer 222 having a wide longitudinal direction can be formed, so that the surrounding element can be formed by one-time ion irradiation. The outer perimeter of region 206 and the high resistance layer 222 behind it.
在有關本實施形態之半導體裝置的製造方法中，以將遮罩應用於基板來進行離子照射之簡單的方法，並不會對已形成的元件帶來實際影響就能夠在所需區域靈活地配置高電阻層。尤其，能夠輕易地形成包圍元件之具有三次元構造之高電阻層。在習知之方法中為了獲得該種結構，必需具備包括用於元件分離之溝槽製作或氧化膜的埋入等之複雜的多階段程序，相對於此，依本實施形態，可提供簡便且低成本的高電阻層形成方法。 In the method for manufacturing a semiconductor device according to the present embodiment, a simple method of applying a mask to a substrate for ion irradiation can be flexibly arranged in a desired region without actually affecting the formed element. High resistance layer. In particular, a high resistance layer having a three-element structure surrounding the element can be easily formed. In order to obtain such a structure, it is necessary to provide a complicated multi-stage program including trench formation for element separation or embedding of an oxide film. In contrast, according to this embodiment, it is simple and low. Cost high resistance layer formation method.
以上，參閱上述實施形態說明了本發明，但本發明並非限定於上述實施形態者，將實施形態的結構進行適當組合者或替換者亦係包含於本發明者。並且，亦能夠依本領域技術人員的知識，將對實施形態中之離子照射系統、加速器、晶圓傳送裝置等進行各種設計變更等之變形追加於實施形態，追加了該種變形之實施形態亦能夠包含於本發明的範圍中。 The present invention has been described above with reference to the above embodiments, but the present invention is not limited to the above-described embodiments, and those who appropriately combine the configurations of the embodiments are also included in the inventors. Further, in addition to the knowledge of those skilled in the art, various modifications such as various design changes in the ion irradiation system, the accelerator, and the wafer transfer apparatus in the embodiment can be added to the embodiment, and the embodiment in which the deformation is added is also added. It can be included in the scope of the invention.
上述實施形態中，遮罩212在基板200的表面(亦即主面202或背面204)上直接形成，但不限於此。一實施形態中，在基板200的表面與遮罩212之間可以設置有中間層(例如薄膜330，參閱第17圖)。該中間層可以為 用於保護基板200之層或膜。或者，中間層可以為用於提高遮罩材料(例如金屬)對基板200的黏附性之層或膜。中間層可以設置在基板200的整個表面上，亦可以設置在基板200的表面的局部(例如相當於遮罩圖案216之區域)。中間層不僅可以設置於形成遮罩212之基板200的單面，還可以設置於基板200的兩面。 In the above embodiment, the mask 212 is directly formed on the surface of the substrate 200 (that is, the main surface 202 or the back surface 204), but is not limited thereto. In one embodiment, an intermediate layer (eg, film 330, see FIG. 17) may be disposed between the surface of substrate 200 and mask 212. The middle layer can be A layer or film for protecting the substrate 200. Alternatively, the intermediate layer may be a layer or film for enhancing the adhesion of the mask material (eg, metal) to the substrate 200. The intermediate layer may be disposed on the entire surface of the substrate 200 or may be disposed on a portion of the surface of the substrate 200 (for example, an area corresponding to the mask pattern 216). The intermediate layer may be provided not only on one side of the substrate 200 forming the mask 212 but also on both sides of the substrate 200.
第17圖係表示本發明的一實施形態之遮罩212之圖。遮罩212具備用於保護基板200且提高遮罩材料(例如金屬)對基板200的黏附性之薄膜330。薄膜330形成於基板200的元件區域206上，薄膜330上形成有遮罩圖案216。薄膜330係能夠從基板200的表面剝離之薄膜。薄膜330例如為聚醯亞胺涂層或積層。因此，藉由將薄膜330從基板200的表面剝離，能夠輕鬆地從基板200去除遮罩212。如此藉由使薄膜330介於基板與遮罩之間，不對基板200的主面側進行研磨或磨削就能夠從主面202去除遮罩212。 Fig. 17 is a view showing a mask 212 according to an embodiment of the present invention. The mask 212 is provided with a film 330 for protecting the substrate 200 and improving the adhesion of the mask material (for example, metal) to the substrate 200. The film 330 is formed on the element region 206 of the substrate 200, and a mask pattern 216 is formed on the film 330. The film 330 is a film that can be peeled off from the surface of the substrate 200. The film 330 is, for example, a polyimide coating or a laminate. Therefore, the mask 212 can be easily removed from the substrate 200 by peeling the film 330 from the surface of the substrate 200. Thus, by interposing the film 330 between the substrate and the mask, the mask 212 can be removed from the main surface 202 without grinding or grinding the main surface side of the substrate 200.
一實施形態中，半導體基板可以在進行離子照射之製程之後，在非元件部份的第1區域中在第1深度具備第1高電阻層，在與第1區域不同之非元件部份的第2區域中在與第1深度不同之第2深度具備第2高電阻層。進行離子照射之製程中之離子照射條件可以規定為將第1高電阻層形成在第1深度。遮罩可以具備與第1高電阻層對應之第1遮罩區域、及與第2高電阻層對應之第2遮罩區域。在第1遮罩區域中，半導體基板的主面或背面可以露出。 第2遮罩區域可以以將第2高電阻層形成在第2深度之方式來規定遮罩厚度和/或遮罩材料。 In one embodiment, the semiconductor substrate may have a first high-resistance layer at a first depth and a non-element portion different from the first region in a first region of the non-element portion after the ion irradiation process. In the second region, the second high-resistance layer is provided at the second depth different from the first depth. The ion irradiation conditions in the process of performing ion irradiation may be defined as forming the first high resistance layer at the first depth. The mask may include a first mask region corresponding to the first high resistance layer and a second mask region corresponding to the second high resistance layer. In the first mask region, the main surface or the back surface of the semiconductor substrate can be exposed. The mask thickness and/or the mask material may be defined in the second mask region such that the second high resistance layer is formed at the second depth.
第1遮罩區域可以不具有遮罩的開口部而具有遮罩材料。遮罩可以具備遮罩厚度和/或遮罩材料與第1遮罩區域及第2遮罩區域不同之第3遮罩區域。各遮罩區域的厚度並非恆定，而可以在橫向改變。遮罩區域的邊界可以不為遮罩厚度的段差，在遮罩區域的邊界，遮罩厚度和/或遮罩材料可以連續改變。 The first mask region may have a mask material without an opening portion of the mask. The mask may have a third mask region having a mask thickness and/or a mask material different from the first mask region and the second mask region. The thickness of each mask area is not constant but can be changed in the lateral direction. The boundary of the mask region may not be the step width of the mask thickness, and the mask thickness and/or the mask material may be continuously changed at the boundary of the mask region.
一實施形態中，可以代替準備遮罩之製程，具備在半導體基板的主面或背面形成用於調整缺陷形成位置(例如自主面或背面的深度)之區域之製程。例如，藉由直接在基板的主面或背面形成(例如切削)凹部，能夠與使用遮罩的情況相同地選擇性地形成高電阻層。此時，被切削之凹部相當於遮罩的開口部，剩下之凸部相當於遮罩圖案。 In one embodiment, instead of the process of preparing the mask, a process for adjusting a region for forming a defect formation position (for example, a depth of the autonomous surface or the back surface) on the main surface or the back surface of the semiconductor substrate may be provided. For example, by forming (for example, cutting) the concave portion directly on the main surface or the back surface of the substrate, the high resistance layer can be selectively formed in the same manner as in the case of using the mask. At this time, the recessed portion to be cut corresponds to the opening portion of the mask, and the remaining convex portion corresponds to the mask pattern.
本發明用於半導體裝置的製造。 The invention is used in the manufacture of semiconductor devices.
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