JP7120475B2 - 半導体装置および車両 - Google Patents
半導体装置および車両 Download PDFInfo
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- JP7120475B2 JP7120475B2 JP2021569751A JP2021569751A JP7120475B2 JP 7120475 B2 JP7120475 B2 JP 7120475B2 JP 2021569751 A JP2021569751 A JP 2021569751A JP 2021569751 A JP2021569751 A JP 2021569751A JP 7120475 B2 JP7120475 B2 JP 7120475B2
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- circuit pattern
- main circuit
- slit
- semiconductor chip
- mounting portion
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Description
[先行技術文献]
[特許文献]
[特許文献1]特開2006-344770号公報
[特許文献2]特開2003-017627号公報
[特許文献3]特開2016-096188号公報
[特許文献4]特開2016-072281号公報
[特許文献5]特開平08-274423号公報
[特許文献6]特開平09-082844号公報
Claims (15)
- 第1半導体チップおよび第2半導体チップと、
回路基板と
を備える半導体装置であって、
前記回路基板は、上面と下面を有する絶縁板と、前記上面に設けられ、前記第1半導体チップおよび前記第2半導体チップを実装する回路層と、前記下面に設けられた金属層とを順に有する積層基板であって、平面視における形状が二組の対向する辺を有する矩形であり、
前記回路層は、前記第1半導体チップを実装する第1搭載部と、前記第2半導体チップを実装する第2搭載部と、前記第1搭載部および前記第2搭載部の間に設けられ、前記矩形の一組の辺が延びる第1方向に延伸する第1の上面スリットおよび第2の上面スリットと、を含み、
前記金属層は、前記第1方向に延びる第1の下面スリットを含み、
平面視において、前記第1搭載部、前記第1の上面スリット、前記第2の上面スリットおよび前記第2搭載部は前記矩形の他の一組の辺が延びる第2方向に並んで設けられ、前記第1の下面スリットは前記第1の上面スリットと前記第2の上面スリットとによって画定される範囲内に位置し、
前記回路基板は、前記半導体装置の加熱工程中に、前記第1搭載部および前記第2搭載部の位置が、前記絶縁板から前記金属層へ向かう方向に凸形状となるように熱変形する特性を有する、
半導体装置。 - 前記回路層は、それぞれが前記第1方向に延伸する、第1主回路パターン、第2主回路パターンおよび第3主回路パターンを含み、
前記第1主回路パターンは前記第1搭載部を含み、前記第2主回路パターンは前記第2搭載部を含み、
前記第1主回路パターン、前記第2主回路パターンおよび前記第3主回路パターンはそれぞれ、他の2つの主回路パターンに互いに隣接する、
請求項1に記載の半導体装置。 - 平面視において、前記第1主回路パターンは2つの長手部を含むU字形状であり、前記第2主回路パターンはI字形状であり、前記第3主回路パターンは1つの長手部を含むL字形状であり、前記第1主回路パターン、前記第2主回路パターンおよび前記第3主回路パターンは、前記矩形を形成するように位置する、
請求項2に記載の半導体装置。 - 前記回路層は、前記第1搭載部と前記第2搭載部との間に設けられ、前記第1方向に延伸する第3の上面スリットを更に含み、
前記第1の上面スリットは前記第1主回路パターンの前記2つの長手部の一方と前記第3主回路パターンの前記長手部との間に位置し、前記第2の上面スリットは前記第1主回路パターンの前記2つの長手部の他方と前記第2主回路パターンとの間に位置し、前記第3の上面スリットは前記第1主回路パターンの前記2つの長手部の他方と前記第3主回路パターンの前記長手部との間に位置する、
請求項3に記載の半導体装置。 - 第3半導体チップおよび第4半導体チップを更に備え、
前記第1主回路パターンは前記第3半導体チップを実装する第3搭載部を更に含み、
前記第2主回路パターンは前記第4半導体チップを実装する第4搭載部を更に含み、
前記第1搭載部および前記第3搭載部はそれぞれ、前記第1主回路パターンの前記2つの長手部の一方の両端に位置し、
前記第2搭載部および前記第4搭載部はそれぞれ、前記第2主回路パターンの前記I字形状の両端に位置する、
請求項3または4に記載の半導体装置。 - 前記回路層は、それぞれが前記第2方向に延伸する、第1制御回路パターン、第2制御回路パターン、第3制御回路パターン、第4制御回路パターン、3本の第4の上面スリット、および、3本の第5の上面スリットを更に含み、
前記第1搭載部、1本の前記第4の上面スリット、前記第1制御回路パターン、1本の前記第4の上面スリット、前記第3制御回路パターン、1本の前記第4の上面スリット、および、前記第3搭載部は前記第1方向に並んで設けられ、
前記第2搭載部、1本の前記第5の上面スリット、前記第2制御回路パターン、1本の前記第5の上面スリット、前記第4制御回路パターン、1本の前記第5の上面スリット、および、前記第4搭載部は前記第1方向に並んで設けられ、
前記金属層は、前記第2方向に延びる第2の下面スリットを更に含み、
平面視において、前記第2の下面スリットは、前記3本の第4の上面スリットによって画定される範囲内、および、前記3本の第5の上面スリットによって画定される範囲内に位置する、
請求項5に記載の半導体装置。 - 前記第1半導体チップおよび前記第1制御回路パターンを接続する制御配線、前記第3半導体チップおよび前記第3制御回路パターンを接続する制御配線、前記第2半導体チップおよび前記第2制御回路パターンを接続する制御配線、ならびに、前記第4半導体チップおよび前記第4制御回路パターンを接続する制御配線、を更に備え、
複数の前記制御配線の断面積および長さは、互いに等しい、
請求項6に記載の半導体装置。 - 前記第1半導体チップおよび前記第3主回路パターンを接続する主回路配線、前記第3半導体チップおよび前記第3主回路パターンを接続する主回路配線、前記第2半導体チップおよび前記第1主回路パターンを接続する主回路配線、ならびに、前記第4半導体チップおよび前記第1主回路パターンを接続する主回路配線、を更に備え、
複数の前記主回路配線の断面積および長さは、互いに等しい、
請求項6または7に記載の半導体装置。 - 前記回路層は、前記第2方向に延びる2本の第2方向スリットを含み、
前記金属層は、前記第2方向に延びる第2方向スリットを含み、
平面視において、前記金属層の前記第2方向スリットは、前記回路層の前記2本の第2方向スリットによって画定される範囲内に位置する、
請求項1から5のいずれか一項に記載の半導体装置。 - 平面視において、各搭載部に実装される半導体チップは、前記回路層および前記金属層が含む何れのスリットにも重ならない、
請求項1から9のいずれか一項に記載の半導体装置。 - 前記回路層および前記金属層は、同じ材料から形成される、
請求項1から10のいずれか一項に記載の半導体装置。 - 前記材料は、銅、銅合金、アルミニウム、および、アルミニウム合金の何れかを含む、
請求項11に記載の半導体装置。 - 前記回路層および前記金属層は、互いに同じ厚みを有する、
請求項1から12のいずれか一項に記載の半導体装置。 - 前記回路層および前記金属層が含む何れのスリットも、互いに同じ幅を有する、
請求項1から13のいずれか一項に記載の半導体装置。 - 請求項1から14のいずれか一項に記載の半導体装置を備える車両。
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