JP7111112B2 - 高周波モジュール - Google Patents
高周波モジュール Download PDFInfo
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- JP7111112B2 JP7111112B2 JP2019563970A JP2019563970A JP7111112B2 JP 7111112 B2 JP7111112 B2 JP 7111112B2 JP 2019563970 A JP2019563970 A JP 2019563970A JP 2019563970 A JP2019563970 A JP 2019563970A JP 7111112 B2 JP7111112 B2 JP 7111112B2
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- 239000004020 conductor Substances 0.000 claims description 66
- 229920005989 resin Polymers 0.000 claims description 52
- 239000011347 resin Substances 0.000 claims description 52
- 238000007789 sealing Methods 0.000 claims description 43
- 239000010410 layer Substances 0.000 description 46
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 7
- 229910052709 silver Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
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- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
- H05K9/002—Casings with localised screening
- H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
- H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0707—Shielding
- H05K2201/0715—Shielding provided by an outer layer of PCB
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本発明の第1実施形態にかかる高周波モジュール1aについて、図1~図3を参照して説明する。なお、図1は高周波モジュール1aの断面図、図2は高周波モジュール1aのシールド膜6の上面および封止樹脂層4を除いた状態の平面図、図3は図1の高周波モジュール1aのシールド壁の形状のパターンを示す図である。
上記した実施形態では、連結導体11は、ブロック状の金属により形成されていたが、例えば、図4および図5に示すモジュール1bのように、連結導体11aが一対の脚部14aと両脚部14aとをつなぐ橋絡部14bとを有するU字状に加工された金属ピンまたはワイヤーにより形成されていてもよい。両脚部14aは表層電極7に接続され、連結導体11aは多層配線基板2の上面20aに立設される。このようにすると、連結導体11aがU字状となっているため、連結導体11aの両脚部14aの間に配線電極を配置することができる。
本発明の第2実施形態にかかる高周波モジュール1dについて、図8および図9を参照して説明する。なお、図8は高周波モジュール1dの断面図、図9は高周波モジュール1dのシールド膜6の上面および封止樹脂層4を除いた状態の平面図である。
上記した実施形態では、3つのシールド壁50a、50b、50cと2つの連結導体11cとによりシールド50が形成されていたが、図10および図11に示す高周波モジュール1eのように、2つの溝12a、13aと1つの連結導体11dとにより屈曲部5a1、5b1を有するシールド51が形成されていてもよい。図8および図9に示す高周波モジュール1dにおけるシールド壁50cの位置には、溝およびシールド壁を形成せず、代わりに連結導体11dを配置することで、屈曲部5a1、5b1を有するシールド51を形成することができる。
本発明の第3実施形態にかかる高周波モジュール1fについて、図12および図13を参照して説明する。なお、図12は高周波モジュール1fの断面図、図13は高周波モジュール1fのシールド膜6の上面および封止樹脂層4を除いた状態の平面図である。
本発明の第4実施形態にかかる高周波モジュール1gについて、図14および図15を参照して説明する。なお、図14は高周波モジュール1gの断面図、図15は高周波モジュール1gのシールド膜6の上面および封止樹脂層4を除いた状態の平面図である。
図16に示す高周波モジュール1hのように、シールド54は、2つ以上のシールド壁と1つ以上の連結導体と、2つの端部導体とで構成されていてもよい。シールド54は、封止樹脂層4に形成された3つの溝12a、13a、15にCuやAgなどを主成分とする導電性ペーストを充填することにより配設された3つのシールド壁54a、54b、54cと2つの連結導体11cと2つの端部導体19a、19b(本発明の「第1端部導体」「第2端部導体」に相当する)とにより構成されている。
2 多層配線基板(配線基板)
3a,3b 部品(第1部品、第2部品)
3c 第3部品
4 封止樹脂層
5、50~54 シールド(シールド部材)
5a、5b、50a~50c、52a~52d、53a、54a~54c シールド壁
5a1、5b1 屈曲部
11、11a~11e 連結導体
12、13、12a、13a、15、16a~16d、 溝
17a、17b 端部導体(第3端部導体、第4端部導体)
19a、19b 端部導体(第1端部導体、第2端部導体)
40a 第1領域
40b 第2領域
Claims (4)
- 配線基板と、
前記配線基板の主面に実装された第1部品および第2部品と、
前記第1部品と前記第2部品との間に配置されたシールド部材と、
前記配線基板の前記主面に形成され、前記第1部品および前記第2部品を封止する封止樹脂層とを備え、
前記シールド部材は、
前記封止樹脂層に形成された第1の溝に配設される第1シールド壁と、
前記第1の溝から離れて前記封止樹脂層に形成された第2の溝に配設される第2シールド壁と、
前記配線基板の前記主面に配置され、前記第1シールド壁と前記第2シールド壁の一端同士を接続する連結導体とを備え、
前記封止樹脂層は、前記シールド部材により前記第1部品を封止する第1領域と前記第2部品を封止する第2領域とに分けられ、前記連結導体の位置で前記第1領域と前記第2領域とが繋がっており、
前記連結導体は、一端が前記配線基板の前記主面に接続された状態で、前記主面に立設された一対の脚部と、前記一対の脚部の他端同士をつなぐ橋絡部とを有していることを特徴とする高周波モジュール。 - 前記連結導体の前記一対の脚部の間に、第3部品または配線電極が配置され、前記連結導体が前記第3部品または前記配線電極を跨ぐように配置されていることを特徴とする請求項1に記載の高周波モジュール。
- 前記配線基板の前記主面に対して垂直な方向から見たときに、前記シールド部材が屈曲部を有し、前記連結導体が前記屈曲部に配置されていることを特徴とする請求項1または2に記載の高周波モジュール。
- 前記配線基板の前記主面の端縁に配置され、前記第1シールド壁の他端に接続される第1端部導体と、
前記配線基板の前記主面の端縁に配置され、前記第2シールド壁の他端に接続される第2端部導体とをさらに備えることを特徴とする請求項1ないし3のいずれか1項に記載の高周波モジュール。
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JP2021196621A JP7334774B2 (ja) | 2018-01-05 | 2021-12-03 | 高周波モジュール |
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PCT/JP2018/047707 WO2019135376A1 (ja) | 2018-01-05 | 2018-12-26 | 高周波モジュール |
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US (1) | US11297746B2 (ja) |
JP (2) | JP7111112B2 (ja) |
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US12055633B2 (en) * | 2020-08-25 | 2024-08-06 | Lumentum Operations Llc | Package for a time of flight device |
WO2022102588A1 (ja) * | 2020-11-12 | 2022-05-19 | 株式会社村田製作所 | 電子部品モジュール |
CN112234047B (zh) * | 2020-12-14 | 2021-02-26 | 甬矽电子(宁波)股份有限公司 | 分层电磁屏蔽封装结构和封装结构制作方法 |
EP4040483A3 (en) * | 2021-02-04 | 2022-10-26 | Murata Manufacturing Co., Ltd. | Electronic component with internal shielding |
CN114242654B (zh) * | 2022-02-23 | 2022-05-13 | 威海嘉瑞光电科技股份有限公司 | 一种无引线磁性封装结构及其制造方法 |
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US20140231972A1 (en) | 2013-02-21 | 2014-08-21 | Siliconware Precision Industries Co., Ltd. | Multi-chip package and method for manufacturing the same |
JP2014203881A (ja) | 2013-04-02 | 2014-10-27 | 太陽誘電株式会社 | 回路モジュール及びその製造方法 |
CN104347533A (zh) | 2013-08-01 | 2015-02-11 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
JP2015057803A (ja) | 2013-08-09 | 2015-03-26 | 太陽誘電株式会社 | 回路モジュールの製造方法 |
WO2016181954A1 (ja) | 2015-05-11 | 2016-11-17 | 株式会社村田製作所 | 高周波モジュール |
WO2016195026A1 (ja) | 2015-06-04 | 2016-12-08 | 株式会社村田製作所 | 高周波モジュール |
WO2017047539A1 (ja) | 2015-09-14 | 2017-03-23 | 株式会社村田製作所 | 高周波モジュール |
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