JP7104448B2 - 二値化アルゴリズムに基づくアクセラレーション制御システム、チップ及びロボット - Google Patents

二値化アルゴリズムに基づくアクセラレーション制御システム、チップ及びロボット Download PDF

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JP7104448B2
JP7104448B2 JP2021507739A JP2021507739A JP7104448B2 JP 7104448 B2 JP7104448 B2 JP 7104448B2 JP 2021507739 A JP2021507739 A JP 2021507739A JP 2021507739 A JP2021507739 A JP 2021507739A JP 7104448 B2 JP7104448 B2 JP 7104448B2
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burst
state
read
binarized
state machine
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JP2021536051A (ja
JPWO2020034500A5 (https=
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再生 何
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Zhuhai Amicro Semiconductor Co Ltd
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Zhuhai Amicro Semiconductor Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/20—Image preprocessing
    • G06V10/28—Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/94—Hardware or software architectures specially adapted for image or video understanding
    • G06V10/955—Hardware or software architectures specially adapted for image or video understanding using specific electronic processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V20/00—Scenes; Scene-specific elements
    • G06V20/10—Terrestrial scenes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Advance Control (AREA)
JP2021507739A 2018-08-14 2018-12-07 二値化アルゴリズムに基づくアクセラレーション制御システム、チップ及びロボット Active JP7104448B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201810920821.5 2018-08-14
CN201810920821.5A CN108984442B (zh) 2018-08-14 2018-08-14 一种基于二值化算法的加速控制系统、芯片及机器人
PCT/CN2018/119916 WO2020034500A1 (zh) 2018-08-14 2018-12-07 一种基于二值化算法的加速控制系统、芯片及机器人

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JP2021536051A JP2021536051A (ja) 2021-12-23
JPWO2020034500A5 JPWO2020034500A5 (https=) 2022-06-22
JP2021536051A5 JP2021536051A5 (https=) 2022-06-22
JP7104448B2 true JP7104448B2 (ja) 2022-07-21

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US (1) US11269796B2 (https=)
EP (1) EP3839754B1 (https=)
JP (1) JP7104448B2 (https=)
KR (1) KR102520983B1 (https=)
CN (1) CN108984442B (https=)
WO (1) WO2020034500A1 (https=)

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CN109857702B (zh) * 2019-04-18 2023-02-17 珠海一微半导体股份有限公司 一种基于机器人的激光雷达数据读写控制系统及芯片
CN111193873B (zh) * 2019-12-25 2021-07-20 新大陆数字技术股份有限公司 一种图像快速调光系统及方法
CN111679286B (zh) * 2020-05-12 2022-10-14 珠海一微半导体股份有限公司 一种基于硬件加速的激光定位系统及芯片
CN114442908B (zh) * 2020-11-05 2023-08-11 珠海一微半导体股份有限公司 一种用于数据处理的硬件加速系统及芯片
CN112416823B (zh) * 2020-11-15 2024-05-03 珠海一微半导体股份有限公司 一种突发模式下的传感器数据读写控制方法、系统及芯片
CN112631658B (zh) * 2021-01-13 2022-11-15 成都国科微电子有限公司 指令发送方法、芯片和电子设备
CN113112393B (zh) * 2021-03-04 2022-05-31 浙江欣奕华智能科技有限公司 视觉导航系统中的边缘化装置
CN114415951B (zh) * 2022-01-04 2024-04-05 杭州中天微系统有限公司 图像数据访存单元、方法、加速单元及电子设备
CN116506656B (zh) * 2023-04-27 2026-01-02 武汉中观自动化科技有限公司 一种基于fpga的视频数据突发传输方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005032019A (ja) 2003-07-04 2005-02-03 Nec Micro Systems Ltd Ａｍｂａにおけるバス調停システム
JP2006154897A (ja) 2004-11-25 2006-06-15 Oki Electric Ind Co Ltd Ｄｒａｍコントローラ
JP2007532066A (ja) 2004-03-31 2007-11-08 シリコン ラボラトリーズ インコーポレーテッド 制限されたバス・アクセスを伴う時間領域分離を実装する通信装置
JP2009200968A (ja) 2008-02-22 2009-09-03 Canon Inc 画像処理装置及びその制御方法
JP2009205412A (ja) 2008-02-27 2009-09-10 Toshiba Corp Ｄｒａｍコントローラおよびメモリシステム

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4143302B2 (ja) * 2002-01-15 2008-09-03 キヤノン株式会社 画像処理装置、画像処理方法、制御プログラム及び記録媒体
US7443526B2 (en) * 2003-07-07 2008-10-28 Kabushiki Kaisha Toshiba Multi-function image processing apparatus and method
JP4313130B2 (ja) * 2003-09-18 2009-08-12 株式会社リコー 画像形成装置、画像形成方法、およびその方法をコンピュータで実行するプログラム
CN101359225B (zh) * 2008-08-29 2010-10-06 北京大学 一种多水下机器人协作控制系统
CN101567078B (zh) 2009-03-27 2011-06-22 西安交通大学 一种双总线的视觉处理芯片架构
CN102207920B (zh) * 2010-03-30 2013-12-04 比亚迪股份有限公司 一种bvci总线到ahb总线的转换桥
US10061537B2 (en) 2015-08-13 2018-08-28 Microsoft Technology Licensing, Llc Data reordering using buffers and memory
CN105573951B (zh) * 2015-12-24 2018-02-09 哈尔滨理工大学 一种针对数据流传输的ahb总线接口系统
CN107577636A (zh) * 2017-09-12 2018-01-12 天津津航技术物理研究所 一种基于soc的axi总线接口数据传输系统及传输方法
CN108161938A (zh) 2017-12-27 2018-06-15 华南智能机器人创新研究院 一种机器人中的视觉跟踪方法及系统
CN211403419U (zh) * 2018-08-14 2020-09-01 珠海市一微半导体有限公司 基于二值化算法的加速控制系统、芯片及机器人
TWI726525B (zh) * 2019-12-09 2021-05-01 新唐科技股份有限公司 影像二值化方法與電子裝置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005032019A (ja) 2003-07-04 2005-02-03 Nec Micro Systems Ltd Ａｍｂａにおけるバス調停システム
JP2007532066A (ja) 2004-03-31 2007-11-08 シリコン ラボラトリーズ インコーポレーテッド 制限されたバス・アクセスを伴う時間領域分離を実装する通信装置
JP2006154897A (ja) 2004-11-25 2006-06-15 Oki Electric Ind Co Ltd Ｄｒａｍコントローラ
JP2009200968A (ja) 2008-02-22 2009-09-03 Canon Inc 画像処理装置及びその制御方法
JP2009205412A (ja) 2008-02-27 2009-09-10 Toshiba Corp Ｄｒａｍコントローラおよびメモリシステム

Also Published As

Publication number Publication date
JP2021536051A (ja) 2021-12-23
EP3839754C0 (en) 2023-08-23
KR20210042978A (ko) 2021-04-20
US11269796B2 (en) 2022-03-08
EP3839754A4 (en) 2022-05-11
WO2020034500A1 (zh) 2020-02-20
CN108984442B (zh) 2023-08-18
US20210311894A1 (en) 2021-10-07
KR102520983B1 (ko) 2023-04-12
EP3839754A1 (en) 2021-06-23
EP3839754B1 (en) 2023-08-23
CN108984442A (zh) 2018-12-11

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