JP7092865B2 - ウェアレベリング - Google Patents
ウェアレベリング Download PDFInfo
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- JP7092865B2 JP7092865B2 JP2020505215A JP2020505215A JP7092865B2 JP 7092865 B2 JP7092865 B2 JP 7092865B2 JP 2020505215 A JP2020505215 A JP 2020505215A JP 2020505215 A JP2020505215 A JP 2020505215A JP 7092865 B2 JP7092865 B2 JP 7092865B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0665—Virtualisation aspects at area level, e.g. provisioning of virtual or logical volumes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
- G11C14/0027—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell and the nonvolatile element is a ferroelectric element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
Claims (9)
- 装置の動作方法であって、
ウェアレベリングされることになるメモリアレイの最後にアクセスされた部分を、前記部分がアクセスされる頻度、またはアクセスされることになる頻度に基づいて、レジスタにおいて指定されたアドレスに基づいて選択すること、及び
前記最後にアクセスされた部分専用の個別のアドレス変換テーブルの論理アドレスを、使用中のメモリセルのグループの物理アドレスからスペアのメモリセルのグループの物理アドレスに再マッピングすることにより、前記最後にアクセスされた部分に排他的な複数の使用中のグループの内のメモリセルの使用中のグループを、前記最後にアクセスされた部分に排他的なスペアのメモリセルのグループに置き換えることによって前記最後にアクセスされた部分をウェアレベリングすること
を含む前記方法。 - メモリセルのアレイの第1の部分と、
メモリセルの前記アレイの第2の部分と、
前記第1の部分に対応する、コントローラの第1のレジスタと、
前記第2の部分に対応する、前記コントローラの第2のレジスタと、を備え、
前記第1のレジスタは、前記第1の部分がアクセスされる頻度、またはアクセスされることになる頻度に基づいて、前記第1の部分がウェアレベリングされるために選択されたことを示す第1の状態に設定されるように構成され、
前記第2のレジスタは、前記第1のレジスタが前記第1の状態に設定されている間に、前記第2の部分がアクセスされる頻度、またはアクセスされることになる頻度に基づいて、前記第2の部分がウェアレベリングされるために選択されたことを示す前記第1の状態に設定されるように構成され、
前記コントローラは、2つの状態のうちの前記第1の状態に設定された、前記コントローラ内の前記第1のレジスタ及び前記第2のレジスタに少なくとも一部が基づいて、前記アレイのどの部分がウェアレベリングされるかを、メモリセルの前記アレイにアクセスする前に識別するように構成されている、
メモリ装置。 - 前記第1のレジスタは、前記第1の部分が特定の回数以上アクセスされることに応答して、前記第1の状態に設定されるように構成されている、請求項2に記載のメモリ装置。
- 前記第1の部分と前記第2の部分とは、互いに独立してウェアレベリングされる、請求項2に記載のメモリ装置。
- 前記メモリ装置は、前記第1の部分が前記第1の状態に設定される場合にのみ、前記第1の部分をウェアレベリングする、請求項2に記載のメモリ装置。
- メモリ装置であって、
複数の部分を備えるメモリアレイと、
前記複数の部分のうちの最後にアクセスされた部分のアドレスを格納するレジスタと、
各部分それぞれに専用のそれぞれのアドレス変換テーブルと、を備え、
前記メモリ装置は、前記アドレスが前記レジスタ内に格納された後に受け取られたコマンドに応答して、前記最後にアクセスされた部分をウェアレベリングするように構成され、
前記メモリ装置は、複数の使用中グループのうちの使用中メモリセルグループの物理アドレスからスペアメモリセルグループの物理アドレスに、それぞれの前記アドレス変換テーブルの論理アドレスを再マッピングすることにより、前記最後にアクセスされた部分に専用の前記使用中メモリセルグループを、前記最後にアクセスされた部分に専用の前記スペアメモリセルグループで置き換えることによって、前記最後にアクセスされた部分をウェアレベリングするように構成されている、
メモリ装置。 - 前記最後にアクセスされた部分は、前記アドレスが前記レジスタに格納された後に受け取られるコマンドに応答して、前記複数の部分の他の部分に先立って最初にウェアレベリングされる前記複数の部分の部分であり、前記コマンドは、前記最後にアクセスされた部分の前記アドレスが格納された後に受け取られる次のウェアレベリングコマンドまたは次のリフレッシュコマンドである、請求項6に記載のメモリ装置。
- ホストと、
前記ホストに結合され、メモリセルのアレイの複数の部分を備えるメモリと、を備え、
前記メモリは、前記ホストからのコマンドに応答して、ウェアレベリングするために前記複数の部分のうちの最後にアクセスされた部分を選択すること、及び
前記最後にアクセスされた部分専用の個別のアドレス変換テーブルの論理アドレスを、
使用中のメモリセルのグループの物理アドレスからスペアのメモリセルのグループの物理アドレスに再マッピングすることにより、前記最後にアクセスされた部分に排他的な複数の使用中のグループの内のメモリセルの使用中のグループを、前記最後にアクセスされた部分に排他的なスペアのメモリセルのグループに置き換えることによって前記アレイの選択された前記最後にアクセスされた部分のウェアレベリングを実行すること
をするように構成されている、
メモリ装置。 - 前記コマンドは、ウェアレベリングコマンドまたはリフレッシュコマンドである、請求項8に記載のメモリ装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/669,290 | 2017-08-04 | ||
US15/669,290 US10198195B1 (en) | 2017-08-04 | 2017-08-04 | Wear leveling |
PCT/US2018/043414 WO2019027727A1 (en) | 2017-08-04 | 2018-07-24 | LEVEL OF WEAR |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020529665A JP2020529665A (ja) | 2020-10-08 |
JP7092865B2 true JP7092865B2 (ja) | 2022-06-28 |
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Application Number | Title | Priority Date | Filing Date |
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JP2020505215A Active JP7092865B2 (ja) | 2017-08-04 | 2018-07-24 | ウェアレベリング |
Country Status (7)
Country | Link |
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US (4) | US10198195B1 (ja) |
EP (1) | EP3662374A4 (ja) |
JP (1) | JP7092865B2 (ja) |
KR (1) | KR20200012026A (ja) |
CN (1) | CN110998543B (ja) |
TW (1) | TWI672588B (ja) |
WO (1) | WO2019027727A1 (ja) |
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US11551990B2 (en) * | 2017-08-11 | 2023-01-10 | Advanced Micro Devices, Inc. | Method and apparatus for providing thermal wear leveling |
US20200081628A1 (en) * | 2018-09-12 | 2020-03-12 | Dell Products, Lp | Apparatus and Method for Monitoring Insertion and Removal of Devices |
US11422826B2 (en) | 2020-05-19 | 2022-08-23 | Micron Technology, Inc. | Operational code storage for an on-die microprocessor |
WO2022011683A1 (en) * | 2020-07-17 | 2022-01-20 | Micron Technology, Inc. | Storage of video data and file system metadata |
KR20220127067A (ko) * | 2021-03-10 | 2022-09-19 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
US11875836B2 (en) * | 2021-06-04 | 2024-01-16 | Kepler Computing Inc. | Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing |
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2017
- 2017-08-04 US US15/669,290 patent/US10198195B1/en active Active
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2018
- 2018-07-24 WO PCT/US2018/043414 patent/WO2019027727A1/en unknown
- 2018-07-24 CN CN201880050879.7A patent/CN110998543B/zh active Active
- 2018-07-24 KR KR1020207002041A patent/KR20200012026A/ko active IP Right Grant
- 2018-07-24 EP EP18840254.9A patent/EP3662374A4/en not_active Withdrawn
- 2018-07-24 JP JP2020505215A patent/JP7092865B2/ja active Active
- 2018-08-03 TW TW107127044A patent/TWI672588B/zh active
- 2018-08-14 US US16/102,807 patent/US10416903B2/en active Active
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2019
- 2019-07-12 US US16/510,236 patent/US10585597B2/en active Active
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2020
- 2020-01-27 US US16/752,959 patent/US11003361B2/en active Active
Patent Citations (6)
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KR20200012026A (ko) | 2020-02-04 |
US20190332281A1 (en) | 2019-10-31 |
US11003361B2 (en) | 2021-05-11 |
US20190042107A1 (en) | 2019-02-07 |
TW201911052A (zh) | 2019-03-16 |
US10198195B1 (en) | 2019-02-05 |
CN110998543A (zh) | 2020-04-10 |
JP2020529665A (ja) | 2020-10-08 |
US10416903B2 (en) | 2019-09-17 |
CN110998543B (zh) | 2023-11-10 |
US20200159420A1 (en) | 2020-05-21 |
US10585597B2 (en) | 2020-03-10 |
US20190042109A1 (en) | 2019-02-07 |
TWI672588B (zh) | 2019-09-21 |
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