JP7028192B2 - Display device and projection type display device - Google Patents

Description

The present disclosure relates to, for example, a display device used as an optical modulation device and a projection type display device including the display device.

In recent years, projection-type liquid crystal displays (LCDs) that project images onto screens have been widely used not only in offices but also at home. A projection type liquid crystal display device (liquid crystal projector) generates image light by modulating light from a light source with a light valve and projects it on a screen for display. The light bulb (optical modulation device) is composed of a liquid crystal panel, and for example, each pixel is driven by an active matrix in response to a video signal from the outside to modulate light.

There is a high demand for high brightness in liquid crystal panels, and it is required to improve the aperture ratio of pixels. However, improving the aperture ratio will reduce the light-shielding area of the TFT. When light hits the PN junction (specifically, LDD; Lightly Doped Drain) of the TFT due to the decrease in the light-shielding area, a light leakage current is generated, and the leakage current causes deterioration of image quality such as flicker.

On the other hand, for example, in Patent Documents 1 and 2, a pair of grooves are provided on both sides of the semiconductor layer, and a light-shielding layer is provided in the grooves to improve the light-shielding property of the semiconductor layer and suppress the generation of leakage current. The electro-optic device (display device) is disclosed. Further, Patent Document 3 discloses an electro-optic device in which an optical surface is formed between an open region and a non-open region to guide light that is about to deviate from the open region to the open region.

Japanese Unexamined Patent Publication No. 2008-191200 Japanese Unexamined Patent Publication No. 2004-158518 Japanese Unexamined Patent Publication No. 2002-913339

As described above, the aperture ratio and the light-shielding property are basically in a trade-off relationship, but the liquid crystal panel is required to have both high brightness and improved image quality.

It is desirable to provide a display device and a projection type display device capable of achieving both high brightness and improvement of image quality.

The display device of one embodiment of the present disclosure includes a first substrate and a second substrate having liquid crystal layers arranged so as to face each other, and the first substrate is provided on a support substrate and a plurality of the support substrates and intersect with each other. The TFTs are provided at the intersections of the scanning lines and the plurality of signal lines, and the plurality of scanning lines and the plurality of signal lines , respectively, and the semiconductor layer and the gate electrode are laminated in this order from the support substrate side via the insulating film, respectively. It is formed of an element and a conductive material, and has a light-shielding film provided along a plurality of scanning lines in a plan view, and has a plurality of scanning lines, a plurality of scanning lines, and a plurality of signals. The insulating films provided at the intersections with the wires have the same end face, and the light-shielding film extends to the same end face .

The projection type display device of one embodiment of the present disclosure has a light modulation device that modulates light from a light source, and is provided with the display device of the above-mentioned embodiment of the present disclosure as a light modulation device.

In the display device of one embodiment and the projection type display device of one embodiment of the present disclosure, a material having conductivity along a plurality of scanning lines provided on a support substrate constituting the first substrate in a plan view. A light-shielding film containing the above was formed. This makes it possible to improve the light-shielding property of the TFT element provided for each pixel without restricting the opening of the pixel.

According to the display device of one embodiment and the projection type display device of one embodiment of the present disclosure, a light-shielding film having conductivity is formed along a plurality of scanning lines in a plan view, so that the pixels can be formed. The light-shielding property of the TFT element is improved without limiting the aperture ratio. Therefore, it is possible to achieve both high brightness and improved image quality.

The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a plan view of the liquid crystal panel which concerns on 1st Embodiment of this disclosure. It is a schematic cross-sectional view of the whole of the liquid crystal panel shown in FIG. It is a schematic diagram which shows the cross section of the drive board which constitutes the liquid crystal panel in the II line shown in FIG. It is a schematic diagram which shows the cross section of the drive substrate which constitutes the liquid crystal panel in the II-II line shown in FIG. It is a schematic diagram which shows the cross section of the drive substrate which constitutes the liquid crystal panel in the line III-III shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the drive substrate which comprises the liquid crystal panel shown in FIG. It is sectional drawing which shows the process following FIG. 6A. It is sectional drawing which shows the process following FIG. 6B. It is sectional drawing which shows the process following FIG. 6C. It is sectional drawing which shows the process following FIG. 6D. It is a schematic diagram which shows the positional relationship of a scanning line, a gate electrode and a through hole. It is a figure which shows an example of the structure of the display device provided with the liquid crystal panel of this disclosure. It is a figure which shows an example of the structure of a spatial light modulation part. It is a figure which shows an example of the circuit structure of a pixel. It is a schematic diagram which shows the cross section of the drive substrate which comprises the liquid crystal panel which concerns on the 2nd Embodiment of this disclosure. It is sectional drawing for demonstrating the manufacturing method of the drive board shown in FIG. It is a schematic diagram which shows the cross section of the drive board which comprises the liquid crystal panel which concerns on 3rd Embodiment of this disclosure. It is sectional drawing for demonstrating the manufacturing method of the drive board shown in FIG. It is sectional drawing which shows the process following FIG. 14A. FIG. 3 is a schematic plan view of a drive board constituting the liquid crystal panel according to the first modification of the present disclosure. It is a schematic diagram which shows the cross section of the drive board in the IV-IV line shown in FIG. FIG. 3 is a schematic plan view of a drive board constituting the liquid crystal panel according to the second modification of the present disclosure. It is a schematic diagram which shows the cross section of the drive board in the VV line shown in FIG. It is a plan view of the drive board which comprises the liquid crystal panel which concerns on 4th Embodiment of this disclosure. It is a schematic diagram which shows the cross section of the drive board in the VI-VI line shown in FIG. It is sectional drawing for demonstrating the manufacturing method of the drive board shown in FIG. It is sectional drawing which shows the process following FIG. 21A. It is sectional drawing which shows the process following FIG. 21B. It is a schematic diagram which shows the cross section of the drive board which constitutes the liquid crystal panel which concerns on the modification 3 of this disclosure. It is a plan view of the drive board which constitutes the liquid crystal panel which concerns on the modification 4 of this disclosure. It is a schematic diagram which shows the cross section of the drive board in the VII-VII line shown in FIG. 23.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The explanation will be given in the following order. The following description is a specific example of the present disclosure, and the present disclosure is not limited to the following aspects. Further, the present disclosure is not limited to the arrangement, dimensions, dimensional ratio, etc. of each component shown in each figure.
1. 1. First embodiment (an example in which a light-shielding film is formed along a scanning line in a plan view)
1-1. Liquid crystal panel configuration 1-2. Manufacturing method of drive board 1-3. Overall configuration of projection type display device 1-4. Action / effect 2. Second embodiment (an example in which a light-shielding film is also formed above the transistor)
3. 3. Third embodiment (example of forming through holes and separating scanning lines at once)
4. Modification 1 (Example of directly connecting the scanning line and the gate electrode)
5. Modification 2 (Example of supplying a potential to the gate electrode outside the effective pixel region)
6. Fourth Embodiment (Example of forming a light-shielding film and an opening after forming the first wiring)
7. Modification 3 (Example of forming a light-shielding film and an opening after forming the third wiring)
8. Modification 4 (Example of bottom gate type transistor)

<1. First Embodiment>
FIG. 1 schematically shows a planar configuration of a display device (liquid crystal panel 1) according to the first embodiment of the present disclosure. FIG. 2 schematically shows the cross-sectional structure of the entire liquid crystal panel 1 shown in FIG. The liquid crystal panel 1 has a pixel region 1A in which a plurality of pixels P are arranged in a matrix and a peripheral region 1B around the pixel region 1A (see FIG. 9). For example, a projection type display device (projector 100, see FIG. 8). ) Is used as an optical modulator (spatial optical modulator 130). In the liquid crystal panel 1, the drive substrate 40A (first substrate) and the facing substrate 50 (second substrate) are arranged to face each other with the liquid crystal cell 60 (liquid crystal layer) in between. The liquid crystal panel 1 of the present embodiment has a configuration in which a light-shielding film 15 having conductivity is provided along a plurality of scanning lines WSL provided on the drive substrate 40A in a plan view.

In addition, "along the scanning line WSL" is provided on the scanning line WSL or in contact with the end face of the scanning line WSL, and another layer (for example, for example) between the scanning line WSL and the light-shielding film 15 is used. This includes the case where the insulating film 12) is present. In this embodiment, an example in which the light-shielding film 15 is provided on the scanning line WSL is shown.

(1-1. Configuration of liquid crystal panel)
As described above, the liquid crystal panel 1 has a liquid crystal cell 60 between the drive substrate 40A arranged to face each other and the facing substrate 50. The liquid crystal cell 60 is provided with alignment films 61 and 62 on the drive substrate 40A side and the facing substrate 50 side, respectively, and the peripheral edge of the liquid crystal cell 60 is sealed by a sealing material 63. Polarizing plates 42 and 52 are provided on the surfaces (surface S2 side and surface S1 side) of the drive substrate 40A and the facing substrate 50 opposite to the liquid crystal cell 60, respectively.

FIG. 3 schematically shows a cross-sectional configuration of a drive substrate 40A in two adjacent pixels P including a pixel transistor 13 in the I-I line shown in FIG. 1. FIG. 4 schematically shows the cross-sectional configuration of the drive substrate 40A in the line II-II shown in FIG. FIG. 5 schematically shows the cross-sectional structure of the drive substrate 40A on the lines III-III. The drive substrate 40A is provided with a plurality of scanning lines WSL and a plurality of signal lines DTL extending in the X-axis direction and the Y-axis direction, respectively, and intersecting each other. The drive substrate 40A has an opening region X that reflects or transmits incident light and a non-opening region Y provided around the opening region X, and a plurality of scans intersecting each other in the non-opening region Y. A line WSL, a plurality of signal line DTLs, and a pixel transistor 13 described later are provided. The drive substrate 40A is provided with, for example, a TFT layer 10 provided with a pixel transistor 13 (TFT element) or the like and various wirings (wiring layers 21, 22, 23) on the support substrate 41 (surface S1 side). The multilayer wiring layer 20 and the pixel electrodes 31 are laminated in this order.

The TFT layer 10 is provided with, for example, a plurality of scanning lines WSL on the support substrate 41 and a pixel transistor 13 on each scanning line WSL via an insulating film 12, and insulation is provided on the pixel transistor 13. A film 14 is provided. Each pixel transistor 13 is formed so as to be separated from each pixel P by a through hole H (see FIG. 6B). The through hole H is formed, for example, along the formation region of a plurality of scanning lines WSL in a plan view, and the bottom surface thereof reaches to the support substrate 41. In this embodiment, although details will be described later, a light-shielding film 15 is formed on the side surface (surface S3) of the through hole H including the side surface of the pixel transistor 13 in the stacking direction (Z-axis direction). Irradiation of the obliquely incident light to the pixel transistor 13 is efficiently reduced. A flattening layer 16 is provided between the pixel transistors 13, and the through hole H is embedded by the flattening layer 16. The multilayer wiring layer 20 is provided on the TFT layer 10, and includes wirings constituting, for example, a signal line DTL and a common connection line COM (not shown) between the interlayer insulating layers 26, 21 and 22,. 23 are provided in this order.

The support substrate 41 is, for example, a quartz substrate, and has, for example, a rectangular surface shape (a surface shape parallel to the display screen).

The scanning line WSL extends, for example, in the X-axis direction, and a part thereof extends in the Y-axis direction. Specifically, the scanning line WSL extends directly below (opposing region) the LDD region (LDD region 13c) of the pixel transistor 13 and its periphery. The scanning line WSL is composed of, for example, a metal film such as tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr) and tantalum (Ta), or an alloy film thereof. The film thickness of the scanning line WSL in the Z-axis direction (hereinafter, simply referred to as thickness) is, for example, 10 nm or more and 500 nm or less.

The insulating films 12 and 14 are composed of, for example, a silicon oxide (SiO ₂ ) film, a silicon nitride (Si ₃ N ₄ ) film, or a laminated film thereof. The insulating film 12 is provided on the scanning line WSL, and the pixel transistor 13 is provided on the insulating film 12. The insulating film 14 is provided so as to cover the gate insulating film 13B and the gate electrode 13C of the pixel transistor 13. The thickness of the insulating film 12 is, for example, 50 nm or more and 1 μm or less. The thickness of the insulating film 14 is, for example, 100 nm or more and 1 μm or less.

The pixel transistor 13 has an LDD (Lightly Doped Drain) structure. The pixel transistor 13 has a semiconductor layer 13A, a gate electrode 13C that applies an electric field to the semiconductor layer 13A (particularly, a channel region 13a), and a gate insulating film 13B that insulates and separates the semiconductor layer 13A and the gate electrode 13C from each other. is doing. The semiconductor layer 13A has a channel region 13a at a position facing the gate electrode 13C, an LDD region 13c provided on both sides of the channel region 13a, and a source / drain region further outside the LDD region 13c, respectively. It has 13b. In the present embodiment, in the pixel transistor 13, the gate electrode 13C is electrically connected to the scanning line WSL via the light shielding film 15, one source / drain region 13b is electrically connected to the signal line DTL, and the other. The source / drain region 13b of the above is electrically connected to the pixel electrode 31.

As described above, the channel region 13a, the source / drain region 13b, and the LDD region 13c are both formed in, for example, the same layer (semiconductor layer 13A), and are, for example, an amorphous silicon film or a polycrystalline silicon film. It is composed of such things. When the semiconductor layer 13A is made of a polysilicon film, the source / drain region 13b is doped with impurities such as n-type impurities to reduce the resistance. The LDD region 13c is doped with impurities so that the impurity concentration is lower than that of the source / drain region 13b.

The gate insulating film 13B is for electrically insulating the semiconductor layer 13A and the gate electrode 13C. The gate insulating film 13B is composed of, for example, a silicon oxide film or a silicon nitride film, and is formed by, for example, a thermal oxidation method or a CVD (Chemical Vapor Deposition) method.

The gate electrode 13C is provided so as to straddle the semiconductor layer 13A in the X-axis direction via the gate insulating film 13B. In the semiconductor layer 13A, the region facing the gate electrode 13C is the channel region 13a. The gate electrode 13C is made of a conductive material. Specifically, it is composed of, for example, an amorphous silicon film, a polycrystalline silicon film, a metal film such as W, Ti, Mo, Cr and Ta, and an alloy film thereof. Further, as shown in FIG. 3, the gate electrode 13C is a conductive film 13d formed of a conductive material such as polysilicon or amorphous silicon, and a metal film 13e (or an alloy film) selected from the above. It may be a structure in which and is laminated. The thickness of the gate electrode 13C is preferably 10 nm or more, for example. The upper limit is, for example, 1 μm or less.

The pixel transistor 13 of the present embodiment shows an example in which the semiconductor layer 13A extends in the Y-axis direction, but the present invention is not limited to this, and the pixel transistor 13 may be configured to extend in the X-axis direction. However, when the signal line DTL extends in the Y-axis direction as in the present embodiment, it is better to extend the semiconductor layer 13A in the Y-axis direction for better layout efficiency.

The light-shielding film 15 is for reducing the irradiation of obliquely incident light to the pixel transistor 13, and is formed on the side surface (surface S3) of the through hole H formed in the manufacturing process of the drive substrate 40A. .. As described above, the through hole H is formed along the formation region of the plurality of scanning lines WSL and the plurality of signal lines DTL in a plan view. Specifically, the peripheral end of the through hole H is formed so as to overlap with the scanning line WSL. As a result, the light-shielding film 15 is formed so as to include the pixel transistor 13 in a plan view. Further, the light-shielding film 15 is provided extending between the semiconductor layer 13A and the gate electrode 13C and on both sides thereof. Specifically, the light-shielding film 15 is continuously formed from the scanning line WSL to the upper end of the insulating film 14 in the stacking direction (Z-axis direction) of the pixel transistors 13. The light-shielding film 15 is formed of, for example, a material having light-shielding properties and conductivity. Specific materials include W, Mo, Ti, aluminum (Al) and copper (Cu). By forming the light-shielding film 15 using a conductive material, the gate electrode 13C and the scanning line WSL are electrically connected to each other via the light-shielding film 15 as shown in FIG. The thickness of the light-shielding film 15 is preferably 5 nm or more and 200 nm or less, for example.

Note that FIG. 1 shows an example in which the light-shielding film 15 is continuously formed on the peripheral edge of the scanning line WSL in a plan view, but the present invention is not limited to this. The light-shielding film 15 may be formed at least on both sides of the PN junction of the pixel transistor 13, specifically, the LDD region 13c, and is preferably formed on the peripheral edge thereof including the pixel transistor 13. Therefore, for example, the light-shielding film 15 may not be formed in the region corresponding to the scanning line WSL formed between the adjacent pixel transistors 13. In other words, the light-shielding film 15 may be formed intermittently along the scanning line WSL provided on the drive substrate 40A in a plan view.

Like the insulating films 12 and 14, the flattening layer 16 is composed of a SiO ₂ film, a Si _{3N 4 film} , or a laminated film thereof. The flattening layer 16 is for burying a through hole H to flatten the surface of the TFT layer 10. Therefore, in FIG. 3 and the like, an example of burying the through hole H and covering the insulating film 14 is shown, but it is not always necessary to form the through hole H on the insulating film 14. The thickness of the flattening layer 16 depends on the thickness of each part constituting the scanning line 11 and the pixel transistor 13, but is preferably 200 nm or more and 2 μm or less from the support substrate 41, for example.

The wiring layers 21, 22, and 23 constitute, for example, a signal line DTL or a common connection line COM (not shown) provided with an interlayer insulating layer 26 in between. The wiring layers 21, 22, and 23 are composed of, for example, a metal film such as Al, Cu, W, Ti, Mo, Cr, and Ta, and an alloy film thereof. The wiring layers 21, 22, and 23 are appropriately electrically connected by, for example, contacts 24, 25 and the like. The thickness of the wiring layers 21, 22, and 23 is preferably 100 nm or more and 1 μm or less, for example.

The signal line DTL extends, for example, in the Y-axis direction, and is provided, for example, directly above the semiconductor layer 13A (opposing region, for example, wiring 21A). The signal line DTL is electrically connected to the semiconductor layer 13A by a contact 17 penetrating the flattening layer 16, the insulating film 14, and the gate insulating film 13B in the source / drain region 13b of the semiconductor layer 13A.

The interlayer insulating layer 26 is composed of a SiO ₂ film, a Si _{3N 4 film} , or a laminated film thereof, similarly to the insulating films 12 and 14 and the flattening layer 16. The interlayer insulating layer 26 is insulated and separated between the wiring layers 21, 22, and 23, and is appropriately flattened. The thickness of the interlayer insulating layer 26 varies depending on the number of wiring layers to be laminated, but the film thickness of each wiring layer (between the wiring layer 21 and the wiring layer 22 and between the wiring layer 22 and the wiring layer 23) is determined. For example, it is preferably 200 nm or more and 1 μm.

The pixel electrode 31 is provided for each pixel P and is made of, for example, a transparent conductive film. Examples of the material of the transparent conductive film include oxide semiconductors called indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or IGZO (indium, gallium, zinc-containing oxide). ..

The facing substrate 50 has, for example, a configuration in which a support substrate 51 and a common electrode 53 provided on a surface facing the liquid crystal cell 60 of the support substrate 51 (on the surface S2 side) are laminated.

The support substrate 51 is made of, for example, a quartz substrate. The support substrate 51 is provided with, for example, a color filter (not shown) and a light-shielding layer (black matrix layer), which are covered with, for example, an overcoat film (not shown). The common electrode 53 is provided on the overcoat film.

The common electrode 53 is, for example, an electrode common to each pixel P, and supplies a voltage to the liquid crystal cell 60 together with the pixel electrode 31. Similar to the pixel electrode 31, the common electrode 53 is made of, for example, the transparent conductive film described above.

The liquid crystal cell 60 has a function of controlling the transmittance of light transmitted therethrough according to the image voltage supplied through the pixel electrode 31 and the common electrode 53. The liquid crystal cell 60 is displayed and driven by, for example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an ECB (Electrically controlled birefringence) mode, an FFS (Fringe Field Switching) mode, an IPS (In Plane Switching) mode, or the like. Is included. The liquid crystal material of the liquid crystal cell 60 is not particularly limited.

The alignment films 61 and 62 are for controlling the orientation of the liquid crystal cell 60, and are made of an inorganic material film such as a silicon oxide film. The thickness of the alignment films 61 and 62 is, for example, about 50 nm or more and 360 nm or less. The alignment films 61 and 62 are formed by, for example, a vapor deposition method. The alignment film 61 is formed so as to cover the pixel electrode 31, and the alignment film 62 is formed so as to cover the common electrode 53.

The sealing material 63 is for sealing the liquid crystal cell 60 between the drive substrate 40A and the facing substrate 50. The sealing material 63 is formed of, for example, an insulating material such as a polymer material. Specific examples thereof include epoxy resin and acrylic resin.

The polarizing plates 42 and 52 are, for example, arranged in a cross Nicol so that only light (polarized light) in a certain vibration direction can pass through.

(1-2. Manufacturing method of drive board)
The drive substrate 40A constituting the liquid crystal panel 1 of the present embodiment can be manufactured, for example, as follows.

6A to 6E show the manufacturing method of the drive substrate 40A in the order of processes. First, as shown in FIG. 6A, a W film is formed on the support substrate 41 by, for example, a CVD method or a sputtering method, and then a scanning line 11 is formed through a patterning step. Subsequently, for example, a silicon oxide film is formed on the support substrate 41 and the scanning line 11 by using, for example, a CVD method to form the insulating film 12. At this time, the surface of the insulating film 12 is flattened by using the CMP method or the like, if necessary. Next, for example, a polysilicon film is formed on the insulating film 12 by using, for example, a CVD method, and then a crystallization step is performed as necessary. After that, the semiconductor layer 13A is formed through a patterning step. Subsequently, for example, a silicon oxide film is formed on the insulating film 12 and the semiconductor layer 13A by a thermal oxidation method or a CVD method to form the gate insulating film 13B. Next, impurities are injected into the semiconductor layer 13A as needed to form the channel region 13a. The impurities may be injected before the gate insulating film 13B is formed. Subsequently, for example, a polysilicon film and a W film are formed on the gate insulating film 13B by using, for example, a CVD method, and then the gate electrode 13C composed of a laminated film of the conductive film 13d and the metal film 13e is formed through a patterning step. Form. Then, if necessary, impurities are injected into the semiconductor layer 13A and thermal annealing is performed to activate the impurities to form the LDD region 13c and the source / drain region 13b. Next, for example, a silicon oxide film is formed on the gate insulating film 13B and the gate electrode 13C by using, for example, a CVD method to form the insulating film 14. At this time, the surface of the insulating film 14 is flattened by using the CMP method or the like, if necessary.

Subsequently, as shown in FIG. 6B, a resist film 81 is formed on the insulating film 14 so as to cover the non-opening region Y, and the resist film 81 is used as a mask by, for example, RIE (Reactive Ion Etching) or wet etching. A through hole H is formed. At this time, as shown in FIG. 7, the end of the through hole H in the vicinity of the gate electrode 13C provided at the intersection of the plurality of scanning lines WSL (scanning line 11) and the plurality of signal lines DTL is as shown in FIG. It is preferable to form the through hole H so that the distance between the end portion (through hole end) and the end portion of the gate electrode 13C (the amount of overlap with the through hole H) is about −0.2 μm or more. Here, the case where the gate electrode 13C and the through hole H overlap is defined as a plus (+). As a result, even if the scanning line 11 and the gate electrode 13C are misaligned, the scanning line 11 and the gate electrode 13C are connected to each other via the light-shielding film 15 at any of the four corners of the gate electrode 13C having a rectangular shape. It becomes possible to connect electrically.

After that, as shown in FIG. 6C, for example, a CVD method, a sputtering method, an ALD (Atomic Layer Deposition) method, or the like is used to form a light-shielding film 15, for example, a W film 15a on the upper surface of the non-opening region Y, through holes. It is continuously formed on the side surface and the bottom surface of H.

Next, as shown in FIG. 6D, the W film 15a is processed using, for example, RIE. Specifically, the W film 15a other than the side surface of the through hole H is selectively removed. As a result, the light-shielding film 15 is formed only on the side surface (surface S3) of the through hole H. Note that FIG. 6D and the like show an example in which the thickness of the light-shielding film 15 in the X-axis direction is constant from the lower end to the upper end, but the present invention is not limited to this. For example, when the W film is processed by RIE as described above, the thickness of the light-shielding film 15 at the upper end portion gradually decreases toward the upper end by a manufacturing process such as RIE.

Subsequently, as shown in FIG. 6E, the through hole H is embedded by using, for example, the CVD method, and a silicon oxide film covering the insulating film 14 is formed to form the flattening layer 16. At this time, the surface of the flattening layer 16 is flattened by using the CMP method or the like, if necessary. Next, the contact 17 that penetrates the flattening layer 16, the insulating film 14, and the gate insulating film 13B and is in contact with the semiconductor layer 13A is formed. Subsequently, for example, an Al film is formed into a film by using, for example, a CVD method, and then a wiring layer 21 including wirings 21A and 21B is formed through a patterning step. Next, for example, a silicon oxide film is formed on the flattening layer 16 and the wiring layer 21 by using, for example, a CVD method.

Hereinafter, using the same method, the wiring layers 22, 23, the silicon oxide film and the wiring layer 21 (wiring 21A) and the wiring layer 22, the wiring layer 22 and the wiring layer 23, and the wiring layer 23 and the pixel electrode 31 are electrically connected. Form contacts 24, 25 to connect to. Note that the contacts that electrically connect the wiring layer 22 and the wiring layer 23 are not shown here. As a result, the multilayer wiring layer 20 is formed. Finally, by forming the pixel electrode 31 on the interlayer insulating layer 26, the drive substrate 40A shown in FIG. 3 and the like is completed.

(1-3. Overall configuration of projection type display device)
FIG. 8 shows an example of the overall configuration of the projector 100 provided with the liquid crystal panel 1 of the present disclosure. The projector 100 is, for example, a three-panel transmissive projector, and has, for example, a light emitting unit 110, an optical path branching unit 120, a spatial light modulation unit 130, a synthesis unit 140, and a projection unit 150.

The light emitting unit 110 supplies a light beam to be applied to the irradiated surface of the spatial light modulation unit 130, and includes, for example, a lamp of a white light source and a reflecting mirror formed behind the lamp. There is. The light emitting unit 110 may have some optical element in the region (on the optical axis AX) through which the light 111 of the lamp passes, if necessary. For example, on the optical axis AX of the lamp, a filter that dims light other than visible light among the light 111 from the lamp and an optical integrator that equalizes the illuminance distribution on the irradiated surface of the spatial light modulation unit 130. It can be provided in this order from the lamp side.

The optical path branching unit 120 separates the light 111 output from the light emitting unit 110 into a plurality of color lights having different wavelength bands, and guides each color light to the irradiated surface of the spatial light modulation unit 130. As shown in FIG. 8, for example, the optical path branching portion 120 includes one cross mirror 121, two mirrors 122, and two mirrors 123. The cross mirror 121 separates the light 111 output from the light emitting unit 110 into a plurality of color lights having different wavelength bands, and branches the optical path of each color light. The cross mirror 121 is arranged, for example, on the optical axis AX, and is configured by connecting two mirrors having different wavelength selectivity to each other so as to cross each other. The mirrors 122 and 123 reflect colored light (red light 111R, blue light 111B in FIG. 8) whose optical path is branched by the cross mirror 121, and are arranged at a place different from the optical axis AX. The mirror 122 guides the light reflected in one direction (red light 111R in FIG. 8) intersecting the optical axis AX by one mirror included in the cross mirror 121 to the irradiated surface of the spatial light modulation unit 130R. Have been placed. The mirror 123 guides the light reflected in another direction (blue light 111B in FIG. 8) intersecting the optical axis AX by another mirror included in the cross mirror 121 to the irradiated surface of the spatial light modulation unit 130B. Have been placed. Of the light 111 output from the light emitting unit 110, the light that passes through the cross mirror 121 and passes on the optical axis AX (green light 111G in FIG. 8) is the spatial light modulation unit 130G arranged on the optical axis AX. It is designed to be incident on the irradiated surface.

The spatial light modulation unit 130 is configured by using, for example, the liquid crystal panel 1 shown in FIG. 2 or the like, and modulates a plurality of colored lights for each colored light according to a video signal Din input from an information processing device (not shown). Then, modulated light is generated for each colored light. The spatial light modulation unit 130 includes, for example, a spatial light modulation unit 130R that modulates the red light 111R, a spatial light modulation unit 130G that modulates the green light 111G, and a spatial light modulation unit 130B that modulates the blue light 111B. ..

The spatial light modulation unit 130R is arranged in a region facing one surface of the synthesis unit 140. The spatial light modulation unit 130R modulates the incident red light 111R based on the video signal Din to generate the red image light 112R, and the red image light 112R is used by the synthesis unit 140 behind the spatial light modulation unit 130R. It is designed to output on one side. The spatial light modulation section 130G is arranged in a region facing the other surface of the synthesis section 140. The spatial light modulation unit 130G modulates the incident green light 111G based on the video signal Din to generate green image light 112G, and the green image light 112G is used by the synthesis unit 140 behind the spatial light modulation unit 130R. It is designed to output to the other side. The spatial light modulation section 130B is arranged in a region facing the other surface of the synthesis section 140. The spatial light modulation unit 130B modulates the incident blue light 111B based on the video signal Din to generate blue image light 112B, and the blue image light 112B is used by the synthesis unit 140 behind the spatial light modulation unit 130R. It is designed to output to other surfaces.

The synthesizing unit 140 synthesizes a plurality of modulated lights to generate image light. The synthesis unit 140 is, for example, arranged on the optical axis AX, and is, for example, a cross prism configured by joining four prisms. On the junction surface of these prisms, for example, two selective reflection surfaces having different wavelength selectivity are formed by a multilayer interference film or the like. One selective reflecting surface is adapted to reflect, for example, the red image light 112R output from the spatial light modulation unit 130R in a direction parallel to the optical axis AX and guide it in the direction of the projection unit 150. Further, the other selective reflection surface is adapted to reflect, for example, the blue image light 112B output from the spatial light modulation unit 130B in a direction parallel to the optical axis AX and guide it in the direction of the projection unit 150. Further, the green image light 112G output from the spatial light modulation unit 130G passes through the two selective reflection surfaces and travels in the direction of the projection unit 150. After all, the synthesizing unit 140 functions to synthesize the image lights generated by the spatial light modulation units 130R, 130G, and 130B to generate the image light 113, and output the generated image light 113 to the projection unit 150. ..

The projection unit 150 projects the image light 113 output from the composition unit 140 onto the screen 200 to display an image. The projection unit 150 is arranged, for example, on the optical axis AX, and is configured by, for example, a projection lens.

FIG. 9 shows an example of the overall configuration of the spatial light modulation units 130R, 130G, and 130B. The spatial light modulation units 130R, 130G, and 130B include, for example, the liquid crystal panel 1 described above and a drive circuit 70 for driving the liquid crystal panel 1. The drive circuit 70 includes a display control unit 71, a data driver 72, and a gate driver 73.

The liquid crystal panel 1 has a pixel region 1A in which a plurality of pixels P are formed in a matrix, and a peripheral region 1B thereof. The liquid crystal panel 1 displays an image based on a video signal Din input from the outside by actively driving each pixel P by a data driver 72 and a gate driver 73.

The liquid crystal panel 1 has a plurality of scanning lines WSL extending in the row direction, a plurality of signal line DTLs extending in the column direction, and a plurality of common connection line COMs extending in the row direction or the column direction. ing. Pixels P are provided corresponding to the intersections of the signal line DTL and the scanning line WSL. Each signal line DTL is connected to an output end (not shown) of the data driver 72. Each scan line WSL is connected to the output end (not shown) of the gate driver 73. Each common connection line COM is connected to, for example, an output end (not shown) of a circuit that outputs a fixed potential.

The display control unit 71 stores, for example, the supplied video signal Din in the frame memory for each screen (for each frame display) and holds it. The display control unit 71 also has a function of controlling, for example, the data driver 72 for driving the liquid crystal panel 1 and the gate driver 73 to operate in conjunction with each other. Specifically, the display control unit 71 supplies, for example, a scanning timing control signal to the data driver 72, and supplies the data driver 72 with an image signal for one horizontal line based on the image signal held in the frame memory. It is designed to supply display timing control signals.

The data driver 72 supplies, for example, a video signal Din for one horizontal line supplied from the display control unit 71 to each pixel P as a signal voltage. Specifically, the data driver 72 supplies, for example, a signal voltage corresponding to the video signal Din to each pixel P constituting one horizontal line selected by the gate driver 73 via the signal line DTL. Is.

The gate driver 73 has a function of selecting a pixel P to be driven according to, for example, a scanning timing control signal supplied from the display control unit 71. Specifically, the gate driver 73 is formed in a matrix in the pixel region 1A by applying a selection pulse to the gate electrode 13C of the pixel transistor 13 of the pixel P, for example, via the scanning line WSL. One of P is selected as the driving target. Then, in these pixels P, one horizontal line is displayed according to the signal voltage supplied from the data driver 72. In this way, the gate driver 73 sequentially scans one horizontal line at a time division, for example, to display the entire display area.

Next, the circuit configuration of the pixel P will be described. FIG. 10 shows an example of the circuit configuration of the pixel P. The pixel P has a liquid crystal element 2 and a pixel circuit 3 for driving the liquid crystal element 2. The liquid crystal element 2 and the pixel circuit 3 are provided corresponding to the intersection of the scanning line WSL and the signal line DTL. The liquid crystal element 2 is composed of a liquid crystal cell 60, a pixel electrode 31 sandwiching the liquid crystal cell 60, and a common electrode 53. The pixel circuit 3 is composed of a transistor (pixel transistor 13) that writes a signal voltage to the liquid crystal element 2 and a storage capacity 27 that holds the voltage written to the liquid crystal element 2. The storage capacity 27 is composed of a pair of capacity electrodes facing each other via a predetermined gap, one capacity electrode is connected to the source / drain region 13b of the semiconductor layer 13A, and the other capacity electrode is a common connection. It is connected to the line COM.

(1-4. Action / effect)
As described above, there is a high demand for high brightness in liquid crystal panels, and in order to realize high brightness, it is necessary to improve the aperture ratio of pixels. However, improving the aperture ratio reduces the light-shielding area of the TFT, and in particular, when the liquid crystal panel is used as a light modulator (light valve) of a projection type display device, leakage occurs due to strong light from a light source. A current is generated, which causes deterioration of image quality such as flicker.

As described above, the aperture ratio and the light-shielding property are basically in a trade-off relationship, and the development of a liquid crystal panel capable of supporting the light-shielding property while improving the aperture ratio is underway. For example, an electro-optic device has been developed in which a gate electrode provided on a semiconductor layer is embedded on both sides of the semiconductor layer as a contact to a scanning line to prevent light from entering the semiconductor layer. However, in this electro-optic device, since the contact by the gate electrode is formed in the non-opening region, it is difficult to improve the aperture ratio. Further, since the gate electrode is embedded in a part on both sides of the semiconductor layer, the light-shielding property of the portion where the gate electrode is not embedded remains low.

In addition, for example, an intermediate light-shielding layer is further provided between the light-shielding layer provided in the non-opening region and the TFT, and the intermediate light-shielding layer is extended to a groove provided on the peripheral edge of the semiconductor layer to provide light-shielding property. A display device with improved performance has been developed. However, in this display device, since the groove for extending the intermediate light-shielding layer is provided in the non-opening region, it is disadvantageous for improving the aperture ratio. Further, it is difficult to control the depth of the groove, and further, since there is a gap between the scanning line provided below the TFT and the groove, there is a possibility that light is incident from this gap.

Further, for example, an electro-optic device has been developed in which an optical surface is provided between an open region and a non-open region, thereby reflecting obliquely incident light toward the open region to improve light shielding and light utilization efficiency. ing. However, in this electro-optic device, since the optical surface is formed of a light-transmitting film such as SiN, it is difficult to obtain a large effect on the light-shielding property.

On the other hand, in the liquid crystal panel 1 of the present embodiment, in a plan view, along a plurality of scanning lines WSL (scanning lines 11) including the semiconductor layer 13A and the gate electrode 13C constituting the pixel transistor 13 above. A light-shielding film 15 extending in the stacking direction (Z-axis direction) is formed so as to cover the side surface of the pixel transistor 13. As a result, a light-shielding film 15 is formed around the pixel transistor 13, and the intrusion path of light incident from an oblique direction into the pixel transistor 13 (particularly, the LDD region 13c of the semiconductor layer 13A) is significantly reduced. It becomes possible. That is, it is possible to improve the light-shielding property of the pixel transistor 13. Further, since the light-shielding film 15 is formed by using a conductive material, the scanning line 11 and the gate electrode 13C are electrically connected without separately arranging a contact between the scanning line 11 and the gate electrode 13C. Can be connected to. Therefore, it is possible to improve the aperture ratio.

As described above, in the present embodiment, since the light-shielding film 15 is formed along the plurality of scanning lines WSL in the plan view, the light-shielding film 15 is formed around the pixel transistor 13. Therefore, the light-shielding property of the pixel transistor 13 is improved, and the image quality can be improved. Further, since the light-shielding film 15 is formed by using a conductive material, the scanning line 11 and the gate electrode 13C are electrically connected without separately arranging a contact between the scanning line 11 and the gate electrode 13C. You will be able to connect to. Therefore, the aperture ratio can be improved, and high brightness can be realized. That is, it is possible to achieve both high brightness and improved image quality.

Hereinafter, the second to fourth embodiments and modifications 1 to 4 of the present disclosure will be described. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

<2. Second Embodiment>
FIG. 11 shows a cross-sectional configuration of the drive substrate 40B constituting the liquid crystal panel 1 according to the second embodiment of the present disclosure. In the drive substrate 40B of the present embodiment, the light-shielding film 15 is provided along a plurality of scanning lines WSL provided on the drive substrate 40A (light-shielding film 15A) in a plan view, and is above the pixel transistor 13 (light-shielding film 15B). ) Also has the configuration provided. The drive substrate 40B shown in FIG. 11 schematically shows a cross-sectional configuration of two pixels P arranged adjacent to each other, including the pixel transistor 13 in the II line shown in FIG. 1.

FIG. 12 shows one step in manufacturing the drive substrate 40B shown in FIG. The light-shielding film 15 (light-shielding) is formed on the side surface of the insulating film 14 (upper surface of the non-opening region Y) and the through hole H provided on the pixel transistor 13 by the same method as that of the drive substrate 40A in the first embodiment. For example, a W film 15a is formed as a film 15A, 15B). Next, as shown in FIG. 12, a resist film 82 having a desired pattern covering the side surface and the upper surface of the W film 15a is formed. Specifically, the resist film 82 is provided with an opening 82H at a position forming a contact 17 that electrically connects the wiring layer 21 and the semiconductor layer 13A. After that, for example, the W film 15a is processed using RIE, and then the drive substrate 40B is manufactured by the same method as in the first embodiment. This completes the drive substrate 40B on which the light-shielding film 15 covering the upper side of the pixel transistor 13 is formed together with the side surface of the through hole H.

As described above, in the present embodiment, the light-shielding film 15 covering the upper side is formed together with the side surface of the pixel transistor 13, so that the stray light propagating in the drive substrate 40B can be prevented from entering the pixel transistor 13. Is possible. Therefore, it is possible to further improve the light-shielding property for the pixel transistor 13.

In the first embodiment, the light-shielding film 15 is provided from the upper surface of the scanning line 11 to the upper surface of the insulating film 14, but the present invention is not limited to this. For example, as shown in FIG. 11, it may be formed so as to cover the end surface (side surface) of the scanning line 11 from the upper surface of the support substrate 41.

<3. Third Embodiment>
FIG. 13 shows a cross-sectional configuration of the drive substrate 40C constituting the liquid crystal panel 1 according to the third embodiment of the present disclosure. In the drive substrate 40C of the present embodiment, the scanning line 11, the insulating film 12, and the insulating film 14 have the same end face, and the light-shielding film 15 is formed on the end face from the upper surface of the support substrate 41 to the upper end of the insulating film 14. Has a configured configuration. The drive substrate 40C shown in FIG. 13 schematically shows the cross-sectional configuration of two pixels P arranged adjacent to each other, including the pixel transistor 13 in the II line shown in FIG. 1.

14A and 14B show a part of the process for manufacturing the drive substrate 40C shown in FIG. First, as shown in FIG. 14A, for example, a W film 11a to be a scanning line 11 is formed on the support substrate 41 by using, for example, a CVD method or a sputtering method. After that, a patterning step may be performed, but the W film 11a is not separated in the non-open region. Subsequently, the silicon oxide film 12a to be the insulating film 12 is formed on the W film 11a, and then the semiconductor layer 13A is formed in the same manner as in the first embodiment, and then the gate insulating film 13B is formed, for example, oxidation. For example, a silicon oxide film 14a to be a silicon film 13x, a gate electrode 13C, and an insulating film 14 is formed in this order.

Next, as shown in FIG. 14B, a resist film 83 is formed on the insulating film 14 in a corresponding region so as to cover the non-opening region Y, and the resist film 81 is used as a mask and supported by, for example, RIE or wet etching. A through hole H reaching to the substrate 41 is formed. At this time, the W film 11a, which is the scanning line 11 of the non-opening region Y, is also separated. After that, the drive substrate 40C is manufactured by the same method as that of the first embodiment. This completes the drive substrate 40C in which the scanning line 11, the insulating film 12, and the insulating film 14 have the same end face.

As described above, in the present embodiment, the through hole H is integrally etched with the scanning line 11, the insulating film 12, and the insulating film 14 to form the light-shielding film 15 having conductivity on the side surface thereof. .. As a result, the scanning lines 11, the insulating film 12, and the side surfaces of the insulating film 14 of the light-shielding film 15 form the same surface (plane S3). That is, the light-shielding film 15 makes it possible to electrically connect the scanning line 11 and the gate electrode 13C without alignment. Therefore, it is not necessary to consider the misalignment between the through hole H and the scanning line 11, and the aperture ratio can be further improved.

<4. Modification 1>
FIG. 15 schematically shows the planar configuration of the drive substrate 40D constituting the liquid crystal panel 1 according to the modified example of the present disclosure. FIG. 16 shows the cross-sectional structure of the IV-IV line shown in FIG. In the drive substrate 40D of this modification, the gate electrode 13C is stretched in the X-axis direction and is continuously formed between adjacent pixels P. Specifically, it is formed above the scanning line 11 so as to extend in the X-axis direction facing the scanning line 11, and the scanning line 11 is formed through a through hole 13H formed between adjacent pixels P. It is different from the first embodiment in that it is electrically connected to the above-mentioned first embodiment.

As in the first embodiment, the through hole 13H has a scanning line 11, an insulating film 12, a semiconductor layer 13A and a gate insulating film 13B formed on the support substrate 41, and then resists on the gate insulating film 13B. The film is patterned and formed by RIE or the like using this resist film as a mask. After forming the through hole 13H, as in the first embodiment, for example, using the CVD method, the through hole 13H is embedded, and then, for example, a polysilicon film is formed on the gate insulating film 13B. The gate electrode 13C is formed through a patterning step. After that, the drive substrate 40D is completed by going through the same steps as in the first embodiment.

As described above, in the present modification, the scanning line 11 and the gate electrode 13C are connected to each other at a position away from the semiconductor layer 13A without passing through the light-shielding film 15. Therefore, the first embodiment is described above. Compared with the above form, the scanning line 11 and the gate electrode 13C can be easily connected. Further, since the through hole 13H is not required to have a light-shielding property, the degree of freedom in layout is improved, and the aperture ratio can be further improved.

In this modification, since the potential of the gate electrode 13C is directly supplied from the scanning line 11, the potential of the light-shielding film 15 may be arbitrary, and may be electrically floating, for example. Therefore, in a plan view, the distance between the end of the through hole H forming the light-shielding film 15 on the side surface and the end of the gate electrode 13C (the amount of overlap with the through hole H) may be less than −0.2 μm.

<5. Modification 2>
FIG. 17 schematically shows the planar configuration of the drive substrate 40E constituting the liquid crystal panel 1 according to the modified example of the present disclosure. FIG. 18 shows the cross-sectional configuration of the VV line shown in FIG. In this modification, the gate electrode 13C is electrically connected to the wiring layer 21 via the contact 18 in the peripheral region 1B, and the potential is supplied from the wiring layer 21.

In this modification, the light-shielding film 15 has the same potential as the scanning line 11. Further, in a plan view, the distance between the end of the through hole H forming the light-shielding film 15 on the side surface and the end of the gate electrode 13C (the amount of overlap with the through hole H) is less than −0.2 μm. There is.

As described above, in the present modification, in the peripheral region 1B, the gate electrode 13C and the wiring layer 21 are connected via the contact 18, and the potential is supplied from the wiring layer 21 to the gate electrode 13C. Compared with the first modification, the connection step between the scanning line 11 and the gate electrode 13C can be reduced.

Further, in this modification, the scanning line WSL (scanning line 11) serves as a light-shielding film on the back surface of the pixel transistor 13. Therefore, by setting the potential of the scanning line 11 to an optimum value for the holding characteristics of the pixel transistor 13, it is possible to reduce the leakage current of the pixel transistor 13 due to the electric field and further improve the image quality. The scanning line 11 and the light-shielding film 15 in this modification may have a floating potential, but by fixing the scanning line 11 and the light-shielding film 15 to a certain potential, the influence of capacitive coupling can be reduced. This makes it possible to further improve the image quality.

<6. Fourth Embodiment>
FIG. 19 schematically shows the planar configuration of the drive substrate 40F constituting the liquid crystal panel 1 according to the fourth embodiment of the present disclosure, and FIG. 20 shows the VI-VI line shown in FIG. It is a schematic representation of the cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 in the above. In the drive substrate 40F of the present embodiment, the light-shielding film 15 is continuously provided from the upper surface of the support substrate 41 to the upper end of the wiring layer 21 (specifically, the wiring 21A), and the semiconductor layer 13A and the wiring 21A are provided. It has a configuration electrically connected via a light-shielding film 15. Further, the scanning line WSL is separated for each pixel P in the X-axis direction.

21A to 21C show a part of the process for manufacturing the drive substrate 40F shown in FIG. First, the insulating film 14 is formed by the same method as the drive substrate 40A in the first embodiment. At this time, the semiconductor layer 13A is patterned so that one end face in the Y-axis direction is outside the end face of the scanning line 11. Next, as shown in FIG. 21A, the contact 17 penetrating the insulating film 14 and the gate insulating film 13B is formed. Subsequently, for example, an Al film is formed into a film by using a CVD method, and then the wiring layer 21 (wiring 21A, 21B) is formed through a patterning step. At this time, the end surface of the wiring 21A on the opening region X side is formed so as to be outside the end surface of the scanning line 11 provided below and to be the same as or inside the end surface of the semiconductor layer 13A. Next, the resist film 84 is formed on the insulating film 14 and the wiring layer 21. At this time, the end face of the wiring 21A on the opening region X side is exposed. Next, the through hole H is formed by, for example, RIE or wet etching using the resist film 84 and the wiring 21A as masks. As a result, the end surface of the semiconductor layer 13A is exposed, and a side surface (surface S3a) having the same surface as the end surface of the wiring layer 21 (wiring 21A) is formed. On the side surface (surface S3b) on the wiring 21B side, the end surface of the semiconductor layer 13A is covered with the gate insulating film 13B.

Subsequently, after removing the resist film 84, as shown in FIG. 21B, for example, by using a CVD method, for example, the W film 15a to be the light-shielding film 15 is formed on the upper surface of the non-opening region Y and the side surface of the through hole H. And continuously formed on the bottom surface. Next, as shown in FIG. 21C, the W film 15a other than the end surface of the wiring layer 21 and the side surface portion of the through hole H is removed by using, for example, RIE to form the light-shielding film 15. As a result, the semiconductor layer 13A and the wiring 21A are electrically connected via the light-shielding film 15. The wiring 21A is a signal line DTL, whereby the potential of the signal line DTL is supplied to the semiconductor layer 13A.

After that, for example, the through hole H is embedded by using a CVD method, and a silicon oxide film covering the insulating film 14 and the wiring layer 21 is formed to form the flattening layer 16. At this time, the surface of the flattening layer 16 is flattened by using the CMP method or the like, if necessary. Subsequently, similarly to the first embodiment, the wiring layers 22 and 23, the silicon oxide film, the wiring layer 21 and the wiring layer 22, the wiring layer 22 and the wiring layer 23, and the wiring layer 23 and the pixel electrode 31 are electrically connected. The contacts 24, 25 and the pixel electrode 31 connected to the above are formed. As a result, the drive board 40F shown in FIG. 19 is completed. Note that the contacts that electrically connect the wiring layer 22 and the wiring layer 23 are not shown here.

Although FIG. 19 shows an example in which the light-shielding film 15 extending in the Y-axis direction is separated between adjacent pixels P, it may be continuous. This is because, in the present embodiment, the scanning line 11 and the gate electrode 13C are arranged so as not to be electrically connected to each other.

As described above, in the present embodiment, after the wiring layer 21 is formed, the side surface (plane) including the end surface of the wiring 21A and the end surface of the semiconductor layer 13A with the wiring layer 21 (specifically, the wiring 21A) as a mask. A through hole H having S3a) was formed, and a light-shielding film 15 was formed on the side surfaces (surface S3a and surface S3b) of the through hole H. As a result, the semiconductor layer 13A and the wiring 21A which is the signal line DTL are electrically connected via the light-shielding film 15, and as shown in FIG. 3 in the first embodiment, the semiconductor layer 13A and the wiring layer are connected. It is no longer necessary to form the contact 17 for connecting to the 21, and it is possible to reduce the non-opening area by the area of the contact 17. That is, the aperture ratio can be further improved.

Further, in the present embodiment, after the wiring layer 21 is formed, the light-shielding film 15 is formed on the side surface of the through hole H including the end surface of the wiring layer 21, so that the light-shielding film 15 of the present embodiment is formed. , Is formed higher in the Z-axis direction than the light-shielding film 15 in the first embodiment. Therefore, the light-shielding property for the pixel transistor 13 is further improved, and the image quality can be further improved.

<7. Modification 3>
FIG. 22 shows a cross-sectional configuration of the drive substrate 40G constituting the liquid crystal panel 1 according to the modified example of the present disclosure. In the drive substrate 40G of this modification, a light-shielding film 15 is formed after the wiring layer 23 is formed. Further, the through hole H is provided so that the end surface of the semiconductor layer 13A and the end surface of the wiring layer 23 form the same surface (plane S3d). Therefore, the light-shielding film 15 is continuously formed from the upper surface of the support substrate 41 to the upper end of the wiring layer 23, and electrically connects the semiconductor layer 13A and the wiring layer 23. The other end surface of the semiconductor layer 13A is covered with the gate insulating film 13B (surface S3c). The wiring layer 23 is electrically connected to the pixel electrode 31 via the contact 25. Therefore, in this modification, the scanning line WSL is separated for each pixel P in both the X-axis direction and the Y-axis direction, and the light-shielding film 15 formed along the scanning line WSL is separated for each pixel P. It is formed. The drive substrate 40F shown in FIG. 22 schematically shows the cross-sectional configuration of two pixels P arranged adjacent to each other, including the pixel transistor 13 in the VI-VI line shown in FIG.

The drive substrate 40G of this modification can be manufactured by the same method as that of the fourth embodiment, except that the through hole H and the light-shielding film 15 are provided after the wiring layer 23 is formed.

As described above, in this modification, after the wiring layer 23 is formed, a through hole H having a side (surface S3d) including the end surface of the wiring layer 23 and the end surface of the semiconductor layer 13A is formed, and the through hole H is formed. A light-shielding film 15 was formed on the side surfaces (surface S3c and surface S3d) of the above. As a result, the semiconductor layer 13A and the wiring layer 23 are electrically connected via the light-shielding film 15. Further, the semiconductor layer 13A is electrically connected to the pixel electrode 31 via the light-shielding film 15, the wiring layer 23, and the contact 25. This eliminates the need to form a contact 17 for connecting the semiconductor layer 13A and the wiring layer 21 as in the fourth embodiment, and reduces the non-opening region by the area of the contact 17. Is possible.

Further, in this modification, after the wiring layer 23 is formed, the light-shielding film 15 is formed on the side surface of the through hole H including the end surface of the wiring layer 23. Therefore, the light-shielding film 15 in the fourth embodiment is formed. A light-shielding film 15 higher than that in the Z-axis direction is formed. Therefore, it is possible to further improve the light-shielding property for the pixel transistor 13. Further, in this modification, since the light-shielding film 15 is formed immediately below the pixel electrode 31, the effect as a waveguide can be obtained by forming the light-shielding film 15 using a material having a high light reflectance. It is possible to improve the light utilization efficiency.

<8. Modification 4>
FIG. 23 schematically shows the planar configuration of the drive substrate 40H constituting the liquid crystal panel 1 according to the modified example of the present disclosure. FIG. 24 schematically shows the cross-sectional configuration of two adjacent pixels P including the pixel transistor 13 in the VII-VII line shown in FIG. 23. In the first to fourth embodiments and the first to third modifications, a top gate type transistor is shown as an example of the pixel transistor 13 provided for each pixel P, but the present invention is not limited to this, as shown in FIG. 24. It may be a bottom gate type transistor. The drive substrate 40H of this modification has a TFT layer 90 having a bottom gate type pixel transistor 93 on a support substrate 41, a multilayer wiring layer 20 having the same configuration as that of the first embodiment, and pixels. The electrodes 31 are laminated in this order.

The pixel transistor 93 has a configuration in which a gate electrode 93C also serving as a scanning line WSL, a gate insulating film 93B, and a semiconductor layer 93A are laminated in this order from the support substrate 41 side. The insulating film 92 and the insulating film 94 are laminated in this order on the semiconductor layer 93A. Each pixel P is separated by a through hole H, and a light-shielding film 95 is formed along the end faces of the gate insulating film 93B and the insulating films 92 and 94 having the same surface. The through hole H is embedded by the flattening layer 96, and the flattening layer 96 is also formed on the insulating film 94, for example, to flatten the surface of the TFT layer 90. The TFT layer 90 and the multilayer wiring layer 20 penetrate the flattening layer 96, the insulating film 94, and the insulating film 92, and are electrically connected by a contact 97 connecting the semiconductor layer 93A and the wiring layer 21.

Although the first to fourth embodiments and the modifications 1 to 4 have been described above, the contents of the present disclosure are not limited to these embodiments and the like, and various modifications are possible. For example, the structure of the liquid crystal panel 1 of the present disclosure can be applied not only to a projection type display device but also to all semiconductor devices that require shading. Further, in the above-described embodiment and the like, an example in which a liquid crystal element is used as a display element has been given, but the present invention is not limited to this, and for example, an organic EL (Electro Luminescence) element or a CLED (Crystal Light Emitting Diode) may be used. do not have.

The display device and the projection type display device of the present disclosure may have the following configurations.
(1)
A first substrate and a second substrate having liquid crystal layers arranged so as to face each other are provided.
The first substrate is
Support board and
A plurality of scanning lines and a plurality of signal lines provided on the support substrate and intersecting each other,
A TFT element provided at the intersection of the plurality of scanning lines and the plurality of signal lines, in which a semiconductor layer and a gate electrode are laminated in this order from the support substrate side via an insulating film, respectively .
It is formed of a conductive material and has a light-shielding film provided along the plurality of scanning lines in a plan view.
The insulating film provided at each of the plurality of scanning lines and the intersection of the plurality of scanning lines and the plurality of signal lines has the same end face, and the light-shielding film extends on the same end face.
Display device.
(2)
The display device according to (1), wherein the light-shielding film is electrically connected to any one of the wiring including the plurality of scanning lines and the plurality of signal lines, the gate electrode, and the semiconductor layer.
(3)
The display device according to (1) or (2), wherein the light-shielding film is continuously provided along the plurality of scanning lines in a plan view.
(4)
The display device according to any one of (1) to (3) above, wherein the TFT element is surrounded by the light-shielding film in a plan view.
(5)
The light-shielding film is described in any one of (2) to (4) above, wherein the side surface of the TFT element is extended between the gate electrode and the semiconductor layer and on both sides thereof. Display device.
(6)
The display device according to any one of (2) to (5) above, wherein the semiconductor layer includes an LDD (Lightly Doped Drain) region.
(7)
The display device according to any one of (2) to (6) above, wherein the light-shielding film extends from the surface of the support substrate to the upper part of the gate electrode in the stacking direction.
(8)
In the first substrate, the gate electrode also serving as the scanning line and the semiconductor layer are laminated in this order from the support substrate side via an insulating film.
The display device according to any one of (2) to (6) above, wherein the light-shielding film extends from the surface of the support substrate to the upper part of the semiconductor layer in the stacking direction.
(9)
The first substrate has a plurality of pixels, and also has an opening region provided for each of the plurality of pixels and a non-opening region provided around the opening region.
The display device according to any one of (1) to (8) above, wherein the light-shielding film is formed on the side surface of a through hole formed including a part of the open region and the non-open region. ..
(10)
It has an optical modulator that modulates the light from the light source,
The optical modulator is
A first substrate and a second substrate having liquid crystal layers arranged so as to face each other are provided.
The first substrate is
Support board and
A plurality of scanning lines and a plurality of signal lines provided on the support substrate and intersecting each other,
A TFT element provided at the intersection of the plurality of scanning lines and the plurality of signal lines, in which a semiconductor layer and a gate electrode are laminated in this order from the support substrate side via an insulating film, respectively .
It is formed of a conductive material and has a light-shielding film provided along the plurality of scanning lines in a plan view.
The insulating film provided at each of the plurality of scanning lines and the intersection of the plurality of scanning lines and the plurality of signal lines has the same end face, and the light-shielding film extends on the same end face.
Projection type display device.

This application claims priority based on Japanese Patent Application No. 2017-016621 filed on February 1, 2017 by the Japan Patent Office, and this application is made by reference to all the contents of this application. Invite to.

Those skilled in the art may conceive various modifications, combinations, sub-combinations, and changes, depending on design requirements and other factors, which are included in the claims and their equivalents. It is understood that it is one of ordinary skill in the art.

Claims (10)

A first substrate and a second substrate having liquid crystal layers arranged so as to face each other are provided.
The first substrate is
Support board and
A plurality of scanning lines and a plurality of signal lines provided on the support substrate and intersecting each other,
A TFT element provided at the intersection of the plurality of scanning lines and the plurality of signal lines, in which a semiconductor layer and a gate electrode are laminated in this order from the support substrate side via an insulating film, respectively .
It is formed of a conductive material and has a light-shielding film provided along the plurality of scanning lines in a plan view.
The insulating film provided at each of the plurality of scanning lines and the intersection of the plurality of scanning lines and the plurality of signal lines has the same end face, and the light-shielding film extends on the same end face.
Display device. The display device according to claim 1, wherein the light-shielding film is electrically connected to any one of the wiring including the plurality of scanning lines and the plurality of signal lines, the gate electrode, and the semiconductor layer. The display device according to claim 1, wherein the light-shielding film is continuously provided along the plurality of scanning lines in a plan view. The display device according to claim 1, wherein the TFT element is surrounded by the light-shielding film in a plan view. The display device according to claim 2, wherein the light-shielding film is provided by extending the side surface of the TFT element between the gate electrode and the semiconductor layer and on both sides thereof. The display device according to claim 2, wherein the semiconductor layer includes an LDD (Lightly Doped Drain) region. The display device according to claim 2, wherein the light-shielding film extends from the surface of the support substrate to above the gate electrode in the stacking direction. In the first substrate, the gate electrode also serving as the scanning line and the semiconductor layer are laminated in this order from the support substrate side via an insulating film.
The display device according to claim 2, wherein the light-shielding film extends from the surface of the support substrate to the upper part of the semiconductor layer in the stacking direction. The first substrate has a plurality of pixels, and also has an opening region provided for each of the plurality of pixels and a non-opening region provided around the opening region.
The display device according to claim 1, wherein the light-shielding film is formed on the side surface of a through hole formed by including a part of the open region and the non-open region. It has an optical modulator that modulates the light from the light source,
The optical modulator is
A first substrate and a second substrate having liquid crystal layers arranged so as to face each other are provided.
The first substrate is
Support board and
A plurality of scanning lines and a plurality of signal lines provided on the support substrate and intersecting each other,
A TFT element provided at the intersection of the plurality of scanning lines and the plurality of signal lines, in which a semiconductor layer and a gate electrode are laminated in this order from the support substrate side via an insulating film, respectively .
It is formed of a conductive material and has a light-shielding film provided along the plurality of scanning lines in a plan view.
The insulating film provided at each of the plurality of scanning lines and the intersection of the plurality of scanning lines and the plurality of signal lines has the same end face, and the light-shielding film extends on the same end face.
Shooting display device.

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