CN110226121B

CN110226121B - Display device and projection display apparatus

Info

Publication number: CN110226121B
Application number: CN201780084744.8A
Authority: CN
Inventors: 津野仁志
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 2017-02-01
Filing date: 2017-12-27
Publication date: 2022-09-30
Anticipated expiration: 2037-12-27
Also published as: JPWO2018142822A1; JP7028192B2; WO2018142822A1; CN110226121A

Abstract

One embodiment of a display device according to the present disclosure is provided with a first substrate and a second substrate arranged facing each other with a liquid crystal layer interposed therebetween. The first substrate includes: supporting a substrate; a plurality of scanning lines and a plurality of signal lines disposed on the support substrate and crossing each other; TFT elements disposed at intersections of the plurality of scanning lines and the plurality of signal lines, respectively; and a light shielding film formed of a conductive material and disposed along the plurality of scanning lines in a plan view.

Description

Display device and projection display apparatus

Technical Field

For example, the present disclosure relates to a display device and a projection display apparatus including the display device. The display device serves as a light modulation unit.

Background

In recent years, a projection Liquid Crystal Display (LCD) unit that projects a picture on a screen is widely used not only in offices but also in homes. A projection liquid crystal display device (liquid crystal projector) modulates light from a light source by using a light valve, generates image light, projects the image light on a screen, and displays a picture. The light valve (light modulation unit) includes a liquid crystal panel. For example, when each pixel is subjected to active matrix driving in accordance with an external picture signal, the light valve modulates light.

It is highly desirable that the liquid crystal panel has higher luminance and that the aperture ratio of the pixel be improved. However, when the aperture ratio is improved, the light-shielding area of the TFT is reduced. When the light-shielding region is reduced and thus the PN junction (specifically, a Lightly Doped Drain (LDD) of the TFT) is irradiated with light, a light leakage current is generated, and the leakage current causes deterioration in image quality such as flicker.

To solve this problem, for example, patent document 1 and patent document 2 disclose electro-optical units (display devices) each having a pair of grooves on both sides of a semiconductor layer and including a light shielding layer in the grooves. This improves the light shielding effect of the semiconductor layer and suppresses the occurrence of leakage current. In addition, patent document 3 discloses an electro-optical unit including an optical surface between an opening region and a non-opening region. The optical surface directs light to the open area as the light deflects off of the open area.

Reference list

Patent literature

Patent document 1: japanese unexamined patent application publication No. 2008-191200

Patent document 2: japanese unexamined patent application publication No. 2004-158518

Patent document 3: japanese unexamined patent application publication No. 2002-

Disclosure of Invention

As described above, basically, there is a trade-off relationship (trade-off) between the aperture ratio and the light-shielding effect, and the liquid crystal panel is expected to have higher luminance and improved image quality.

It is desirable to provide a display device and a projection display apparatus that can achieve higher luminance and improved image quality.

A display device according to an embodiment of the present disclosure includes first and second substrates facing each other with a liquid crystal layer interposed therebetween. The first substrate includes a support substrate, a plurality of scan lines, a plurality of signal lines, a thin film transistor device, and a light shielding film. A plurality of scan lines and a plurality of signal lines are disposed over the support substrate and cross each other, and a thin film transistor device is disposed at each crossing point between the plurality of scan lines and the plurality of signal lines. The light shielding film includes a conductive material and is disposed along a plurality of scanning lines in a plan view.

A projection display apparatus according to an embodiment of the present disclosure includes a light modulation unit that modulates light from a light source. The projection display apparatus includes a display device according to an embodiment of the present disclosure as a light modulation unit.

In the display device according to the embodiment of the present disclosure and the projection display apparatus according to the embodiment of the present disclosure, the light shielding film including the conductive material is formed along the plurality of scanning lines provided on the support substrate in a plan view. The support substrate is included in the first substrate. This can improve the light shielding effect of the TFT device provided for each pixel without restricting the opening of the pixel.

According to the display device of the embodiment of the present disclosure and the projection display apparatus of the embodiment of the present disclosure, the conductive light shielding film is formed along a plurality of scanning lines in a plan view, so that the light shielding effect of the TFT device can be improved without limiting the aperture ratio of the pixel. This can achieve higher brightness and improve image quality.

It should be noted that the above-described effects are not necessarily restrictive, and may include any of the effects described in the present disclosure.

Drawings

Fig. 1 is a schematic plan view of a liquid crystal panel according to a first embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view of the entire liquid crystal panel shown in fig. 1.

Fig. 3 is a schematic view of a cross section of the driving substrate included in the liquid crystal panel taken along a line I-I shown in fig. 1.

Fig. 4 is a schematic diagram of a cross section of the driving substrate included in the liquid crystal panel taken along line II-II shown in fig. 1.

Fig. 5 is a schematic diagram of a cross section of the driving substrate included in the liquid crystal panel taken along the line III-III shown in fig. 1.

Fig. 6A is a sectional view describing a manufacturing method of a driving substrate included in the liquid crystal panel shown in fig. 1.

Fig. 6B is a sectional view of the process following fig. 6A.

Fig. 6C is a sectional view of the process following fig. 6B.

Fig. 6D is a sectional view of the process following fig. 6C.

Fig. 6E is a cross-sectional view of the process following fig. 6D.

Fig. 7 is a schematic diagram of the positional relationship among the scan lines, the gate electrodes, and the through holes.

Fig. 8 illustrates an embodiment of a configuration of a display device including a liquid crystal panel according to the present disclosure.

Fig. 9 shows an embodiment of a configuration of a spatial light modulator.

Fig. 10 shows an embodiment of a circuit configuration of a pixel.

Fig. 11 is a schematic view of a cross section of a driving substrate included in a liquid crystal panel according to a second embodiment of the present disclosure.

Fig. 12 is a sectional view describing a manufacturing method of the driving substrate shown in fig. 11.

Fig. 13 is a schematic view of a cross section of a driving substrate included in a liquid crystal panel according to a third embodiment of the present disclosure.

Fig. 14A is a sectional view describing a manufacturing method of the driving substrate shown in fig. 13.

Fig. 14B is a sectional view showing a process subsequent to fig. 14A.

Fig. 15 is a schematic plan view of a driving substrate included in a liquid crystal panel according to modification 1 of the present disclosure.

Fig. 16 is a schematic view of a section of the drive substrate taken along the line IV-IV shown in fig. 15.

Fig. 17 is a schematic plan view of a driving substrate included in a liquid crystal panel according to modification 2 of the present disclosure.

Fig. 18 is a schematic view of a cross section of the drive substrate taken along the line V-V shown in fig. 16.

Fig. 19 is a schematic plan view of a driving substrate included in a liquid crystal panel according to a fourth embodiment of the present disclosure.

Fig. 20 is a schematic view of a section of the drive substrate taken along the line VI-VI shown in fig. 19.

Fig. 21A is a sectional view describing a manufacturing method of the driving substrate shown in fig. 20.

Fig. 21B is a sectional view showing a process subsequent to fig. 21A.

Fig. 21C is a sectional view showing a process subsequent to fig. 21B.

Fig. 22 is a schematic diagram of a cross section of a driving substrate included in a liquid crystal panel according to modification 3 of the present disclosure.

Fig. 23 is a schematic plan view of a driving substrate included in a liquid crystal panel according to modification 4 of the present disclosure.

Fig. 24 is a schematic view of a cross section of the drive substrate taken along the line VII-VII shown in fig. 23.

Detailed Description

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Note that the description is given in the following order. The following description is merely specific embodiments of the present disclosure, and the present disclosure should not be limited to the following implementations. Further, the present disclosure is not limited to the arrangement, the dimensions, the dimensional ratios, and the like of each component illustrated in the drawings.

1. First embodiment (example of forming light-shielding film along scanning line in plan view)

1-1. configuration of liquid crystal panel

1-2. method for manufacturing drive substrate

1-3. integral configuration of projection display device

1-4. action and Effect

2. Second embodiment (example in which a light-shielding film is formed over a transistor as well)

3. Third embodiment (example in which via holes are formed and scan lines are separated at a time)

4. Modification 1 (embodiment in which scan lines and gate electrodes are directly coupled)

5. Modification 2 (embodiment in which potential is supplied to the gate electrode outside the effective pixel region)

6. Fourth embodiment (example of forming light-shielding film and opening after forming first wiring line)

7. Modification 3 (embodiment in which light shielding film and opening are formed after third wiring line is formed)

8. Modification 4 (embodiment of bottom gate transistor)

<1. first embodiment >

Fig. 1 schematically shows a planar configuration of a display unit (liquid crystal panel 1) according to a first embodiment of the present disclosure. Fig. 2 schematically shows a sectional configuration of the entire liquid crystal panel 1 shown in fig. 1. The liquid crystal panel 1 includes a pixel region 1A and a peripheral region 1B (see fig. 9). In the pixel region 1A, a plurality of pixels P are arranged in a matrix form. The peripheral region 1B surrounds the pixel region 1A. The liquid crystal panel 1 is used as a light modulation unit (spatial light modulation section 130) in a projection display apparatus (projector 100; see fig. 8), for example. In the liquid crystal panel 1, a drive substrate 40A (first substrate) and a counter substrate 50 (second substrate) are opposed to each other, and a liquid crystal cell 60 (liquid crystal layer) is interposed between the drive substrate and the counter substrate. In a plan view, the liquid crystal panel 1 according to the present embodiment includes the conductive light shielding film 15 along the plurality of scanning lines WSL provided in the driving substrate 40A.

It is to be noted that the expression "along the plurality of scanning lines WSL" means that the light shielding film 15 is provided on or in contact with the end face of each scanning line WSL, and the expression "along the plurality of scanning lines WSL" also means that other layers (such as the insulating film 12) are interposed between the scanning lines WSL and the light shielding film 15. In this embodiment mode, an example in which the light shielding film 15 is provided on the scanning line WSL is described.

(1-1. configuration of liquid Crystal Panel)

As described above, the liquid crystal panel 1 includes the liquid crystal cell 60 between the drive substrate 40A and the counter substrate 50 which are opposed to each other. The

alignment films

61 and 62 are provided on respective sides of the liquid crystal cell 60, which are the side of the drive substrate 40A and the side of the counter substrate 50. The periphery of the liquid crystal cell 60 is sealed with a sealant 63. Respective

polarizing plates

42 and 52 are disposed on the side of the drive substrate 40A (surface S2 side) and the side of the counter substrate 50 (surface S1 side). These sides are opposite to the liquid crystal cell 60.

Fig. 3 schematically shows a sectional configuration of the drive substrate 40A taken along a line I-I shown in fig. 1. The driving substrate 40A includes the pixel transistors 13 with respect to two adjacent pixels P. Fig. 4 schematically shows a sectional configuration of the drive substrate 40A taken along a line II-II shown in fig. 1. Fig. 5 schematically shows a sectional configuration of the drive substrate 40A taken along the line III-III. For example, the drive substrate 40A includes a plurality of scanning lines WSL and a plurality of signal lines DTL which extend in the X-axis direction and the Y-axis direction, respectively, and cross each other. The driving substrate 40A includes an opening region X and a non-opening region Y. In the opening region X, incident light is reflected or transmitted. The non-opening region Y is disposed around the opening region X. In the non-opening region Y, a pixel transistor 13 described later and a plurality of scanning lines WSL and a plurality of signal lines DTL intersecting each other are provided. For example, in the drive substrate 40A, the TFT layer 10, the multilayer wiring layer 20, and the pixel electrode 31 are stacked in this order on (the surface S1 side of) the support substrate 41. The TFT layer 10 includes a pixel transistor 13(TFT device) and the like. The multilayer wiring layer 20 includes various wiring lines (wiring layers 21, 22, and 23).

For example, with respect to the TFT layer 10, a plurality of scanning lines WSL are provided on the support substrate 41; the pixel transistor 13 is disposed above each scanning line WSL via the insulating film 12; and an insulating film 14 is provided on the pixel transistor 13. For each pixel P, the corresponding pixel transistor 13 is separated by a via H (see fig. 6B). For example, in a plan view, the through hole H is formed along a region where the plurality of scanning lines WSL are formed. The bottom of the through hole H reaches the support substrate 41. In the present embodiment, the light shielding film 15 is formed on the side surface (surface S3) of the through hole H including the side surface of the pixel transistor 13 in the stacking direction (Z-axis direction); details will be described later. This can effectively reduce the irradiation of the pixel transistor 13 by oblique incident light. The planarization layer 16 is interposed between the pixel transistors 13. The via hole H is filled with the planarization layer 16. The multilayer wiring layer 20 is disposed on the TFT layer 10. The multilayer wiring layer 20 includes wiring layers 21, 22, and 23 in this order with an interlayer insulating layer 26 interposed therebetween. For example, the wiring layers 21, 22, and 23 each include a wiring line configuring a signal line DTL or a common connection line COM (not shown).

The support substrate 41 is, for example, a quartz substrate. For example, the support substrate 41 has a rectangular surface shape (a surface shape parallel to the display screen).

For example, the scanning line WSL extends in the X-axis direction, and a part of the scanning line WSL extends in the Y-axis direction. Specifically, the scanning line WSL extends directly below (opposite region) the LDD region (LDD region 13c) of the pixel transistor 13 or extends to the vicinity thereof. For example, the scanning line WSL includes a metal film of tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta), or the like, or an alloy film thereof. For example, the film thickness (hereinafter simply referred to as thickness) of the scanning line WSL in the Z-axis direction is in the range of 10nm to 500 nm.

For example, the insulating

films

12 and 14 each include silicon oxide (SiO) ₂ ) Film, silicon nitride (Si) ₃ N ₄ ) A film or a laminate thereof. The insulating film 12 is disposed on the substrateAnd (5) tracing on the line WSL. The pixel transistor 13 is provided on the insulating film 12. The insulating film 14 is provided to cover the gate insulating film 13B and the gate electrode 13C of the pixel transistor 13. The thickness of the insulating film 12 is, for example, in the range of 50nm to 1 μm. The thickness of the insulating film 14 is, for example, in the range of 100nm to 1 μm.

The pixel transistor 13 has a Lightly Doped Drain (LDD) structure. The pixel transistor 13 includes a semiconductor layer 13A, a gate electrode 13C, and a gate insulating film 13B. The gate electrode 13C applies an electric field to the semiconductor layer 13A (particularly, the channel region 13A). The gate insulating film 13B insulates the semiconductor layer 13A and the gate electrode 13C from each other. The semiconductor layer 13A includes a channel region 13A, LDD regions 13c, and source-drain regions 13 b. The channel region 13a is provided at a position opposite to the gate electrode 13C. LDD regions 13c are provided on respective sides of the channel region 13 a. The source-drain regions 13b are disposed outside the respective LDD regions 13 c. In the pixel transistor 13 according to the present embodiment, the gate electrode 13C is electrically coupled to the scanning line WSL via the light shielding film 15; one of the source-drain regions 13b is electrically coupled to the signal line DTL; and the other of the source-drain regions 13b is electrically coupled to the pixel electrode 31.

As described above, for example, the channel region 13A, the source-drain region 13b, and the LDD region 13c are provided in the same layer (the semiconductor layer 13A). For example, the semiconductor layer 13A includes an amorphous silicon film, a polysilicon film, or the like. In the case where the semiconductor layer 13A is configured of a polysilicon film, for example, an impurity such as an n-type impurity is doped into the source-drain region 13b, so that the semiconductor layer 13A has a lower resistance. Impurities are doped into the LDD regions 13c so that the LDD regions 13c have a lower impurity concentration than the source-drain regions 13 b.

The gate insulating film 13B serves to electrically insulate the semiconductor layer 13A and the gate electrode 13C from each other. For example, the gate insulating film 13B includes a silicon oxide film, a silicon nitride film, or the like. The gate insulating film 13B is formed by, for example, a thermal oxidation method or a Chemical Vapor Deposition (CVD) method.

The gate electrode 13C is provided across the semiconductor layer 13A in the X-axis direction via the gate insulating film 13B. In the semiconductor layer 13A, a region opposed to the gate electrode 13C is a channel region 13A. The gate electrode 13C includes a conductive material. Specifically, for example, the gate electrode 13C includes an amorphous silicon film, a polycrystalline silicon film, a metal film of tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta), or the like, or an alloy film thereof. In addition, as shown in fig. 3, the gate electrode 13C may have a structure in which a conductive film 13d and a metal film 13e (or an alloy film) are stacked. The conductive film 13d includes a conductive material such as polysilicon, amorphous silicon, or the like. The metal film 13e is selected from the above-described metal films. For example, the thickness of the gate electrode 13C is preferably 10nm or more. For example, the upper limit of the thickness of the gate electrode 13C is 1 μm or less.

Note that an example in which the semiconductor layer 13A extends in the Y-axis direction in the pixel transistor 13 according to the present embodiment has been described above. However, this is not restrictive. The pixel transistor 13 may have a configuration in which the semiconductor layer 13A extends in the X-axis direction. However, in the case where the signal lines DTL extend in the Y-axis direction as described in this embodiment, the semiconductor layer 13A extending in the Y-axis direction realizes excellent layout efficiency.

The light shielding film 15 is for reducing the irradiation of the pixel transistor 13 with oblique incident light. The light shielding film 15 is formed on the side surface (surface S3) of the through-hole H formed in the process of manufacturing the drive substrate 40A. As described above, the via hole H is formed along the region where the plurality of scanning lines WSL and the plurality of signal lines DTL are formed in plan view. Specifically, the periphery of the through hole H is formed to overlap the scanning line WSL. In this way, the light shielding film 15 is formed to surround the pixel transistor 13 in a plan view. In addition, the light shielding film 15 is provided so as to extend between the semiconductor layer 13A and the gate electrode 13C and on both sides. Specifically, the light shielding film 15 is continuously formed from above the scanning line WSL to the upper end of the insulating film 14 in the stacking direction (Z-axis direction) of the pixel transistors 13. For example, the light shielding film 15 has a light shielding effect and includes a conductive material. Specific examples of the material include tungsten (W), molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and the like. The light shielding film 15 is formed using a conductive material so that the gate electrode 13C and the scanning line WSL are electrically coupled to each other via the light shielding film 15, as shown in fig. 4. For example, the thickness of the light-shielding film 15 is preferably in the range of 5nm to 200 nm.

Note that fig. 1 shows an embodiment in which the light shielding film 15 is continuously formed on the periphery of the scanning line WSL in a plan view. However, this is not restrictive. It is sufficient to form the light shielding film 15 at least at the position of the PN junction of the pixel transistor 13. Specifically, it is sufficient to form the light-shielding film 15 on both sides of the LDD region 13 c. It is desirable to form the light shielding film 15 around the pixel transistors 13 including the periphery thereof. Therefore, for example, it is not necessary to form the light shielding film 15 in a region corresponding to the scanning line WSL provided between the adjacent pixel transistors 13. In other words, the light shielding films 15 may be intermittently formed along the scanning lines WSL provided in the drive substrate 40A in a plan view.

Similar to the insulating

films

12 and 14, the planarization layer 16 includes SiO ₂ Film, Si ₃ N ₄ A film or a laminate thereof. The planarization layer 16 fills the via hole H and planarizes the surface of the TFT layer 10. Therefore, although fig. 3 and the like show an embodiment in which the planarizing layer 16 fills the through hole H and covers the insulating film 14, the planarizing layer 16 is not necessarily formed on the insulating film 14. The thickness of the planarization layer 16 depends on the thickness of each component included in the pixel transistor 13, the scan line 11, and the like. For example, the thickness of the planarization layer 16 from the support substrate 41 is preferably in the range of 200nm to 2 μm.

For example, the wiring layers 21, 22, and 23 configure a signal line DTL and a common connection line COM (not shown), with an interlayer insulating layer 26 interposed therebetween. For example, the wiring layers 21, 22, and 23 each include a metal film of aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta), or the like, or an alloy film thereof. For example, the wiring layers 21, 22, and 23 are electrically coupled via the

contacts

24 and 25 and the like in an appropriate manner. For example, the thickness of each of the wiring layers 21, 22, and 23 is preferably in the range of 100nm to 1 μm.

The signal line DTL extends in the Y-axis direction, for example, and is disposed directly above the semiconductor layer 13A (such as the opposite region of the wiring line 21A). In the source-drain region 13B of the semiconductor layer 13A, the signal line DTL is electrically coupled to the semiconductor layer 13A via a contact 17 penetrating the planarization layer 16, the insulating film 14, and the gate insulating film 13B.

Similar to the insulating

films

12 and 14 and the planarizing layer 16,the interlayer insulating layer 26 comprises SiO ₂ Film, Si ₃ N ₄ A film or a laminate thereof. The interlayer insulating layer 26 insulates the wiring layers 21, 22, and 23 from each other, and is appropriately planarized. The thickness of the interlayer insulating layer 26 varies depending on the number of wiring layers stacked. For example, the film thickness between the wiring layers (the thickness between the wiring layer 21 and the wiring layer 22, or the thickness between the wiring layer 22 and the wiring layer 23) is preferably in the range of 200nm to 1 μm.

The pixel electrode 31 is provided for each pixel P. The pixel electrode 31 includes, for example, a transparent conductive film. Examples of the material of the transparent conductive film include oxide semiconductors such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), and Indium Gallium Zinc Oxide (IGZO).

For example, the counter substrate 50 has a configuration in which a support substrate 51 and a common electrode 53 are stacked. The common electrode 53 is provided on the surface (surface S2 side) of the support substrate 51 opposite to the liquid crystal cell 60.

The support substrate 51 includes, for example, a quartz substrate. For example, a color filter and a light-shielding layer (black matrix layer), not shown, are provided in the support substrate 51 and, for example, are covered with an overcoat film (not shown). The common electrode 53 is provided on the overcoat film.

For example, the common electrode 53 serves as an electrode common to the respective pixels P. The common electrode 53 supplies a voltage to the liquid crystal cell 60 together with the pixel electrode 31. The common electrode 53 includes, for example, the above-described transparent conductive film similarly to the above-described pixel electrode 31.

The liquid crystal cell 60 has a function of controlling the transmittance of light passing through the liquid crystal cell 60 according to the picture voltage supplied through the pixel electrode 31 and the common electrode 53. For example, the liquid crystal cell 60 includes liquid crystals that drive display in a Vertical Alignment (VA) mode, a Twisted Nematic (TN) mode, an Electrically Controlled Birefringence (ECB) mode, a Fringe Field Switching (FFS) mode, an in-plane switching (IPS) mode, or the like. The liquid crystal material of the liquid crystal cell 60 is not particularly limited.

The

alignment films

61 and 62 are each used to control the alignment of the liquid crystal cell 60. For example, the

alignment films

61 and 62 each include an inorganic material film such as a silicon oxide film. For example, the thickness of each of the

alignment films

61 and 62 is in the range of about 50nm to about 360 nm. For example, the

alignment films

61 and 62 are each formed by a vapor deposition method. The alignment film 61 covers the pixel electrode 31, and the alignment film 62 covers the common electrode 53.

The sealant 63 is used to seal the liquid crystal cell 60 between the driving substrate 40A and the counter substrate 50. For example, the sealant 63 includes an insulating material such as a polymer material. Specific examples of the sealant 63 include epoxy resin and acrylic resin.

For example, the

polarizing plates

42 and 52 are disposed in a crossed nicols arrangement. The

polarizing plates

42 and 52 each transmit only light (polarized light) in a specific vibration direction.

(1-2. method for manufacturing drive substrate)

The drive substrate 40A included in the liquid crystal panel 1 according to the present embodiment can be manufactured, for example, as follows.

Fig. 6A to 6E illustrate a manufacturing method of the driving substrate 40A in the order of processing. First, as shown in fig. 6A, for example, a W film is formed on the support substrate 41 by a CVD method or a sputtering method, and then the scanning line 11 is formed by a patterning process. Next, a silicon oxide film is formed on the support substrate 41 and the scanning lines 11 by, for example, a CVD method, thereby forming the insulating film 12. At this time, the surface of the insulating film 12 is planarized by CMP or the like as necessary. Next, a polysilicon film is formed on the insulating film 12 by, for example, a CVD method or the like, and then a crystallization process is performed as necessary. Thereafter, the semiconductor layer 13A is formed by a patterning process. Subsequently, for example, a silicon oxide film is formed on the insulating film 12 and the semiconductor layer 13A by a thermal oxidation method or a CVD method, thereby forming the gate insulating film 13B. Next, impurities are implanted into the semiconductor layer 13A as necessary to form a channel region 13A. Note that the impurity may be implanted before the gate insulating film 13B is formed. Subsequently, for example, a polysilicon film and a W film are formed on the gate insulating film 13B by a CVD method, and then the gate electrode 13C is formed by a patterning process. The gate electrode 13C includes a conductive film 13d and a metal film 13e stacked. Thereafter, as necessary, an impurity is implanted into the semiconductor layer 13A, and thermal annealing is performed to perform impurity activation, thereby forming an LDD region 13c and a source-drain region 13 b. Next, for example, a silicon oxide film is formed on the gate insulating film 13B and the gate electrode 13C by a CVD method, thereby forming the insulating film 14. At this time, the surface of the insulating film 14 is planarized by CMP or the like as necessary.

Next, as illustrated in fig. 6B, a resist film 81 is formed on the insulating film 14 to cover the non-opening region Y. The resist film 81 serves as a mask to form the through-hole H by, for example, Reactive Ion Etching (RIE) or wet etching. Note that at this time, as shown in fig. 7, it is preferable that the distance between the edge of the via hole H (via hole edge) and the edge of the gate electrode 13C (the amount of overlap with the via hole H) be about-0.2 μm or more with respect to the edge of the via hole H close to the gate electrode 13C provided at each intersection between the plurality of scanning lines WSL (scanning lines 11) and the plurality of signal lines DTL. Here, "positive (+)" means a case where the gate electrode 13C and the via hole H overlap with each other. Therefore, even when alignment deviation occurs between the scanning line 11 and the gate electrode 13C, the scanning line 11 and the gate electrode 13C can be electrically coupled to each other via the light shielding film 15 at any one of the four corners of the rectangular gate electrode 13C.

Thereafter, as shown in fig. 6C, for example, a W film 15a is continuously formed on the upper surface of the non-opening region Y, on the side surfaces of the through-holes H, and on the bottom surfaces of the through-holes H by, for example, a CVD method, a sputtering method, an Atomic Layer Deposition (ALD) method, or the like. The W film 15a functions as a light shielding film 15.

Next, as shown in fig. 6D, the W film 15a is processed by RIE, for example. Specifically, the W film 15a is selectively removed at a position other than the side surface of the through hole H. Therefore, the light shielding film 15 is formed only on the side surface (surface S3) of the through hole H. Note that fig. 6D and the like show an embodiment in which the thickness of the light shielding film 15 from the upper end to the lower end is constant in the X-axis direction. However, this is not restrictive. For example, in the case of processing the W film by RIE as described above, the thickness of the upper edge of the light shielding film 15 becomes gradually thinner toward the upper end due to the manufacturing process using RIE or the like.

Subsequently, as shown in fig. 6E, the via hole H is filled by a CVD method, for example, a silicon oxide film is formed to cover the insulating film 14, thereby forming the planarization layer 16. At this time, the surface of the planarizing layer 16 is planarized by CMP or the like as necessary. Next, the contact 17. The contact 17 penetrates the planarization layer 16, the insulating film 14, and the gate insulating film 13B, and is in contact with the semiconductor layer 13A. Subsequently, an aluminum (Al) film is formed by, for example, a CVD method, and then the wiring layer 21 is formed by a patterning process. The wiring layer 21 includes

wiring lines

21A and 21B. Next, for example, a silicon oxide film is formed on the planarization layer 16 and the wiring layer 21 by, for example, a CVD method.

Thereafter, similarly to the above-described method, the wiring layers 22 and 23, the silicon oxide film, the wiring layer 21 (wiring line 21A), and the

contacts

24 and 25 are formed. The

contacts

24 and 25 electrically couple the wiring layer 21 (wiring line 21A) and the wiring layer 22 to each other, the wiring layer 22 and the wiring layer 23 to each other, and the wiring layer 23 and the pixel electrode 31 to each other. Note that in this embodiment, a contact for electrically coupling the wiring layer 22 and the wiring layer 23 is not shown. In this way, the multilayer wiring layer 20 is formed. Finally, the pixel electrode 31 is formed on the interlayer insulating layer 26, thereby realizing the drive substrate 40A shown in fig. 3 and the like.

(1-3. integral configuration of projection display device)

Fig. 8 shows an embodiment of the overall configuration of a projector 100 including a liquid crystal panel 1 according to the present disclosure. For example, projector 100 is a three CCD transmissive projector. For example, the projector 100 includes a light emitting section 110, an optical path branching section 120, a spatial light modulation section 130, a combining section 140, and a projecting section 150.

The light emitting section 110 supplies a light flux that irradiates the irradiation target surface of the spatial light modulation section 130. The light emitting section 110 includes, for example, a white light source lamp and a reflector. The reflector is arranged behind the lamp. The light emitting portion 110 may include, as necessary, some optical device in a region through which the light 111 from the lamp passes (on the optical axis AX). For example, a filter and an optical integrator may be provided on the optical axis AX of the lamp in this order from the lamp side. The filter darkens light other than visible light from the lamp light 111. The optical integrator equalizes the illuminance distribution on the irradiation target surface of the spatial light modulation section 130.

The optical path branching section 120 separates the light 111 output from the light emitting section 110 into a plurality of color beams having different wavelength bands, and guides the respective color beams to the irradiation target surface of the spatial light modulation section 130. For example, as shown in fig. 8, the optical path branching section 120 includes a single cross mirror 121, two mirrors 122, and two mirrors 123. The cross mirror 121 separates the light 111 output from the light emitting section 110 into a plurality of color beams having different wavelength bands, and causes the color beams to have respective branch optical paths. For example, the cross mirror 121 is disposed on the optical axis AX. The cross mirror 121 has a configuration in which two mirrors having different wavelength selectivities are coupled to intersect each other. The

mirrors

122 and 123 reflect the color light beams (red light 111R and blue light 111B in fig. 8) branched by the cross mirror 121. The

mirrors

122 and 123 are disposed at positions different from the optical axis AX. The mirror 122 is provided to guide light (red light 111R in fig. 8) to the irradiation target surface of the spatial light modulation section 130R. The light is reflected by one mirror included in the cross mirror 121 toward a direction intersecting the optical axis AX. The mirror 123 is provided to guide light (blue light 111B in fig. 8) to the irradiation target surface of the spatial light modulation section 130B. The light is reflected by another mirror included in the cross mirror 121 toward another direction intersecting the optical axis AX. Among the light 111 output from the light emitting section 110, light (green light 111G in fig. 8) transmitted through the cross mirror 121 and traveling on the optical axis AX is incident on the irradiation target surface of the spatial light modulation section 130G disposed on the optical axis AX.

For example, the spatial light modulation section 130 is configured by using the liquid crystal panel 1 shown in fig. 2 and the like. The spatial light modulation section 130 modulates a plurality of color beams for each color beam in accordance with a picture signal Din input from an information processing unit, not shown, to generate a modulated beam for each color beam. For example, spatial light modulation section 130 includes spatial light modulation section 130R, spatial light modulation section 130G, and spatial light modulation section 130B. The spatial light modulation section 130R modulates the red light 111R. The spatial light modulation section 130G modulates the green light 111G. The spatial light modulation section 130B modulates the blue light 111B.

The spatial light modulation section 130R is provided in a region opposed to the surface of the combining section 140. The spatial light modulation section 130R modulates the incident red light 111R based on the picture signal Din, generates red image light 112R, and outputs the red image light 112R to the surface of the combining section 140 disposed behind the spatial light modulation section 130R. The spatial light modulation section 130G is provided at a region opposite to the other surface of the combining section 140. The spatial light modulation section 130G modulates the incident green light 111G based on the picture signal Din, generates green image light 112G, and outputs the green image light 112G to the other surface of the combining section 140 disposed behind the spatial light modulation section 130R. The spatial light modulation section 130B is disposed in a region opposite to the other surface of the combining section 140. The spatial light modulation section 130B modulates the incident blue light 111B based on the picture signal Din, generates blue image light 112B, and outputs the blue image light 112B to the other surface of the combining section 140 disposed behind the spatial light modulation section 130R.

The combining section 140 combines the plurality of modulated light beams and generates image light. For example, the combining section 140 is disposed on the optical axis AX. For example, the combining unit 140 is a cross prism configured by four connected prisms. For example, two selective reflection surfaces are formed on the joining surface of the prism. The two selective reflection surfaces have different wavelength selectivities by using a multilayer interference film or the like. For example, one of the selective reflection surfaces reflects the red image light 112R output from the spatial light modulation section 130R in a direction parallel to the optical axis AX, and guides the red image light 112R to the projection section 150. In addition, for example, the other of the selective reflection surfaces reflects the blue image light 112B output from the spatial light modulation section 130B in a direction parallel to the optical axis AX and guides the blue image light 112B to the projection section 150. In addition, the green image light 112G output from the spatial light modulation section 130G is transmitted through the two selective reflection surfaces and travels toward the projection section 150. As a result, the combining section 140 serves to combine the respective image light beams generated by the spatial

light modulating sections

130R, 130G, and 130B, thereby generating the image light 113 and outputting the generated image light 113 to the projecting section 150.

The projection section 150 projects the image light 113 output from the combining section 140 on the screen 200 to display an image. The projection section 150 is disposed on the optical axis AX, for example, and includes a projection lens, for example.

Fig. 9 shows an example of the overall configuration of the spatial

light modulation sections

130R, 130G, and 130B. For example, each of the spatial

light modulation sections

130R, 130G, and 130B includes the liquid crystal panel 1 described above and the drive circuit 70 that drives the liquid crystal panel 1. The drive circuit 70 includes a display control section 71, a data driver 72, and a gate driver 73.

The liquid crystal panel 1 includes a pixel region 1A and a peripheral region 1B thereof. In the pixel region 1A, a plurality of pixels P are arranged in a matrix form. Each pixel P is actively driven by the data driver 72 and the gate driver 73, thereby causing the liquid crystal panel 1 to display an image based on a picture signal Din input from the outside.

The liquid crystal panel 1 includes a plurality of scanning lines WSL, a plurality of signal lines DTL, and a plurality of common connection lines COM. The plurality of scanning lines WSL extend in the row direction. The plurality of signal lines DTL extend in the column direction. The plurality of common connection lines extend in a row direction or in a column direction. The pixels P are disposed to correspond to intersections between the signal lines DTL and the scanning lines WSL. Each signal line DTL is coupled to an output terminal (not shown) of the data driver 72. Each scanning line WSL is coupled to an output terminal (not shown) of the gate driver 73. For example, each common connection line COM is coupled to an output terminal (not shown) of a circuit that outputs a fixed potential.

For example, the display control section 71 stores and holds the picture signal Din to be supplied in the frame memory for each screen (for each frame display). In addition, for example, the display control section 71 has a function of controlling to allow the gate driver 73 and the data driver 72 that drive the liquid crystal panel 1 to operate in conjunction with each other. Specifically, for example, the display control section 71 supplies the scan timing control signal to the data driver 72, and supplies the display timing control signal for one horizontal line and the image signal to the data driver 72 based on the image signal held in the frame memory.

For example, the data driver 72 supplies the picture signal Din of one horizontal line to each pixel P as a signal voltage. The picture signal Din has been supplied from the display control section 71. Specifically, for example, the data driver 72 supplies a signal voltage corresponding to the picture signal Din to the corresponding pixel P via the corresponding signal line DTL. The pixels P are included in one horizontal line selected by the gate driver 73.

For example, the gate driver 73 has a function of selecting the driving target pixel P in accordance with a scan timing control signal supplied from the display control section 71. Specifically, for example, the gate driver 73 applies a selection pulse to the gate electrode 13C of the pixel transistor 13 of the pixel P via the scanning line WSL, thereby selecting the pixel P of one line in the matrix provided in the pixel region 1A as a driving target. Thereafter, the pixels P display one horizontal line according to the signal voltage supplied from the data driver 72. In this way, for example, the gate driver 73 sequentially scans each horizontal line in time series and displays on the entire display area.

Next, a circuit configuration of the pixel P is described. Fig. 10 shows an embodiment of the circuit configuration of the pixel P. The pixel P includes a liquid crystal device 2 and a pixel circuit 3 that drives the liquid crystal device 2. The liquid crystal device 2 and the pixel circuit 3 are disposed so as to correspond to an intersection between the scanning line WSL and the signal line DTL. The liquid crystal device 2 includes a liquid crystal cell 60, a pixel electrode 31, and a common electrode 53. The pixel electrode 31 and the common electrode 53 are interposed in the liquid crystal cell 60. The pixel circuit 3 includes a transistor (pixel transistor 13) and a storage capacitor 27. The transistor writes a signal voltage into the liquid crystal device 2. The storage capacitor 27 holds a voltage written in the liquid crystal device 2. The storage capacitor 27 includes a pair of capacitor electrodes that face each other with a predetermined gap interposed therebetween. One capacitor electrode is coupled to the source-drain region 13b of the semiconductor layer 13A, and the other capacitor electrode is coupled to the common connection line COM.

(1-4. action and Effect)

As described above, it is highly desirable that the liquid crystal panel have higher luminance. In order to achieve higher luminance, the aperture ratio of the pixel needs to be improved. However, when the aperture ratio is improved, the light-shielding area of the TFT is reduced. In particular, in the case of using a liquid crystal panel as a light modulation unit (light valve) of a projection display apparatus, strong light from a light source causes a leakage current, and this causes deterioration in image quality such as flicker.

As described above, basically, there is a trade-off relationship between the aperture ratio and the light shielding effect. A liquid crystal panel having a light blocking effect while having an improved aperture ratio has been developed. For example, an electro-optical cell that prevents light from entering a semiconductor layer has been developed by providing a gate electrode on the semiconductor layer and embedding the gate electrode in both sides of the semiconductor layer. The gate electrode also serves as a contact to the scan line. However, since a contact realized by the gate electrode is formed in the non-opening area, it is difficult for the electro-optical cell to improve the opening ratio. In addition, since the embedded gate electrode is formed at portions in both sides of the semiconductor layer, the portion without the embedded gate electrode still has a low light shielding effect.

Alternatively, for example, a display unit having an improved light-shielding effect has been developed by further providing an intermediate light-shielding layer between the TFT and a light-shielding layer provided in the non-opening region and by extending the intermediate light-shielding layer to a groove formed on the periphery of the semiconductor layer. However, the display unit has a disadvantage in improving the aperture ratio due to the non-opening area having the groove in which the intermediate light-shielding layer extends. In addition, it is difficult to control the depth of the groove, and there is a gap between the groove and the scan line disposed below the TFT. Therefore, light may be incident through the gap.

In addition, for example, an electro-optical unit having an improved light blocking effect and improved light utilization efficiency has been developed by providing an optical surface between an opening region and a non-opening region. The optical surface reflects the obliquely incident light to the opening region side. However, the optical surface includes a light transmissive film such as SiN. Therefore, it is difficult for the electro-optical cell to achieve a significant light shielding effect.

Meanwhile, the liquid crystal panel 1 according to the present embodiment includes the light shielding film 15 extending in the stacking direction (Z-axis direction) in plan view to cover the side surfaces of the pixel transistors 13 along the plurality of scanning lines WSL (scanning lines 11) over which the semiconductor layer 13A and the gate electrodes 13C are disposed. The semiconductor layer 13A and the gate electrode 13C are included in the pixel transistor 13. In this way, the light-shielding film 15 is formed around the pixel transistor 13, so that the path of obliquely incident light entering the pixel transistor 13 (particularly the LDD region 13c in the semiconductor layer 13A) can be significantly reduced. In other words, the light shielding effect of the pixel transistor 13 can be improved. In addition, the light shielding film 15 includes a conductive material, and thus the scanning line 11 and the gate electrode 13C can be electrically coupled to each other without providing a contact between the scanning line 11 and the gate electrode 13C. This can improve the aperture ratio.

As described above, according to the present embodiment, the light shielding film 15 is formed along the plurality of scanning lines WSL in plan view, thereby allowing the light shielding film 15 to be formed around the pixel transistors 13. This improves the light shielding effect of the pixel transistor 13, so that the image quality can be improved. In addition, the light shielding film 15 includes a conductive material, and thus the scanning lines 11 and the gate electrodes 13C can be electrically coupled to each other without providing a contact between the scanning lines 11 and the gate electrodes 13C. This can improve the aperture ratio, so that higher luminance can be achieved. In other words, this can achieve higher luminance and improve image quality.

Next, second to fourth embodiments and modifications 1 to 4 according to the present disclosure are described. Note that the same components as those of the first embodiment are denoted by the same reference symbols as those of the first embodiment, and descriptions thereof are omitted.

< 2> second embodiment

Fig. 11 shows a sectional configuration of a driving substrate 40B included in the liquid crystal panel 1 according to the second embodiment of the present disclosure. In a plan view, the drive substrate 40B according to the present embodiment has a configuration in which the light shielding film 15 (light shielding film 15A) is provided along the plurality of scanning lines WSL provided in the drive substrate 40A, and the light shielding film 15 (light shielding film 15B) is also provided above the pixel transistors 13. It should be noted that fig. 11 schematically shows a sectional configuration of the drive substrate 40B with respect to two adjacent pixels P including the pixel transistor 13, taken along the line I-I shown in fig. 1.

Fig. 12 shows a process for manufacturing the drive substrate 40B shown in fig. 11. Similarly to the drive substrate 40A according to the first embodiment, for example, the W film 15a is formed on the side surfaces of the via hole H and the insulating film 14 (the upper surface of the non-opening region Y) provided above the pixel transistor 13. The W film 15A functions as a light shielding film 15 (

light shielding films

15A and 15B). Next, as shown in fig. 12, a resist film 82 is formed. The resist film 82 covers the side surface and the upper surface of the W film 15a and has a desired pattern. Specifically, the resist film 82 has an opening 82H at a position where the contact 17 is formed. The contact 17 electrically couples the wiring layer 21 and the semiconductor layer 13A to each other. Thereafter, the W film 15a is processed by RIE, for example, and then the drive substrate 40B is manufactured by using a method similar to the first embodiment. In this way, the driving surface 40B including the light shielding film 15 covering the side surfaces of the through hole H and the portion above the pixel transistor 13 is realized.

As described above, according to the present embodiment, the light shielding film 15 is formed to cover the pixel transistor 13 and the side surface of the portion above the pixel transistor 13. This can prevent stray light traveling in the drive substrate 40B from entering the pixel transistor 13. This further improves the light shielding effect of the pixel transistor 13.

Note that, in the first embodiment, an example has been described in which the light shielding film 15 is provided from the upper surface of the scanning line 11 to the upper surface of the insulating film 14. However, this is not restrictive. For example, as shown in fig. 11, the light shielding film 15 may be formed to cover the upper surface of the support substrate 41 to the end surface (side surface) of the scanning line 11.

< 3> third embodiment

Fig. 13 shows a sectional configuration of a driving substrate 40C included in the liquid crystal panel 1 according to the third embodiment of the present disclosure. The drive substrate 40C according to the present embodiment has a configuration in which end faces of the scanning lines 11, the insulating film 12, and the insulating film 14 are disposed on the same plane, and the light shielding film 15 is formed on the end face between the upper surface of the support substrate 41 and the upper end of the insulating film 14. It should be noted that fig. 13 schematically shows a sectional configuration of the drive substrate 40C with respect to two adjacent pixels P including the pixel transistor 13, taken along the line I-I shown in fig. 1.

Fig. 14A and 14B illustrate part of a process for manufacturing the drive substrate 40C illustrated in fig. 13. First, as shown in fig. 14A, the W film 11a is formed on the support substrate 41 by, for example, a CVD method, a sputtering method, or the like. The W film 11a serves as the scanning line 11. Thereafter, the patterning process may be performed without the W film 11a being separated in the non-opening area. Subsequently, a silicon oxide film 12a serving as an insulating film 12 is formed on the W film 11a, and then a semiconductor layer 13A is formed similarly to the first embodiment. After that, for example, a silicon oxide film 13x serving as the gate insulating film 13B, a gate electrode 13C, and, for example, a silicon oxide film 14a serving as the insulating film 14 are formed in this order.

Next, as shown in fig. 14B, a resist film 83 is formed in the corresponding region on the insulating film 14 to cover the non-opening region Y. The through hole H reaching the support substrate 41 is formed by, for example, RIE or wet etching by using the resist film 81 as a mask. At this time, the W film 11a serving as the scanning line 11 is also separated in the non-opening region Y. After that, the drive substrate 40C is manufactured by using a method similar to that of the first embodiment. In this way, the drive substrate 40C is realized in which the end faces of the scanning line 11, the insulating film 12, and the insulating film 14 are disposed on the same plane.

As described above, according to the present embodiment, the through hole H is formed by etching the scanning line 11, the insulating film 12, and the insulating film 14 at one time, so that the conductive light-shielding film 15 is formed on the side surface of the through hole H. Therefore, the side surfaces of the light shielding film 15 on the scanning line 11, the insulating film 12, and the insulating film 14 are formed on the same plane (surface S3). This makes it possible to electrically couple the scanning lines 11 and the gate electrodes 13C to each other through the light shielding film 15 in the case of misalignment. Therefore, it is not necessary to consider the alignment deviation between the through hole H and the scanning line 11. This can further improve the aperture ratio.

<4. modification 1>

Fig. 15 schematically shows a planar configuration of a driving substrate 40D included in the liquid crystal panel 1 according to a modification of the present disclosure. Fig. 16 shows a cross-sectional configuration taken along the line IV-IV shown in fig. 15. In the drive substrate 40D according to the present modification, the gate electrode 13C extends in the X-axis direction and is continuously formed between the adjacent pixels P. Specifically, modification 1 differs from the foregoing first embodiment in that a gate electrode 13C is opposed to the scanning line 11 and extends in the X-axis direction above the scanning line 11, and the gate electrode 13C is electrically coupled to the scanning line 11 via a through hole 13H formed between adjacent pixels P.

Note that, similarly to the first embodiment, the through hole 13H is formed by forming the scanning line 11, the insulating film 12, the semiconductor layer 13A, and the gate insulating film 13B on the support substrate 41; patterning a resist film on the gate insulating film 13B; and RIE or the like is performed while using the resist film as a mask. After the formation of the via hole 13H, the via hole 13H is filled, for example, by a CVD method, similarly to the first embodiment, and a polysilicon film, for example, is formed on the gate insulating film 13B. Subsequently, the gate electrode 13C is formed by a patterning process. Thereafter, the driving substrate 40D is realized by a process similar to the first embodiment.

As described above, in the present modification, the scan line 11 and the gate electrode 13C are coupled to each other at a position away from the semiconductor layer 13A without using the light shielding film 15. This can couple the scan line 11 and the gate electrode 13C to each other more easily than the first embodiment. In addition, the through hole 13H does not need to have a light shielding effect. This can improve the degree of freedom of layout, and thus can further improve the aperture ratio.

Note that, in the present modification, the scanning line 11 directly supplies the potential of the gate electrode 13C. Therefore, the light shielding film 15 may have any potential, and may be, for example, electrically floating. Therefore, the distance from the edge of the via hole H to the edge of the gate electrode 13C (the amount of overlap with the via hole H) may be less than-0.2 μm in plan view. The through hole H has a side surface on which the light shielding film 15 is formed.

<5. modification 2>

Fig. 17 schematically shows a planar configuration of a driving substrate 40E included in the liquid crystal panel 1 according to a modification of the present disclosure. Fig. 18 shows a cross-sectional configuration taken along the line V-V shown in fig. 17. In the present modification, the gate electrode 13C is electrically coupled to the wiring layer 21 in the peripheral region 1B via the contact 18. The potential is supplied from the wiring layer 21.

Note that, in the present modification, the light shielding film 15 has the same potential as the scanning line 11. In addition, the distance from the edge of the via hole H to the edge of the gate electrode 13C (the amount of overlap with the via hole H) is less than-0.2 μm in plan view. The through hole H has a side surface on which the light shielding film 15 is formed.

As described above, in the present modification, the gate electrode 13C and the wiring layer 21 are coupled to each other via the contact 18 in the peripheral region 1B, and a potential is supplied from the wiring layer 21 to the gate electrode 13C. This can omit the process of coupling the scan line 11 and the gate electrode 13C to each other, compared to the foregoing modification 1.

In addition, in the present modification, the scanning line WSL (scanning line 11) serves as a backside light-shielding film of the pixel transistor 13. Therefore, by making the scanning line 11 have an optimum potential for the holding characteristic of the pixel transistor 13, the leak current of the pixel transistor 13 caused by the electric field can be reduced, so that the picture quality can be further improved. Note that the scanning lines 11 and the light shielding films 15 according to the present modification may have floating potentials, respectively; however, fixing the potential to a certain potential may reduce the effect of capacitive coupling. This may further improve the image quality.

<6. fourth embodiment >

Fig. 19 schematically shows a planar configuration of a driving substrate 40F included in the liquid crystal panel 1 according to the fourth embodiment of the present disclosure. Fig. 20 schematically shows a sectional configuration with respect to two adjacent pixels P including the pixel transistor 13, taken along the line VI-VI shown in fig. 19. The drive substrate 40F according to the present embodiment has a configuration in which the light shielding film 15 is continuously provided from the upper surface of the support substrate 41 to the upper end of the wiring layer 21 (specifically, the wiring line 21A), and in which the semiconductor layer 13A and the wiring line 21A are electrically coupled to each other via the light shielding film 15. In addition, the scanning lines WSL are separated in the X-axis direction for each pixel P.

Fig. 21A to 21C show part of a process for manufacturing the drive substrate 40F shown in fig. 19. First, a method similar to that for driving the substrate 40A according to the first embodiment is used until the insulating film 14 is formed. Note that at this time, the semiconductor layer 13A is subjected to patterning so that one end face of the semiconductor layer 13A is located outside the end face of the scanning line 11 in the Y-axis direction. Next, as shown in fig. 21A, the contact 17 is formed to penetrate the insulating film 14 and the gate insulating film 13B. Subsequently, an aluminum (Al) film is formed by, for example, a CVD method, and then the wiring layer 21 (

wiring lines

21A and 21B) is formed by a patterning process. At this time, the end face of the wiring line 21A on the open region X side is located outside the end face of the scan line 11 below the wiring line 21A, and the end face of the wiring line 21A is located on the same plane as the end face of the semiconductor layer 13A or located inside the end face of the semiconductor layer 13A. Next, a resist film 84 is formed on the insulating film 14 and the wiring layer 21. At this time, the end face of the wiring line 21A on the open region X side remains exposed. Next, the through hole H is formed by RIE, wet etching, or the like while using the resist film 84 and the wiring line 21A as a mask. In this way, the end face of the semiconductor layer 13A is exposed, and the side surface (surface S3A) is formed on the same plane as the end face of the wiring layer 21 (wiring line 21A). Note that, at the side surface (surface S3B) on the wiring line 21B side, the end face of the semiconductor layer 13A is covered with the gate insulating film 13B.

Subsequently, the resist film 84 is removed, and then the W film 15a is formed on the upper surface of the non-opening area Y, on the side surface of the through hole H, and on the bottom surface of the through hole H continuously by, for example, a CVD method, as shown in fig. 21B. The W film 15a functions as a light shielding film 15. Next, as shown in fig. 21C, the light shielding film 15 is formed by removing the W film 15a at a portion other than the end face of the wiring layer 21 and the side surface of the through hole H by RIE, for example. In this way, the semiconductor layer 13A and the wiring line 21A are electrically coupled via the light shielding film 15. Note that the wiring line 21A functions as a signal line DTL, so that the potential of the signal line DTL can be supplied to the semiconductor layer 13A.

After that, the via hole H is filled by, for example, a CVD method, and a silicon oxide film covering the insulating film 14 and the wiring layer 21 is formed, thereby forming the planarization layer 16. At this time, the surface of the planarization layer 16 is planarized by a CMP method or the like as necessary. Subsequently, similarly to the first embodiment, wiring layers 22 and 23, silicon oxide films,

contacts

24 and 25, and a pixel electrode 31 are formed. The

contacts

24 and 25 electrically couple the wiring layer 21 and the wiring layer 22 to each other, the wiring layer 22 and the wiring layer 23 to each other, and the wiring layer 23 and the pixel electrode 31 to each other. In this way, the drive substrate 40F shown in fig. 19 is realized. Note that in this embodiment, a contact for electrically coupling the wiring layer 22 and the wiring layer 23 is not shown.

Note that fig. 19 shows an embodiment in which the light shielding film 15 extends in the Y-axis direction and the light shielding film 15 is separated from each other between adjacent pixels P; however, the light shielding film 15 may be continuous. One of the reasons is that, in the present embodiment, the scanning line 11 and the gate electrode 13C are provided so as not to be electrically coupled to each other.

As described above, according to the present embodiment, after the wiring layer 21 is formed, the via hole H is formed by using the wiring layer 21 (specifically, the wiring line 21A) as a mask. The through hole H has a side surface (surface S3A) including an end surface of the wiring line 21A and an end surface of the semiconductor layer 13A. After that, the light shielding film 15 is formed on the side surfaces (surface S3a and surface S3b) of the through hole H. In this way, the semiconductor layer 13A and the wiring line 21A serving as the signal line DTL are electrically coupled to each other via the light-shielding film 15. Therefore, as shown in fig. 3 according to the first embodiment, it is not necessary to form the contact 17 that couples the semiconductor layer 13A and the wiring layer 21 to each other. Therefore, the non-opening area can be reduced according to the area of the contact 17. In other words, this can further improve the aperture ratio.

In addition, in the present embodiment, after the wiring layers 21 are formed, the light-shielding film 15 is formed on the side surfaces of the through-holes H including the end surfaces of the wiring layers 21. This allows the light shielding film 15 according to the present embodiment to have a higher height in the Z-axis direction than the light shielding film 15 according to the first embodiment. This further improves the light shielding effect of the pixel transistor 13, so that the image quality can be further improved.

<7. modification 3>

Fig. 22 shows a sectional configuration of a driving substrate 40G included in the liquid crystal panel 1 according to a modification of the present disclosure. With the drive substrate 40G according to the present modification, the light shielding film 15 is formed after the wiring layer 23 is formed. In addition, with respect to the through hole H, the end face of the semiconductor layer 13A is on the same plane (surface S3d) as the end face of the wiring layer 23. Therefore, the light shielding film 15 is continuously formed from the upper surface of the support substrate 41 to the upper end of the wiring layer 23, and the light shielding film 15 electrically couples the semiconductor layer 13A and the wiring layer 23 to each other. Note that the other end face of the semiconductor layer 13A is covered with the gate insulating film 13B (surface S3 c). The wiring layer 23 is electrically coupled to the pixel electrode 31 via the contact 25. Therefore, in the present modification, the scanning line WSL is divided in the X-axis direction and the Y-axis direction for each pixel P. In addition, the light shielding film 15 formed along the scanning line WSL is separated for each pixel P. It should be noted that fig. 22 schematically shows a sectional configuration of the drive substrate 40F with respect to two adjacent pixels P including the pixel transistor 13, taken along the line VI-VI shown in fig. 19.

The drive substrate 40G according to the present modification can be manufactured by using a method similar to the foregoing fourth embodiment except that the through hole H and the light-shielding film 15 are formed after the wiring layer 23 is formed.

As described above, according to the present modification, after the wiring layer 23 is formed, the through hole H having the side surface (surface S3d) including the end surface of the wiring layer 23 and the end surface of the semiconductor layer 13A is formed. After that, the light shielding film 15 is formed on the side surfaces (surface S3c and surface S3d) of the through hole H. In this way, the semiconductor layer 13A and the wiring layer 23 are electrically coupled to each other via the light-shielding film 15. In addition, the semiconductor layer 13A is electrically coupled to the pixel electrode 31 via the light shielding film 15, the wiring layer 23, and the contact 25. Therefore, similarly to the foregoing fourth embodiment, it is not necessary to form the contact 17 that couples the semiconductor layer 13A and the wiring layer 21 to each other. Therefore, the non-opening area can be reduced according to the area of the contact 17.

In addition, in the present modification, after the wiring layer 23 is formed, the light shielding film 15 is formed on the side surface of the through hole H including the end face of the wiring layer 23. This makes it possible to form the light shielding film 15 higher than the light shielding film 15 according to the fourth embodiment in the Z-axis direction. This can further improve the light shielding effect of the pixel transistor 13. Further, in the present modification, the light shielding film 15 is formed directly below the pixel electrode 31. Therefore, by forming the light-shielding film 15 using a material having a high optical reflectance, an effect as a waveguide can be obtained. This can improve light use efficiency.

<8. modification 4>

Fig. 23 schematically shows a planar configuration of a driving substrate 40H included in the liquid crystal panel 1 according to a modification of the present disclosure. Fig. 24 schematically shows a cross-sectional configuration with respect to two adjacent pixels P including the pixel transistor 13, taken along the line VII-VII shown in fig. 23. In the foregoing first to fourth embodiments and modifications 1 to 3, the top gate transistor is used as the pixel transistor 13 provided for each pixel P. However, this is not restrictive. As shown in fig. 24, the transistor may be a bottom gate transistor. In the drive substrate 40H according to the present modification, the TFT layer 90, the multilayer wiring layer 20, and the pixel electrode 31 are stacked in this order on the support substrate 41. The TFT layer 90 includes a bottom gate pixel transistor 93. The multilayer wiring layer 20 has a configuration similar to that of the foregoing first embodiment.

In the pixel transistor 93, a gate electrode 93C, a gate insulating film 93B, and a semiconductor layer 93A are stacked in this order from the support substrate 41 side. The gate electrode 93C also serves as a scanning line WSL. The insulating film 92 and the insulating film 94 are stacked in this order over the semiconductor layer 93A. The respective pixels P are separated by the via holes H. A light-shielding film 95 is formed along the end faces of the gate insulating film 93B, the insulating film 92, and the insulating film 94. The end faces of which are placed on the same plane. The via hole H is filled with the planarization layer 96. For example, a planarization layer 96 is also formed on the insulating film 94, thereby planarizing the surface of the TFT layer 90. The TFT layer 90 and the multilayer wiring layer 20 are electrically coupled to each other via a contact 97. The contacts 97 each penetrate the planarization layer 96, the insulating film 94, and the insulating film 92, and couple the semiconductor layer 93A and the wiring layer 21 to each other.

The description has been given above with reference to the first to fourth embodiments and the modifications 1 to 4. However, the disclosure is not limited thereto, and may be modified in various ways. For example, the configuration of the liquid crystal panel 1 according to the present disclosure is not limited to the projection display device. The configuration of the liquid crystal panel 1 according to the present disclosure is applicable to all types of semiconductor units that require light shielding. In addition, the above embodiments and the like exemplify a liquid crystal device used as a display device. However, this is not restrictive. For example, an organic Electroluminescent (EL) device or a Crystal Light Emitting Diode (CLED) may also be used.

It should be noted that the display unit and the projection display device according to the present disclosure may also have the following configuration.

(1)

A display unit, comprising:

a first substrate; and

a second substrate facing the first substrate with the liquid crystal layer interposed therebetween,

the first substrate comprises

A substrate is supported on the supporting base plate,

a plurality of scanning lines are arranged on the substrate,

a plurality of signal lines disposed above the support substrate and crossing each other,

a thin film transistor device disposed at each intersection between the plurality of scan lines and the plurality of signal lines, an

A light shielding film including a conductive material and disposed along a plurality of scanning lines in a plan view.

(2)

The display unit according to (1), wherein,

the thin film transistor device comprises

A gate electrode provided at each of intersections between the plurality of scan lines and the plurality of signal lines, an

A semiconductor layer disposed over each of the plurality of scan lines and including a plurality of first and second electrodes

The light shielding film is electrically coupled to one of a wiring line including a plurality of scanning lines and a plurality of signal lines, a gate electrode, and a semiconductor layer.

(3)

The display unit according to (1) or (2), wherein the light shielding film is continuously provided along a plurality of scanning lines in a plan view.

(4)

The display unit according to any one of (1) to (3), wherein the thin film transistor device is surrounded by a light shielding film in a plan view.

(5)

The display unit according to any one of (2) to (4), wherein the light shielding film is provided so that side surfaces of the thin film transistor device are expanded between the gate electrode and the semiconductor layer and on both sides.

(6)

The display unit according to any one of (2) to (5), wherein the semiconductor layer includes a lightly doped drain region.

(7)

The display unit according to any one of (2) to (6), wherein the scanning line, the semiconductor layer, and the gate electrode are stacked in this order from the side of the support substrate with the respective insulating films interposed therebetween in the first substrate, and

the light shielding film extends from the surface of the support substrate or the surface of the scan line to a position above the gate electrode in the stacking direction.

(8)

The display unit according to any one of (2) to (6),

a gate electrode and a semiconductor layer are stacked in this order from the side of the supporting substrate with an insulating film interposed therebetween in the first substrate, the gate electrode also serving as a scanning line, and

the light shielding film extends from the surface of the support substrate to a position above the semiconductor layer in the stacking direction.

(9)

The display unit according to any one of (1) to (8),

the first substrate comprises

A plurality of pixels, the number of which is,

an opening region provided for each of the plurality of pixels, an

A non-opening region disposed around the opening region, and

the light shielding film is formed on a side surface of the through-hole, the through-hole including a portion of the opening region and a portion of the non-opening region.

(10)

A projection display apparatus includes a light modulation unit modulating light from a light source,

the light modulation unit comprises

A first substrate, and

the first substrate comprises

A substrate is supported on the supporting base plate,

a plurality of scanning lines are arranged on the substrate,

A light shielding film including a conductive material and disposed along a plurality of scan lines in a plan view.

This application claims the benefit of japanese priority patent application No. 2017-016621, filed on day 1/2/2017 to the japanese patent office, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

Claims

1. A display device, comprising:

a first substrate; and

a second substrate facing each other with a liquid crystal layer interposed therebetween,

the first substrate comprises

A substrate is supported on the supporting base plate,

a plurality of scanning lines are arranged on the substrate,

a plurality of signal lines disposed over the support substrate and crossing each other,

A light-shielding film disposed at a side surface of the thin film transistor device, the light-shielding film including a conductive material and disposed along the plurality of scanning lines in a plan view,

the thin film transistor device comprises

A gate electrode disposed at each intersection between the plurality of scan lines and the plurality of signal lines, an

A semiconductor layer disposed over each of the plurality of scan lines and

the light shielding film is electrically coupled to one of a wiring line including the plurality of scanning lines and the plurality of signal lines, the gate electrode, and the semiconductor layer.

2. The display device according to claim 1, wherein the light shielding film is continuously provided along the plurality of scanning lines in the plan view.

3. The display device according to claim 1, wherein the thin film transistor device is surrounded by the light shielding film in the plan view.

4. The display device according to claim 1, wherein the light shielding film is provided so that side surfaces of the thin film transistor device are expanded between the gate electrode and the semiconductor layer and on both sides.

5. The display device of claim 1, wherein the semiconductor layer comprises a lightly doped drain region.

6. The display device according to claim 1, wherein the scan line, the semiconductor layer, and the gate electrode are stacked in this order from a side of the support substrate with a corresponding insulating film interposed therebetween in the first substrate, and

the light shielding film extends from a surface of the support substrate or a surface of the scan line to a position above the gate electrode in a stacking direction.

7. The display device according to claim 1,

the gate electrode and the semiconductor layer are stacked in this order from the side of the support substrate with an insulating film interposed therebetween in the first substrate, the gate electrode also serving as the scanning line, and

the light shielding film extends from a surface of the support substrate to a position above the semiconductor layer in a stacking direction.

8. The display device according to claim 1,

the first substrate comprises

A plurality of pixels, each of which is formed of a plurality of pixels,

an opening region provided for each of the plurality of pixels, an

A non-opening region disposed around the opening region, and

the light shielding film is formed on a side surface of a through-hole including a portion of the open region and a portion of the non-open region.

9. A projection display apparatus includes a light modulation unit modulating light from a light source,

the light modulation unit comprises

A first substrate, and

the first substrate comprises

A substrate is supported on the supporting base plate,

a plurality of scanning lines are arranged on the substrate,

A light-shielding film disposed on a side surface of the thin film transistor device, the light-shielding film including a conductive material and disposed along the plurality of scanning lines in a plan view,

the thin film transistor device comprises

A semiconductor layer disposed over each of the plurality of scan lines and