CN110226121A

CN110226121A - Display device and projection display apparatus

Info

Publication number: CN110226121A
Application number: CN201780084744.8A
Authority: CN
Inventors: 津野仁志
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 2017-02-01
Filing date: 2017-12-27
Publication date: 2019-09-10
Anticipated expiration: 2037-12-27
Also published as: CN110226121B; JPWO2018142822A1; JP7028192B2; WO2018142822A1

Abstract

The display device of the disclosure embodiment is provided with the first substrate arranged facing with each otherly and the second substrate, liquid crystal layer is between first substrate and the second substrate.First substrate includes: supporting substrate；It is arranged on supporting substrate and multi-strip scanning line intersected with each other and a plurality of signal wire；It is correspondingly disposed in the TFT element of the intersection of multi-strip scanning line and a plurality of signal wire；And the photomask for being formed by conductive material and being arranged in the plan view along multi-strip scanning line.

Description

Display device and projection display apparatus

Technical field

For example, this disclosure relates to display device and the projection display apparatus including display device.Display device is used as light tune Unit processed.

Background technique

In recent years, the projection liquid crystal of projection image shows that (LCD) unit is not only widely used in an office on the screen, And it is widely used in the family.Project liquid crystal display device (liquid crystal projection apparatus) is modulated by using light valve from light source Light, generate image light, on the screen by image light projection, and show picture.Light valve (light-modulating cell) includes liquid crystal surface Plate.For example, when carrying out active matrix drive to each pixel according to exterior artwork signal, light valve modulation light.

Liquid crystal display panel is highly desirable to higher brightness, and it is expected to improve the aperture opening ratio of pixel.However, working as aperture opening ratio When improvement, the lightproof area of TFT reduces.Reduce and therefore PN junction (specifically, the lightly doped drain of TFT in lightproof area (LDD)) when being irradiated by light, light leakage current is generated, and leakage current causes the picture quality such as flashed to deteriorate.

In order to solve this problem, for example, patent document 1 and patent document 2 disclose electrooptic unit (display device), each Electrooptic unit has pairs of groove on the two sides of semiconductor layer and in a groove includes light shield layer.Which improve semiconductors The shaded effect of layer and the appearance for inhibiting leakage current.In addition, patent document 3 discloses a kind of electrooptic unit, the electric light Unit includes the optical surface between open area and non-open areas.When light deviates open area, optical surface is by light It is directed to open area.

Reference listing

Patent document

Patent document 1: Japanese Unexamined Patent application discloses No. 2008-191200

Patent document 2: Japanese Unexamined Patent application discloses No. 2004-158518

Patent document 3: Japanese Unexamined Patent application discloses No. 2002-91339

Summary of the invention

As described above, substantially, there are trade-off relation (trade-off between aperture opening ratio and shaded effect Relation), it is expected that liquid crystal display panel has higher brightness and improved picture quality.

It would be desirable to provide a kind of display device and throwing that higher brightness and improved picture quality may be implemented Shadow shows equipment.

Display device according to embodiment of the present disclosure includes first substrate and the second substrate relative to each other, liquid crystal layer Between first substrate and the second substrate.First substrate includes supporting substrate, multi-strip scanning line, a plurality of signal wire, film crystalline substance Body tube device and photomask.Multi-strip scanning line and the setting of a plurality of signal wire are above supporting substrate and intersected with each other, and film is brilliant Each intersection between multi-strip scanning line and a plurality of signal wire is arranged in body tube device.Photomask include conductive material and It is arranged in the plan view along multi-strip scanning line.

Projection display apparatus according to embodiment of the present disclosure includes the light-modulating cell for modulating the light from light source.It throws Shadow shows that equipment includes the display device according to embodiment of the present disclosure as light-modulating cell.

In the display device according to embodiment of the present disclosure and the projection display apparatus according to embodiment of the present disclosure In, the photomask including conductive material is to be formed in the plan view along the multi-strip scanning line being arranged on supporting substrate.Branch Support group plate is included in first substrate.This can improve the shaded effect of the TFT device provided for each pixel, without limiting The opening of pixel.

According to the display device of embodiment of the present disclosure and according to the projection display apparatus of embodiment of the present disclosure, lead Electric photomask is to be formed in the plan view along multi-strip scanning line, so as to improve the shaded effect of TFT device, and it is unlimited The aperture opening ratio of pixel processed.Higher brightness and improving image quality may be implemented in this.

It it should be noted that said effect needs not be restrictive, and may include any effect described in the disclosure.

Detailed description of the invention

Fig. 1 is the schematic plan view according to the liquid crystal display panel of the first embodiment of the disclosure.

Fig. 2 is the schematic sectional view of entire liquid crystal display panel shown in Fig. 1.

Fig. 3 is the signal along the section of the drive substrate for including of the interception of line I-I shown in Fig. 1 in liquid crystal display panel Figure.

Fig. 4 is to show in liquid crystal display panel along the section of the drive substrate for including of the interception of line II-II shown in Fig. 1 It is intended to.

Fig. 5 is the section along the drive substrate for including of the interception of line III-III shown in Fig. 1 in liquid crystal display panel Schematic diagram.

Fig. 6 A is the sectional view of the manufacturing method for the drive substrate for including in description liquid crystal display panel shown in Fig. 1.

Fig. 6 B is the sectional view of the process after Fig. 6 A.

Fig. 6 C is the sectional view of the process after Fig. 6 B.

Fig. 6 D is the sectional view of the process after Fig. 6 C.

Fig. 6 E is the sectional view of the process after Fig. 6 D.

Fig. 7 is the schematic diagram of the positional relationship between scan line, gate electrode and through-hole.

Fig. 8 is shown including the embodiment according to the configuration of the display equipment of the liquid crystal display panel of the disclosure.

Fig. 9 shows the embodiment of the configuration of spatial light modulator.

Figure 10 shows the embodiment of the circuit configuration of pixel.

Figure 11 is showing for the section for the drive substrate for including in the liquid crystal display panel according to the second embodiment of the disclosure It is intended to.

Figure 12 is the sectional view for describing the manufacturing method of the drive substrate shown in Figure 11.

Figure 13 is showing for the section for the drive substrate for including in the liquid crystal display panel according to the third embodiment of the disclosure It is intended to.

Figure 14 A is the sectional view for describing the manufacturing method of the drive substrate shown in Figure 13.

Figure 14 B is to show the sectional view of the process after Figure 14 A.

Figure 15 is the schematic plan view for the drive substrate for including in the liquid crystal display panel according to the variation example 1 of the disclosure.

Figure 16 is the schematic diagram in the section of the drive substrate of the interception of the line IV-IV shown in Figure 15.

Figure 17 is the schematic plan view for the drive substrate for including in the liquid crystal display panel according to the variation example 2 of the disclosure.

Figure 18 is the schematic diagram in the section of the drive substrate of the interception of the line V-V shown in Figure 16.

Figure 19 is the diagrammatic plan for the drive substrate for including in the liquid crystal display panel according to the 4th embodiment of the disclosure Figure.

Figure 20 is the schematic diagram in the section of the drive substrate of the interception of the line VI-VI shown in Figure 19.

Figure 21 A is the sectional view for describing the manufacturing method of the drive substrate shown in Figure 20.

Figure 21 B is to show the sectional view of the process after Figure 21 A.

Figure 21 C is to show the sectional view of the process after Figure 21 B.

Figure 22 is the schematic diagram in the section for the drive substrate for including in the liquid crystal display panel according to the variation example 3 of the disclosure.

Figure 23 is the schematic plan view for the drive substrate for including in the liquid crystal display panel according to the variation example 4 of the disclosure.

Figure 24 is the schematic diagram in the section of the drive substrate of the interception of the line VII-VII shown in Figure 23.

Specific embodiment

Hereinafter, embodiment of the present disclosure is described in detail with reference to the accompanying drawings.It is retouched it should be noted that providing in the following order It states.Be described below be only the disclosure specific embodiment, and the disclosure should not necessarily be limited by following implementations.In addition, the disclosure It is not limited to the arrangement, size, size ratio etc. of each component shown in the drawings.

1. first embodiment (forms the embodiment of photomask) along scan line in the plan view

The configuration of 1-1. liquid crystal display panel

The manufacturing method of 1-2. drive substrate

The configured in one piece of 1-3. projection display apparatus

1-4. effect and effect

2. second embodiment (also forms the embodiment of photomask) above transistor

3. third embodiment (embodiment for forming through-hole and scan line first separation)

4. variation example 1 (embodiment that scan line and gate electrode directly couple)

5. variation example 2 (to the embodiment of the gate electrode supply current potential outside effective pixel area)

6. the 4th embodiment (forms the embodiment of photomask and opening) after forming the first wiring route

7. variation example 3 (forms the embodiment of photomask and opening) after forming third wiring route

8. variation example 4 (embodiment of bottom gate transistor)

<1. first embodiment>

Fig. 1 schematically shows the plane of the display unit (liquid crystal display panel 1) of the first embodiment according to the disclosure Configuration.Fig. 2 schematically shows the cross-sectional configurations of entire liquid crystal display panel 1 shown in Fig. 1.Liquid crystal display panel 1 includes pixel region Domain 1A and neighboring area 1B (referring to Fig. 9).In pixel region 1A, multiple pixel P are arranged in the matrix form.Neighboring area 1B encloses Around pixel region 1A.For example, liquid crystal display panel 1 is used as projection display apparatus (projector 100；Referring to Fig. 8) in light-modulating cell (space light modulation unit 130).In liquid crystal display panel 1, drive substrate 40A (first substrate) and counter substrate 50 (the second substrate) that This is opposite, and liquid crystal cells 60 (liquid crystal layer) are between drive substrate and counter substrate.In the plan view, according to the present embodiment Liquid crystal display panel 1 include conductive photomask 15 along the multi-strip scanning line WSL being arranged in drive substrate 40A.

It should be noted that statement mean " along multi-strip scanning line WSL " photomask 15 be arranged on every scan line WSL or with The end face of every scan line WSL is in contact, and states and still mean that other layer (such as, insulating films " along multi-strip scanning line WSL " 12) between scan line WSL and photomask 15.In the present embodiment, photomask 15 is described to be arranged in scan line WSL On embodiment.

(configuration of 1-1. liquid crystal display panel)

As described above, liquid crystal display panel 1 includes the liquid crystal list between drive substrate 40A and counter substrate 50 relative to each other Member 60.Oriented film 61 and 62 is arranged in the respective sides of liquid crystal cells 60, this two sides is the side of drive substrate 40A and opposed The side of substrate 50.The periphery of liquid crystal cells 60 is sealed with sealant 63.Corresponding polarization plates 42 and 52 are arranged in drive substrate The side (the surface side S2) of 40A and the side (the surface side S1) of counter substrate 50.These sides and liquid crystal cells 60 are opposite.

Fig. 3 schematically shows the cross-sectional configurations of the drive substrate 40A of the interception of the line I-I shown in Fig. 1.Drive base Plate 40A includes the pixel transistor 13 about two adjacent pixel P.Fig. 4 schematically shows the line II- shown in Fig. 1 The cross-sectional configurations of the drive substrate 40A of II interception.Fig. 5 schematically show along III-III interception drive substrate 40A Cross-sectional configurations.For example, drive substrate 40A includes multi-strip scanning line WSL and a plurality of signal wire DTL, these scan lines and signal wire Respectively in X-direction and Y direction extend and it is intersected with each other.Drive substrate 40A includes open area X and non-open areas Y.In the X of open area, incident light is reflected or is transmitted.Non-open areas Y is arranged around the X of open area.In non-open region In the Y of domain, provided with the pixel transistor 13 and multi-strip scanning line WSL intersected with each other that are described later on and a plurality of signal wire DTL.Example Such as, in drive substrate 40A, TFT layer 10, multiple wiring layer 20 and pixel electrode 31 are sequentially stacked on 41 (table of supporting substrate The face side S1) on.TFT layer 10 includes pixel transistor 13 (TFT device) etc..Multiple wiring layer 20 includes various wiring route (cloth Line layer 21,22 and 23).

For example, multi-strip scanning line WSL is arranged on supporting substrate 41 about TFT layer 10；Pixel transistor 13 is via insulation Film 12 is arranged above every scan line WSL；And insulating film 14 is arranged on pixel transistor 13.For each pixel P, phase The pixel transistor 13 answered is separated by through-hole H (referring to Fig. 6 B).For example, in the plan view, through-hole H is along formation multi-strip scanning What the region of line WSL was formed.The bottom of through-hole H reaches supporting substrate 41.In the present embodiment, photomask 15 is in stacking direction It is formed in (Z-direction) on the side surface (surface S3) of the through-hole H of the side surface including pixel transistor 13；It later will description Details.Irradiation of the oblique incidence light to pixel transistor 13 can be effectively reduced in this.Planarization layer 16 is between pixel transistor Between 13.Through-hole H is filled using planarization layer 16.Multiple wiring layer 20 is arranged on TFT layer 10.Multiple wiring layer 20 successively wraps Wiring layer 21,22 and 23 is included, interlayer insulating film 26 is between these wiring layers.For example, wiring layer 21,22 and 23 includes matching Set the wiring route of signal wire DTL or bus COM (not shown).

For example, supporting substrate 41 is quartz base plate.For example, there is supporting substrate 41 square surface shape (to be parallel to display The surface shape of screen).

For example, scan line WSL extends in the X-axis direction, and a part of scan line WSL extends in the Y-axis direction.Tool Body, scan line WSL extends or prolongs in the underface (opposed area) in the LDD region domain (LDD region domain 13c) of pixel transistor 13 It reaches near it.For example, scan line WSL includes the metal films such as tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta), or packet Include its alloy film.For example, the film thickness (hereinafter referred to as thickness) of scan line WSL in the Z-axis direction is in 10nm to 500nm In the range of.

For example, insulating film 12 and 14 includes silica (SiO₂) film, silicon nitride (Si₃N₄) film or its stack membrane.Insulating film 12 are arranged on scan line WSL.Pixel transistor 13 is arranged on insulating film 12.Insulating film 14 is arranged to cover pixel transistor The gate insulating film 13B and gate electrode 13C of pipe 13.For example, the thickness of insulating film 12 is in the range of 50nm to 1 μm.For example, absolutely The thickness of velum 14 is in the range of 100nm to 1 μm.

Pixel transistor 13 has lightly doped drain (LDD) structure.Pixel transistor 13 includes semiconductor layer 13A, grid electricity Pole 13C and gate insulating film 13B.Gate electrode 13C applies electric field to semiconductor layer 13A (especially channel region 13a).Grid is exhausted Velum 13B keeps semiconductor layer 13A and gate electrode 13C insulated from each other.Semiconductor layer 13A includes channel region 13a, LDD region domain 13c With source-drain regions 13b.Channel region 13a is arranged at the position opposite with gate electrode 13C.13c setting in LDD region domain exists In the respective sides of channel region 13a.The outside of corresponding LDD region domain 13c is arranged in source-drain regions 13b.According to this In the pixel transistor 13 of embodiment, gate electrode 13C is conductively coupled to scan line WSL via photomask 15；Source-drain regions One in 13b is conductively coupled to signal wire DTL；And the other of source-drain regions 13b is conductively coupled to pixel electrode 31。

As described above, for example, channel region 13a, source-drain regions 13b and LDD region domain 13c setting are in same layer (half Conductor layer 13A) in.For example, semiconductor layer 13A includes amorphous silicon film, polysilicon film etc..In semiconductor layer 13A by polysilicon film In the case of made of configuration, for example, the impurity of such as p-type impurity is doped in the 13b of source-drain regions, so that semiconductor layer 13A has lower resistance.Impurity is doped in the 13c of LDD region domain so that LDD region domain 13c has than source-drain regions The lower impurity concentration of 13b.

Gate insulating film 13B is for making semiconductor layer 13A and gate electrode 13C be electrically insulated from each other.For example, gate insulating film 13B includes silicon oxide film, silicon nitride film etc..For example, gate insulating film 13B is by thermal oxidation process or chemical vapor deposition (CVD) method is formed.

Via gate insulating film 13B, across semiconductor layer 13A is arranged gate electrode 13C in the X-axis direction.In semiconductor layer 13A In, the region opposite with gate electrode 13C is channel region 13a.Gate electrode 13C includes conductive material.Specifically, for example, grid are electric Pole 13C includes metal film of amorphous silicon film, polysilicon film, tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), tantalum (Ta) etc. or its conjunction Golden film.In addition, as shown in Figure 3, gate electrode 13C can have such structure, be stacked in this configuration conductive film 13d and Metal film 13e (or alloy film).Conductive film 13d includes conductive material, such as, polysilicon, amorphous silicon etc..Metal film 13e is selected from Above-mentioned metal film.For example, the thickness of gate electrode 13C is preferably 10nm or more.For example, the upper limit of the thickness of gate electrode 13C is 1 μm Below.

It should be noted that semiconductor layer 13A is described above in pixel transistor 13 according to the present embodiment in Y-axis The embodiment just upwardly extended.But this is not limiting.Pixel transistor 13 can also have semiconductor layer 13A in X-axis The configuration just upwardly extended.However, in the case where the signal wire DTL as described in present embodiment extends in the Y-axis direction, The semiconductor layer 13A extended in the Y-axis direction realizes excellent positioning efficiency.

Photomask 15 is for reducing irradiation of the oblique incidence light to pixel transistor 13.Photomask 15 is formed in manufacture driving On the side surface (surface S3) of the through-hole H formed during substrate 40A.As described above, in the plan view, through-hole H is along shape At thering is multi-strip scanning line WSL and the region of a plurality of signal wire DTL to be formed.Specifically, the periphery of through-hole H is formed and scan line WSL overlapping.In this way, photomask 15 is formed as in the plan view around pixel transistor 13.In addition, photomask 15 is arranged To be extended between semiconductor layer 13A and gate electrode 13C and on two sides.Specifically, in the stacking direction (Z of pixel transistor 13 Axis direction) on, photomask 15 is continuously formed to the upper end of insulating film 14 above scan line WSL.For example, photomask 15 has Shaded effect, and including conductive material.The specific embodiment of the material includes tungsten (W), molybdenum (Mo), titanium (Ti), aluminium (Al), copper (Cu) etc..Using conductive material to form photomask 15 makes gate electrode 13C and scan line WSL carry out thermocouple each other via photomask 15 It connects, as shown in Figure 4.For example, the thickness of photomask 15 is preferably in the range of 5nm to 200nm.

It should be noted that Fig. 1 shows the implementation for being continuously formed photomask 15 on the periphery of scan line WSL in the plan view Example.But this is not limiting.Photomask 15 is formed at least on the position of the PN junction of pixel transistor 13 to be sufficient. Specifically, photomask 15 is formed on the two sides of LDD region domain 13c to be sufficient., it is desirable in the picture including its periphery 13 surrounding of cellulose crystal pipe forms photomask 15.Thus, for example, it is not necessary to sweeping between adjacent pixel transistor 13 is being set Retouch formation photomask 15 in the corresponding region line WSL.It in other words, in the plan view, can be along setting in drive substrate 40A In scan line WSL discontinuously form photomask 15.

Similar to insulating film 12 and 14, planarization layer 16 includes SiO₂Film, Si₃N₄Film or its stack membrane.Planarization layer 16 is filled out It fills through-hole H and makes the surface planarisation of TFT layer 10.Therefore, although Fig. 3 etc. shows planarization layer 16 and fills through-hole H and cover The embodiment of lid insulating film 14, but planarization layer 16 need not be formed on insulating film 14.The thickness of planarization layer 16 depends on The thickness for all parts for including in pixel transistor 13, scan line 11 etc..For example, thickness of the planarization layer 16 away from supporting substrate 41 Degree is preferably in the range of 200nm to 2 μm.

For example, wiring layer 21,22 and 23 configures signal wire DTL and bus COM (not shown), interlayer insulating film 26 Between signal wire and bus.For example, wiring layer 21,22 and 23 includes aluminium (Al), copper (Cu), tungsten (W), titanium (Ti), the metal film or its alloy film of molybdenum (Mo), chromium (Cr), tantalum (Ta) etc..For example, wiring layer 21,22 and 23 is with side appropriate Formula carrys out electric coupling via contact 24 and 25 etc..For example, the thickness of each of wiring layer 21,22 and 23 is preferably in 100nm To in the range of 1 μm.

For example, signal wire DTL extends in the Y-axis direction, and the surface that semiconductor layer 13A is arranged in (is such as routed The opposed area of route 21A).In the source-drain regions 13b of semiconductor layer 13A, signal wire DTL via penetrate planarization The contact 17 of layer 16, insulating film 14 and gate insulating film 13B is electrically coupled to semiconductor layer 13A.

Similar to insulating film 12 and 14 and planarization layer 16, interlayer insulating film 26 includes SiO₂Film, Si₃N₄Film or it is folded Tunic.Interlayer insulating film 26 makes wiring layer 21,22 and 23 insulated from each other, and is suitably planarized.Interlayer insulating film 26 Thickness changes according to the quantity of the wiring layer of stacking.For example, between wiring layer film thickness (wiring layer 21 and wiring layer 22 it Between thickness or wiring layer 22 and wiring layer 23 between thickness) preferably in the range of 200nm to 1 μm.

For each pixel P, pixel electrode 31 is set.For example, pixel electrode 31 includes transparent conductive film.Transparent conductive film The embodiment of material includes oxide semiconductor, such as, tin indium oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and oxygen Change indium gallium zinc (IGZO).

For example, counter substrate 50 has the configuration for being wherein stacked supporting substrate 51 and public electrode 53.Public electrode 53 It is arranged on the surface (the surface side S2) opposite with liquid crystal cells 60 of supporting substrate 51.

For example, supporting substrate 51 includes quartz base plate.For example, unshowned colour filter and light shield layer (black-matrix layer) are set It sets in supporting substrate 51, and is for example covered with outer film (not shown).Public electrode 53 is arranged on outer film.

For example, public electrode 53 is used as the electrode that each pixel P is shared.Public electrode 53 is with pixel electrode 31 together to liquid Brilliant unit 60 supplies voltage.Similar to above-mentioned pixel electrode 31, public electrode 53 includes for example above-mentioned transparent conductive film.

Liquid crystal cells 60 have according to the picture voltage supplied by pixel electrode 31 and public electrode 53 control across The function of the transmissivity of the light of liquid crystal cells 60.For example, liquid crystal cells 60 include with vertical orientation (VA) mode, twisted-nematic (TN) drivings such as mode, electrically conerolled birefringence (ECB) mode, fringing field switching (FFS) mode, in-plane switching (IPS) mode are shown Liquid crystal.It is not particularly limited the liquid crystal material of liquid crystal cells 60.

Orientation of the oriented film 61 and 62 respectively for control liquid crystal cells 60.For example, oriented film 61 and 62 includes inorganic Material membrane, such as, silicon oxide film.For example, the thickness of each of oriented film 61 and 62 is in about 50nm to the range of about 360nm It is interior.For example, oriented film 61 and 62 is formed each by vapor deposition method.Oriented film 61 covers pixel electrode 31, and orients Film 62 covers public electrode 53.

Sealant 63 is used to seal the liquid crystal cells 60 between drive substrate 40A and counter substrate 50.For example, sealant 63 Insulating materials including such as polymeric material.The specific embodiment of sealant 63 includes epoxy resin and acrylic resin.

For example, polarization plates 42 and 52 are arranged with crossed Nicols arrangements.Polarization plates 42 and 52 only transmit certain vibration Light (polarised light) on direction.

(manufacturing method of 1-2. drive substrate)

For example, the drive substrate 40A for including in liquid crystal display panel 1 according to the present embodiment can be manufactured as described below.

Fig. 6 A to Fig. 6 E shows the manufacturing method of drive substrate 40A with processing sequence.Firstly, as shown in FIG, example Such as, W film is formed on supporting substrate 41 by CVD method or sputtering method, and is then formed and is scanned by patterning process Line 11.Next, for example, silicon oxide film is formed on supporting substrate 41 and scan line 11 by CVD method, to form insulation Film 12.At this point, as needed, the surface planarisation of insulating film 12 is made by CMP etc..Next, for example, passing through CVD method etc. Polysilicon film is formed on insulating film 12, and then carries out crystallization process as needed.Hereafter, half is formed by patterning process Conductor layer 13A.Then, for example, forming oxidation on insulating film 12 and semiconductor layer 13A by thermal oxidation process or CVD method Silicon fiml, to form gate insulating film 13B.Next, impurity is injected into semiconductor layer 13A to form channel as needed Region 13a.It should be noted that can before forming gate insulating film 13B implanted dopant.Then, for example, by CVD method in grid Polysilicon film and W film are formed on the insulating film 13B of pole, and gate electrode 13C is then formed by patterning process.Gate electrode 13C packet Include the conductive film 13d and metal film 13e of stacking.Hereafter, as needed, impurity is injected into semiconductor layer 13A, and carries out heat Annealing is to carry out impurity activation, to form LDD region domain 13c and source-drain regions 13b.Next, for example, passing through the side CVD Method forms silicon oxide film on gate insulating film 13B and gate electrode 13C, to form insulating film 14.At this point, as needed, leading to Crossing CMP etc. makes the surface planarisation of insulating film 14.

Next, as depicted in figure 6b, resist film 81 is formed on insulating film 14 to cover non-open areas Y.It is against corrosion Agent film 81 is used as mask, to for example form through-hole H by reactive ion etching (RIE) or wet etching.It should be noted that at this point, As shown in Figure 7, it is preferable that relative to being arranged close in multi-strip scanning line WSL (scan line 11) and a plurality of signal wire for through-hole H The edge of the gate electrode 13C on each crosspoint between DTL, the edge at edge (the through-hole edge) and gate electrode 13C of through-hole H The distance between (amount Chong Die with through-hole H) be about -0.2 μm or bigger.Here, " positive (+) " means gate electrode 13C and through-hole H The case where overlapping each other.It therefore, can also be in rectangle even if when deviation of the alignment occur between scan line 11 and gate electrode 13C It is via photomask 15 that scan line 11 and gate electrode 13C is electrically coupled to each other at the angle of any one of four angles of gate electrode 13C.

Hereafter, as shown in figure 6c, for example, for example, by CVD method, sputtering method, atomic layer deposition (ALD) method etc. On the upper surface of non-open areas Y, W film 15a is continuously formed on the side surface of through-hole H and on the bottom surface of through-hole H. W film 15a is used as photomask 15.

Next, as shown in figure 6d, W film 15a is for example handled by RIE.Specifically, in the side table in addition to through-hole H W film 15a is optionally removed at position except face.Therefore, photomask only is formed on the side surface (surface S3) of through-hole H 15.It should be noted that Fig. 6 D etc. shows the thickness from top to bottom of photomask 15 constant embodiment in the X-axis direction.But It is that this is not limiting.For example, in the case where handling W film by RIE as described above, due to using the manufacture of RIE etc. The thickness of journey, the top edge of photomask 15 is gradually thinning towards upper end.

Then, as is shown in figure 6e, through-hole H is filled by CVD method, for example, forming silicon oxide film to cover insulating film 14, to form planarization layer 16.At this point, as needed, the surface planarisation of planarization layer 16 is made by CMP etc..Next, Contact 17.Contact 17 penetrates planarization layer 16, insulating film 14 and gate insulating film 13B, and is in contact with semiconductor layer 13A. Then, such as by CVD method aluminium (Al) film is formed, and wiring layer 21 is then formed by patterning process.Wiring layer 21 wraps Include wiring route 21A and 21B.Next, for example, forming example on planarization layer 16 and wiring layer 21 for example, by CVD method Such as silicon oxide film.

Hereafter, be similar to the above method, formed wiring layer 22 and 23, silicon oxide film, wiring layer 21 (wiring route 21A) and Contact 24 and 25.Contact 24 and 25 is electrically coupled to each other by wiring layer 21 (wiring route 21A) and wiring layer 22, by 22 He of wiring layer Wiring layer 23 is electrically coupled to each other, and wiring layer 23 and pixel electrode 31 is electrically coupled to each other.It should be noted that in this embodiment, It is not shown the contact of 23 electric coupling of wiring layer 22 and wiring layer.In this way, multiple wiring layer 20 is formed.Finally, in layer Between pixel electrode 31 is formed on insulating layer 26, thus realize Fig. 3 it is equal shown in drive substrate 40A.

(configured in one piece of 1-3. projection display apparatus)

Fig. 8 is shown including the embodiment according to the configured in one piece of the projector 100 of the liquid crystal display panel 1 of the disclosure.For example, Projector 100 is three CCD stereopticons.For example, projector 100 includes illumination region 110, optical path branch portion 120, spatial light tune Portion 130, combination section 140 and Projection Division 150 processed.

The luminous flux of the irradiation target surface of the supply irradiation space light modulation unit 130 of illumination region 110.For example, illumination region 110 Including white light source lamp and reflecting mirror.Reflecting mirror is arranged behind lamp.As needed, illumination region 110 may include from lamp Light 111 pass through some optical device in the region of (on optical axis AX).For example, can be from lamp side successively in the optical axis AX of lamp Upper setting optical filter and light integrator.Optical filter keeps the light other than the visible light of the light 111 from lamp dimmed.Light integrator Keep the Illumination Distribution in the irradiation target surface of space light modulation unit 130 balanced.

The light 111 exported from illumination region 110 is separated into multiple colouramas with different-waveband by optical path branch portion 120 Beam, and each column of colour is directed to the irradiation target surface of space light modulation unit 130.For example, as shown in Figure 8, light Road branch portion 120 includes 121, two reflecting mirrors 122 of single crossed reflex mirror and two reflecting mirrors 123.Crossed reflex mirror 121 will The light 111 exported from illumination region 110 is separated into multiple column of colour with different-waveband, and it is respective to have column of colour Branch's optical path.For example, crossed reflex mirror 121 is arranged on optical axis AX.Crossed reflex mirror 121 has such configuration, wherein Two reflecting mirrors with different wavelength selectivities are coupled to intersect with each other.The reflected light path of reflecting mirror 122 and 123 is anti-by intersecting The column of colour (the feux rouges 111R and blue light 111B in Fig. 8) of 121 branch of She Jing.Reflecting mirror 122 and 123 setting with optical axis AX At different positions.Reflecting mirror 122 is arranged to for light (the feux rouges 111R in Fig. 8) to be directed to the irradiation of space light modulation unit 130R Target surface.Light is reflected by a reflecting mirror for including in crossed reflex mirror 121 towards the direction intersected with optical axis AX.Reflecting mirror 123 are arranged to for light (the blue light 111B in Fig. 8) to be directed to the irradiation target surface of space light modulation unit 130B.Light is intersected anti- Another reflecting mirror for including in mirror 121 is penetrated to reflect towards another direction intersected with optical axis AX.It is exported from illumination region 110 Light 111 in, be transmitted through crossed reflex mirror 121 and the light (the green light 111G in Fig. 8) advanced on optical axis AX be incident on and set It sets in the irradiation target surface of the space light modulation unit 130G on optical axis AX.

For example, space light modulation unit 130 is configured by using liquid crystal display panel 1 shown in Fig. 2 etc..Space light modulation unit 130 modulate multiple colouramas according to the picture signal Din inputted from unshowned information process unit, for each column of colour Beam, to generate modulation light beam for each column of colour.For example, space light modulation unit 130 includes space light modulation unit 130R, sky Between light modulation unit 130G and space light modulation unit 130B.Space light modulation unit 130R modulates feux rouges 111R.Space light modulation unit 130G modulates green light 111G.Space light modulation unit 130B modulates blue light 111B.

Space light modulation unit 130R is arranged in the region opposite with the surface of combination section 140.Space light modulation unit 130R Based on the incident feux rouges 111R of picture signal Din modulation, red image light 112R is generated, and red image light 112R is exported To the surface that the subsequent combination section 140 space light modulation unit 130R is arranged in.Space light modulation unit 130G setting with combination section At the opposite region in 140 another surface.Green light 111G space light modulation unit 130G incident based on picture signal Din modulation, Green image light 112G is generated, and green image light 112G is output to and is arranged in the subsequent combination of space light modulation unit 130R Another surface in portion 140.Space light modulation unit 130B is arranged in the region opposite with another surface of combination section 140.Space Blue light 111B light modulation unit 130B incident based on picture signal Din modulation generates blue image light 112B, and blue is schemed As light 112B is output to, another surface of the subsequent combination section 140 space light modulation unit 130R is set.

It combines multiple modulation light beams and generates image light in combination section 140.For example, combination section 140 is arranged on optical axis AX. For example, combination section 140 is the crossed nicols as made of the four prisms configuration linked.For example, two selective reflecting surface shapes At on the connected surfaces of prism.By using multi-coated interference film etc., the two selective reflecting surfaces have different wavelength Selectivity.For example, one of selective reflecting surface reflected on the direction for being parallel to optical axis AX it is defeated from space light modulation unit 130R Red image light 112R out, and guide red image light 112R into Projection Division 150.In addition, for example, selective reflecting surface In another reflected on the direction for being parallel to optical axis AX from space light modulation unit 130B export blue image light 112B, and And guide blue image light 112B into Projection Division 150.In addition, the green image light 112G exported from space light modulation unit 130G is saturating It was shot through two selective reflecting surfaces and advanced towards Projection Division 150.As a result, combination section 140 is for combining by space Each image beam that light modulation unit 130R, 130G and 130B are generated, to generate image light 113 and the image light by generation 113 are output to Projection Division 150.

Projection Division 150 will be projected on screen 200 from the image light 113 that combination section 140 exports to show image.For example, Projection Division 150 is arranged on optical axis AX, and including such as projecting lens.

Fig. 9 shows the embodiment of the configured in one piece of space light modulation unit 130R, 130G and 130B.For example, spatial light tune Each of portion 130R, 130G and 130B processed include above-mentioned liquid crystal display panel 1 and the driving circuit 70 for driving liquid crystal display panel 1.It drives Dynamic circuit 70 includes display control section 71, data driver 72 and gate drivers 73.

Liquid crystal display panel 1 includes pixel region 1A and its neighboring area 1B.In pixel region 1A, multiple pixel P are with matrix Form setting.Each pixel P by 73 active drive of data driver 72 and gate drivers, thus make liquid crystal display panel 1 be based on from Externally input picture signal Din shows image.

Liquid crystal display panel 1 includes multi-strip scanning line WSL, a plurality of signal wire DTL and a plurality of bus COM.Multi-strip scanning Line WSL extends in the row direction.A plurality of signal wire DTL extends in a column direction.A plurality of bus in the row direction or Extend on column direction.Pixel P is arranged to correspond to the crosspoint between signal wire DTL and scan line WSL.Every signal line DTL is couple to the output end (not shown) of data driver 72.Every scan line WSL is couple to the output end of gate drivers 73 (not shown).For example, every bus COM is couple to the output end (not shown) for exporting the circuit of fixed current potential.

For example, (showing) that display control section 71 is stored and kept in frame memory for each frame for each screen The picture signal Din to be supplied.In addition, for example, display control section 71 has the grid controlled to allow to drive liquid crystal display panel 1 Driver 73 and data driver 72 are bonded to each other the function of operation.Specifically, for example, display control section 71 will scan timing Control signal is supplied to data driver 72, and based on the picture signal being maintained in frame memory come to data driver 72 Supply a horizontal display timing controling signal and picture signal.

For example, data driver 72 supplies a horizontal picture signal Din as signal voltage to each pixel P. Picture signal Din is supplied from display control section 71.Specifically, for example, data driver 72 is via corresponding signal wire DTL Signal voltage corresponding to picture signal Din is supplied to corresponding pixel P.Pixel P is included in be selected by gate drivers 73 In the horizontal line selected.

It selects to drive according to the scanning timing controling signal supplied from display control section 71 for example, gate drivers 73 have The function of moving-target pixel P.Specifically, for example, strobe pulse is applied to pixel P via scan line WSL by gate drivers 73 Pixel transistor 13 gate electrode 13C, so that the pixel P of a line in the matrix being alternatively provided in pixel region 1A makees To drive target.Hereafter, pixel P shows a horizontal line according to the signal voltage supplied from data driver 72.With this Mode, for example, gate drivers 73 sequentially scan every horizontal line in chronological order, and on the complete display area into Row display.

Next, the circuit configuration of description pixel P.Figure 10 shows the embodiment of the circuit configuration of pixel P.Pixel P packet It includes liquid-crystal apparatus 2 and drives the pixel circuit 3 of liquid-crystal apparatus 2.Liquid-crystal apparatus 2 and pixel circuit 3 are arranged to correspond to scanning Crosspoint between line WSL and signal wire DTL.Liquid-crystal apparatus 2 includes liquid crystal cells 60, pixel electrode 31 and public electrode 53. Pixel electrode 31 and public electrode 53 are in liquid crystal cells 60.Pixel circuit 3 includes transistor (pixel transistor 13) and deposits Storage container 27.Liquid-crystal apparatus 2 is written in signal voltage by transistor.Storage 27 keeps the voltage of write-in liquid-crystal apparatus 2. Storage 27 includes pairs of electrode for capacitors, these electrode for capacitors are facing with each other, and scheduled gap is between this Between a little electrode for capacitors.One electrode for capacitors is couple to the source-drain regions 13b of semiconductor layer 13A, and another is electric Container electrode is couple to bus COM.

(1-4. effect and effect)

As described above, it would be highly desirable to which liquid crystal display panel has higher brightness.In order to realize higher brightness, picture is needed to be improved The aperture opening ratio of element.However, the lightproof area of TFT reduces when aperture opening ratio improves.Particularly, use liquid crystal display panel as throw In the case that shadow shows the light-modulating cell (light valve) of equipment, strong light guide from light source causes leakage current, and this cause it is all As the picture quality of flashing deteriorates.

As described above, substantially, there are trade-off relations between aperture opening ratio and shaded effect.It has developed with shading Effect has the liquid crystal display panel of improved aperture opening ratio simultaneously.For example, by the way that gate electrode is arranged on the semiconductor layer and by gate electrode It is embedded in the two sides of semiconductor layer, has developed the electrooptic unit for preventing light from entering semiconductor layer.Gate electrode is also served as and is swept Retouch the contact of line.However, because the contact realized by gate electrode is formed in non-open areas, so electrooptic unit is difficult to improve Aperture opening ratio.In addition, the grid not being embedded in are electric because the gate electrode of insertion is formed at the part in the two sides of semiconductor layer The part of pole still has low shaded effect.

Alternatively, for example, by further being hidden in TFT and being arranged between the light shield layer in non-open areas among setting Photosphere and by the way that intermediate light shield layer is extended to the groove on the periphery for being formed in semiconductor layer, having developed to have improves Shaded effect display unit.However, due to the non-open areas of the groove extended with intermediate light shield layer, display unit exists It is had the disadvantage in terms of improving aperture opening ratio.In addition, it is difficult to control the depth of groove, and groove and the scanning being arranged in below TFT There are gaps between line.Therefore, light may pass through gap incidence.

In addition, for example, by the way that optical surface is arranged between open area and non-open areas, develops to have and change The electrooptic unit of kind shaded effect and improved light utilization ratio.Oblique incidence light is reflected into open area by optical surface Side.However, optical surface includes the light-transmissive film of such as SiN.Therefore, electrooptic unit is difficult to realize significant shaded effect.

Meanwhile liquid crystal display panel 1 according to the present embodiment includes photomask 15, the photomask is in the plan view in stacking side Extend in (Z-direction) along the side surface of multi-strip scanning line WSL (scan line 11) covering pixel transistor 13, semiconductor Layer 13A and gate electrode 13C is arranged above scan line.Semiconductor layer 13A and gate electrode 13C are included in pixel transistor 13 In.In this way, photomask 15 is formed around pixel transistor 13, is entered so as to reduce oblique incidence light significantly The path (the LDD region domain 13c in especially semiconductor layer 13A) of pixel transistor 13.In other words, pixel transistor can be improved The shaded effect of pipe 13.In addition, photomask 15 includes conductive material, therefore can be electric each other by scan line 11 and gate electrode 13C Coupling, without contact is arranged between scan line 11 and gate electrode 13C.This can improve aperture opening ratio.

As described above, according to the present embodiment, in the plan view, photomask 15 is formed along multi-strip scanning line WSL, thus Allow to form photomask 15 around pixel transistor 13.Which improve the shaded effects of pixel transistor 13, so as to change Kind picture quality.In addition, photomask 15 includes conductive material, therefore can be electrically coupled to each other by scan line 11 and gate electrode 13C, Without contact is arranged between scan line 11 and gate electrode 13C.This can improve aperture opening ratio, higher bright so as to realize Degree.In other words, higher brightness and improving image quality may be implemented in this.

Next, second to fourth embodiment and variation example 1 to 4 of the description according to the disclosure.It should be noted that in fact with first The identical component of component for applying mode is indicated with reference symbol same as the first embodiment, and the descriptions thereof are omitted.

<2. second embodiment>

Figure 11 shows the drive substrate 40B for including in the liquid crystal display panel 1 according to the second embodiment of the disclosure Cross-sectional configurations.In the plan view, drive substrate 40B according to the present embodiment has such configuration, and wherein photomask 15 (hides Light film 15A) it is arranged along the multi-strip scanning line WSL being arranged in drive substrate 40A, and photomask 15 (photomask 15B) It is arranged above pixel transistor 13.It should be noted that Figure 11 schematically shows the pass intercepted along line I-I shown in Fig. 1 In the cross-sectional configurations of the drive substrate 40B for two adjacent pixel P for including pixel transistor 13.

Figure 12 shows the process for manufacturing drive substrate 40B shown in Figure 11.Similar to according to the first embodiment party The drive substrate 40A of formula, for example, the insulating film 14 that W film 15a is formed in through-hole H and is arranged in above pixel transistor 13 is (non-to open The upper surface of mouth region domain Y) side surface on.W film 15a is used as photomask 15 (photomask 15A and 15B).Next, as in Figure 12 It is shown, form resist film 82.Resist film 82 cover W film 15a side surface and upper surface and have desired pattern.Tool Body, resist film 82 has opening 82H at the position for forming contact 17.Contact 17 is by wiring layer 21 and semiconductor layer 13A It is electrically coupled to each other.Hereafter, for example, W film 15a is handled by RIE, then by using the method system being similar with first embodiment Make drive substrate 40B.In this way, driving surface 40B is realized, which includes covering through-hole H and pixel transistor The photomask 15 of the side surface of the part of 13 top of pipe.

As described above, according to the present embodiment, forming photomask 15, which covers pixel transistor 13 and pixel is brilliant The side surface of the part of 13 top of body pipe.This can prevent the stray light advanced in drive substrate 40B from entering pixel transistor 13.This further improves the shaded effects of pixel transistor 13.

It should be noted that in the first embodiment, it has been described that photomask 15 is from the upper surface of scan line 11 to insulation The embodiment of the upper surface setting of film 14.But this is not limiting.For example, as shown in Figure 11, photomask 15 can be with shape Upper surface to the end face (side surface) of scan line 11 as covering supporting substrate 41.

<3. third embodiment>

Figure 13 shows the drive substrate 40C for including in the liquid crystal display panel 1 according to the third embodiment of the disclosure Cross-sectional configurations.Drive substrate 40C according to the present embodiment have such configuration, wherein scan line 11, insulating film 12 and absolutely The end face of velum 14 is disposed on the same plane, and photomask 15 is formed in upper surface and the insulating film 14 of supporting substrate 41 On end face between upper end.It should be noted that Figure 13 is schematically shown along the interception of line I-I shown in Fig. 1 about including The cross-sectional configurations of the drive substrate 40C of two adjacent pixel P of pixel transistor 13.

Figure 14 A and Figure 14 B show the part for manufacturing the process of drive substrate 40C shown in Figure 13.Firstly, such as Shown in Figure 14 A, for example, forming W film 11a on supporting substrate 41 by CVD method, sputtering method etc..W film 11a, which is used as, to be swept Retouch line 11.Hereafter, Patternized technique can be executed, and W film 11a is not separated in non-open areas.Then, the shape on W film 11a At the silicon oxide film 12a as insulating film 12, and form semiconductor layer 13A with being then similar with first embodiment.Later, For example, sequentially forming the silicon oxide film 13x as gate insulating film 13B, gate electrode 13C and, for example, as insulating film 14 Silicon oxide film 14a.

Next, as shown in Figure 14 B, resist film 83 is formed in the corresponding region on insulating film 14 to cover non-open Mouth region domain Y.Mask is used as by using resist film 81, is formed for example, by RIE or wet etching and reaches supporting substrate 41 Through-hole H.At this point, being separated also in non-open areas Y to the W film 11a for being used as scan line 11.Later, by using with The similar method of first embodiment manufactures drive substrate 40C.In this way, drive substrate 40C is realized, wherein scan line 11, the end face of insulating film 12 and insulating film 14 is disposed on the same plane.

As described above, according to the present embodiment, being formed by once etching scan line 11, insulating film 12 and insulating film 14 Through-hole H, to form conductive photomask 15 on the side surface of through-hole H.Therefore, in scan line 11, insulating film 12 and insulating film The side surface of photomask 15 on 14 is formed on same plane (surface S3).This makes in case of misalignment, Ke Yitong Cross photomask 15 scan line 11 and gate electrode 13C is electrically coupled to each other.Therefore, it is not necessary to consider between through-hole H and scan line 11 Deviation of the alignment.This can further improve aperture opening ratio.

<4. variation example 1>

Figure 15 schematically shows the drive substrate 40D for including in the liquid crystal display panel 1 according to the variation example of the disclosure Planar configuration.Figure 16 shows the cross-sectional configurations of the interception of the line IV-IV shown in Figure 15.In the driving according to this variation example In substrate 40D, gate electrode 13C extends in the X-axis direction and is continuously formed between adjacent pixel P.Specifically, variation example 1 with foregoing first embodiment the difference is that, gate electrode 13C and scan line 11 it is opposite and above scan line 11 Extend in X-direction, and through-hole 13H of the gate electrode 13C between adjacent pixel P is conductively coupled to scan line 11.

It should be noted that first embodiment is similar to, by forming scan line 11, insulating film 12, half on supporting substrate 41 Conductor layer 13A and gate insulating film 13B forms through-hole 13H；Resist film is patterned on gate insulating film 13B；And RIE etc. is carried out while using resist film as mask.After forming through-hole 13H, such as is filled and led to by CVD method Hole 13H is similar to first embodiment, and forms such as polysilicon film on gate insulating film 13B.Then, pass through pattern Change process forms gate electrode 13C.Hereafter, drive substrate 40D is realized by the process being similar with first embodiment.

As described above, in this modified example, in the case where not using photomask 15, scan line 11 and gate electrode 13C exist It is coupled to each other at position far from semiconductor layer 13A.This can be than first embodiment more easily by scan line 11 and grid electricity Pole 13C is coupled to each other.In addition, through-hole 13H is not needed with shaded effect.This can improve the freedom degree of layout, so as to Further improve aperture opening ratio.

It should be noted that in this modified example, scan line 11 directly supplies the current potential of gate electrode 13C.Therefore, photomask 15 can be with With any current potential, and can be for example electrically floating.Therefore, in the plan view, from the edge of through-hole H to gate electrode 13C Edge distance (amount Chong Die with through-hole H) can be less than -0.2 μm.Through-hole H has side surface, and photomask 15 is formed in this On side surface.

<5. variation example 2>

Figure 17 schematically shows the drive substrate 40E for including in the liquid crystal display panel 1 according to the variation example of the disclosure Planar configuration.Figure 18 shows the cross-sectional configurations of the interception of the line V-V shown in Figure 17.In this modified example, gate electrode 13C The wiring layer 21 being electrically coupled to via contact 18 in the 1B of neighboring area.Current potential is supplied from wiring layer 21.

It should be noted that in this modified example, photomask 15 has current potential identical with scan line 11.In addition, in the plan view, Distance (amount Chong Die with through-hole H) from the edge of through-hole H to the edge of gate electrode 13C is less than -0.2 μm.Through-hole H has side table Face, photomask 15 are formed on the side surface.

As described above, in this modified example, gate electrode 13C and wiring layer 21 in the 1B of neighboring area via contact 18 each other Coupling, and current potential is supplied to gate electrode 13C from wiring layer 21.Compared with aforementioned variant example 1, this can be saved scan line 11 The process being coupled to each other with gate electrode 13C.

In addition, in this modified example, scan line WSL (scan line 11) is used as the back side photomask of pixel transistor 13.Cause This can reduce and caused by electric field by making scan line 11 have the best current potential of the retention performance for pixel transistor 13 Pixel transistor 13 leakage current, so as to further improve image quality.It should be noted that according to the scanning of this variation example Line 11 and photomask 15 can be respectively provided with floating potential；However, current potential, which is fixed to some current potential, can reduce capacitor coupling Influence.This can further improving image quality.

<6. the 4th embodiment>

Figure 19 schematically shows the driving base for including in the liquid crystal display panel 1 according to the 4th embodiment of the disclosure The planar configuration of plate 40F.Figure 20 is schematically shown along the interception of line VI-VI shown in Figure 19 about brilliant including pixel The cross-sectional configurations of two adjacent pixel P of body pipe 13.Drive substrate 40F according to the present embodiment has such configuration, Middle photomask 15 is continuously provided from the upper surface of supporting substrate 41 to the upper end of wiring layer 21 (specifically, wiring route 21A), And wherein semiconductor layer 13A and wiring route 21A are electrically coupled to each other via photomask 15.In addition, being swept for each pixel P It is separated for retouching line WSL in the X-axis direction.

Figure 21 A to Figure 21 C shows the part for manufacturing the process of drive substrate 40F shown in Figure 19.Firstly, making With with the similar method for drive substrate 40A according to first embodiment, until forming insulating film 14.It should infuse Meaning, at this point, semiconductor layer 13A is subjected to patterning so that an end face of semiconductor layer 13A is located at scan line in the Y-axis direction The outside of 11 end face.Next, as shown in figure 21 a, contact 17 is formed as penetrating insulating film 14 and gate insulating film 13B. Then, such as by CVD method aluminium (Al) film is formed, and 21 (wiring route of wiring layer is then formed by patterning process 21A and 21B).At this point, wiring route 21A's is located at the scanning below wiring route 21A in the end face on the side X of open area The outside of the end face of line 11, and the end face of wiring route 21A be located in plane identical with the end face of semiconductor layer 13A or Inside the end face of semiconductor layer 13A.Next, forming resist film 84 on insulating film 14 and wiring layer 21.At this point, cloth The end face on the side X of open area of line route 21A keeps exposing.Next, using resist film 84 and wiring route While 21A is as mask, through-hole H is formed by RIE, wet etching etc..In this way, the end face dew of semiconductor layer 13A Out, and side surface (surface S3a) is formed in plane identical with the end face of wiring layer 21 (wiring route 21A).It should be noted that At the side surface (surface S3b) on the side wiring route 21B, the end face of semiconductor layer 13A is covered with gate insulating film 13B.

Then, resist film 84 is removed, and then for example, by CVD method continuously in the upper table of non-open areas Y On face, W film 15a is formed on the side surface of through-hole H and on the bottom surface of through-hole H, as shown in figure 21b.W film 15a is used as shading Film 15.Next, as shown in Figure 21 C, for example, by being removed using RIE in addition to the end face of wiring layer 21 and the side table of through-hole H W film 15a at part except face forms photomask 15.In this way, semiconductor layer 13A and wiring route 21A via 15 electric coupling of photomask.It should be noted that wiring route 21A is used as signal wire DTL, so as to supply the current potential of signal wire DTL Give semiconductor layer 13A.

Later, such as by CVD method through-hole H is filled, and forms the silica of covering insulating film 14 and wiring layer 21 Film, to form planarization layer 16.At this point, as needed, the surface planarisation of planarization layer 16 is made by CMP method etc..With Afterwards, it is similar to first embodiment, forms wiring layer 22 and 23, silicon oxide film, contact 24 and 25 and pixel electrode 31.Touching Point 24 and 25 is electrically coupled to each other by wiring layer 21 and wiring layer 22, and wiring layer 22 and wiring layer 23 is electrically coupled to each other, and will Wiring layer 23 and pixel electrode 31 are electrically coupled to each other.In this way, drive substrate 40F shown in Figure 19 is realized.It should infuse Meaning, in this embodiment, is not shown the contact of 23 electric coupling of wiring layer 22 and wiring layer.

It should be noted that Figure 19 show photomask 15 extend in the Y-axis direction and photomask 15 between adjacent pixel P that The embodiment of this separation；However, photomask 15 can be continuously.One reason for this is that in the present embodiment, scan line 11 and gate electrode 13C is arranged to not electrically coupled to each other.

As described above, according to the present embodiment, after forming wiring layer 21, by using 21 (specifically, cloth of wiring layer Line route 21A) it is used as mask to form through-hole H.Through-hole H has the end face including wiring route 21A and the end of semiconductor layer 13A The side surface (surface S3a) in face.Later, photomask 15 is formed on the side surface of through-hole H (surface S3a and surface S3b).With this Kind mode, semiconductor layer 13A and the wiring route 21A as signal wire DTL are electrically coupled to each other via photomask 15.Therefore, such as Shown in Fig. 3 according to first embodiment, it is not necessary to form the contact 17 that semiconductor layer 13A and wiring layer 21 are coupled to each other. Therefore, non-open areas can be reduced according to the area of contact 17.In other words, this can further improve aperture opening ratio.

In addition, including the through-hole H's of the end face of wiring layer 21 after forming wiring layer 21 in the present embodiment Photomask 15 is formed on side surface.This has photomask 15 according to the present embodiment than according to first in the Z-axis direction The higher height of photomask 15 of embodiment.This further improves the shaded effect of pixel transistor 13, so as into One step improving image quality.

<7. variation example 3>

Match in the section that Figure 22 shows the drive substrate 40G for including in the liquid crystal display panel 1 according to the variation example of the disclosure It sets.About the drive substrate 40G according to this variation example, photomask 15 is formed after forming wiring layer 23.In addition, about The end face of through-hole H, semiconductor layer 13A and the end face of wiring layer 23 are on same plane (surface S3d).Therefore, photomask 15 from The upper surface of supporting substrate 41 is continuously formed the upper end of wiring layer 23, and photomask 15 is by semiconductor layer 13A and wiring Layer 23 is electrically coupled to each other.It should be noted that another end face of semiconductor layer 13A is covered with gate insulating film 13B (surface S3c).Cloth Line layer 23 is conductively coupled to pixel electrode 31 via contact 25.Therefore, in this modified example, for each pixel P, scan line WSL It is separated in X-direction and Y direction.In addition, the photomask 15 formed along scan line WSL is point for each pixel P It opens.It should be noted that Figure 22 is schematically shown along the interception of line VI-VI shown in Figure 19 about including pixel transistor The cross-sectional configurations of the drive substrate 40F of 13 two adjacent pixel P.

In addition to through-hole H and photomask 15 be other than being formed after forming wiring layer 23, can by using with it is aforementioned 4th embodiment similar method manufactures the drive substrate 40G according to this variation example.

As described above, after forming wiring layer 23, forming through-hole H, it includes wiring which, which has, according to this variation example The side surface (surface S3d) of the end face of the end face and semiconductor layer 13A of layer 23.Later, the side surface of through-hole H (surface S3c and Surface S3d) on form photomask 15.In this way, semiconductor layer 13A and wiring layer 23 are via the thermocouple each other of photomask 15 It connects.In addition, semiconductor layer 13A is conductively coupled to pixel electrode 31 via photomask 15, wiring layer 23 and contact 25.Therefore, similar In aforementioned 4th embodiment, it is not necessary to form the contact 17 that semiconductor layer 13A and wiring layer 21 are coupled to each other.It therefore, can be with Reduce non-open areas according to the area of contact 17.

In addition, including the side of the through-hole H of the end face of wiring layer 23 after forming wiring layer 23 in this modified example Photomask 15 is formed on surface.This can be formed in the Z-axis direction than the higher screening of photomask 15 according to the 4th embodiment Light film 15.This can further improve the shaded effect of pixel transistor 13.In addition, in this modified example, the formation of photomask 15 In the underface of pixel electrode 31.Therefore, photomask 15 is formed by using the material with high optical reflectivity, can be obtained Obtain the effect as waveguide.This can improve efficiency of light.

<8. variation example 4>

Figure 23 schematically shows the drive substrate 40H for including in the liquid crystal display panel 1 according to the variation example of the disclosure Planar configuration.Figure 24 is schematically shown along the interception of line VII-VII shown in Figure 23 about including pixel transistor The cross-sectional configurations of two adjacent pixel P of pipe 13.In aforementioned first to fourth embodiment and variation example 1 to 3, top grid Transistor is used as the pixel transistor 13 that each pixel P is provided.However, this is not limiting.As shown in Figure 24, crystal Pipe can be bottom gate transistor.In the drive substrate 40H according to this variation example, TFT layer 90, multiple wiring layer 20 and picture Plain electrode 31 is sequentially stacked on supporting substrate 41.TFT layer 90 includes bottom grid pixel transistor 93.Multiple wiring layer 20 has There is the configuration similar with foregoing first embodiment.

In pixel transistor 93, gate electrode 93C, gate insulating film 93B and semiconductor layer 93A are from 41 side of supporting substrate It stacks gradually.Gate electrode 93C also serves as scan line WSL.Insulating film 92 and insulating film 94 are sequentially stacked on semiconductor layer 93A Side.Each pixel P is separated by through-hole H.Photomask is formed along the end face of gate insulating film 93B, insulating film 92 and insulating film 94 95.It places in the same plane its end face.Through-hole H is filled using planarization layer 96.For example, planarization layer 96 is also formed in insulation On film 94, to make the surface planarisation of TFT layer 90.TFT layer 90 and multiple wiring layer 20 are electrically coupled to each other via contact 97.Touching Point 97 penetrates planarization layer 96, insulating film 94 and insulating film 92, and semiconductor layer 93A and wiring layer 21 are coupled to each other.

Description is given referring to first to fourth embodiment and variation example 1 to 4 above.However, the disclosure is interior Hold without being limited thereto, and can be modified in various ways.For example, being not limited to according to the configuration of the liquid crystal display panel 1 of the disclosure Projection display apparatus.All types of semiconductor units of shading are applicable to according to the configuration of the liquid crystal display panel 1 of the disclosure. In addition, above embodiment etc. instantiates the liquid-crystal apparatus as display device.But this is not limiting.For example, can also To use organic electroluminescent (EL) device or crystal light-emitting diodes (CLED).

It should be noted that can also have following configuration according to the display unit of the disclosure and projection display apparatus.

(1)

A kind of display unit, comprising:

First substrate；And

The second substrate, first substrate and the second substrate are relative to each other, and wherein liquid crystal layer is between first substrate and the second substrate Between,

First substrate includes

Supporting substrate,

Multi-strip scanning line,

A plurality of signal wire, the multi-strip scanning line and a plurality of signal wire setting are above supporting substrate and intersected with each other,

Film transistor device, the film transistor device each of are arranged between multi-strip scanning line and a plurality of signal wire Intersection, and

Photomask, the photomask include conductive material and are arranged in the plan view along multi-strip scanning line.

(2)

The display unit according to (1), wherein

Film transistor device includes

Each intersection between multi-strip scanning line and a plurality of signal wire is arranged in gate electrode, the gate electrode, and

Semiconductor layer, the semiconductor layer are arranged in above every scan line in multi-strip scanning line, and

Photomask is conductively coupled to one in wiring route, gate electrode and semiconductor layer, and wiring route includes multi-strip scanning Line and a plurality of signal wire.

(3)

According to display unit described in (1) or (2), wherein photomask is continuous along multi-strip scanning line in the plan view It is arranged.

(4)

The display unit according to any one of (1) to (3), wherein film transistor device is hidden in the plan view Light film surrounds.

(5)

The display unit according to any one of (2) to (4), wherein photomask is arranged to make thin film transistor (TFT) device The side surface of part extends between gate electrode and semiconductor layer and on two sides.

(6)

According to (2) to the display unit of any one of (5), wherein semiconductor layer includes lightly doped drain region.

(7)

According to (2) to the display unit of any one of (6), wherein scan line, semiconductor layer and gate electrode are from supporting substrate Side stack gradually, wherein in insulating film corresponding in first substrate between scan line, semiconductor layer and gate electrode, and And

Photomask extends to the position above gate electrode from the surface on the surface of supporting substrate or scan line in the stacking direction It sets.

(8)

The display unit according to any one of (2) to (6), wherein

Gate electrode and semiconductor layer are stacked gradually from the side of supporting substrate, wherein insulating film is between grid in first substrate Between electrode and semiconductor layer, gate electrode also serves as scan line, and

Photomask extends to the position above semiconductor layer from the surface of supporting substrate in the stacking direction.

(9)

The display unit according to any one of (1) to (8), wherein

First substrate includes

Multiple pixels,

Open area, the open area are arranged for each pixel in multiple pixels, and

Non-open areas, the non-open areas are arranged around open area, and

Photomask is formed on the side surface of through-hole, through-hole include open area a part and one of non-open areas Point.

(10)

A kind of projection display apparatus, the light-modulating cell including modulating the light from light source,

Light-modulating cell includes

First substrate, and

First substrate includes

Supporting substrate,

Multi-strip scanning line,

This application claims the Japanese Priority Patent Application 2017- for being submitted to Japanese Patent Office for 2 months on the 1st in 2017 No. 016621 equity, entire contents are incorporated herein by reference.

It will be understood by those skilled in the art that can be carry out various modifications, be combined, subgroup according to design requirement and other factors It closes and replaces, as long as they are in the range of appended claims or its equivalent.

Claims

1. a kind of display device, comprising:

First substrate；And

The second substrate, the first substrate and the second substrate are relative to each other, wherein liquid crystal layer between the first substrate with Between the second substrate,

The first substrate includes

Supporting substrate,

Multi-strip scanning line,

A plurality of signal wire, the multi-strip scanning line and a plurality of signal wire are arranged above the supporting substrate and hand over each other Fork,

Film transistor device, the film transistor device are arranged between the multi-strip scanning line and a plurality of signal wire Each intersection, and

Photomask, the photomask include conductive material and are arranged in the plan view along the multi-strip scanning line.

2. display device according to claim 1, wherein

The film transistor device includes

Each intersection between the multi-strip scanning line and a plurality of signal wire is arranged in gate electrode, the gate electrode, And

Semiconductor layer, the semiconductor layer are arranged in above every scan line in the multi-strip scanning line, and

The photomask is conductively coupled to one in wiring route, the gate electrode and the semiconductor layer, the wiring route Including the multi-strip scanning line and a plurality of signal wire.

3. display device according to claim 1, wherein the photomask is in the plan view along described a plurality of What scan line was continuously arranged.

4. display device according to claim 1, wherein the film transistor device is described in the plan view Photomask surrounds.

5. display device according to claim 2, wherein the photomask is arranged to make the film transistor device Side surface extended between the gate electrode and the semiconductor layer and on two sides.

6. display device according to claim 2, wherein the semiconductor layer includes lightly doped drain region.

7. display device according to claim 2, wherein the scan line, the semiconductor layer and the gate electrode from The side of the supporting substrate stacks gradually, wherein corresponding insulating film is between the scan line, institute in the first substrate It states between semiconductor layer and the gate electrode, and

The photomask extends to the grid from the surface on the surface of the supporting substrate or the scan line in the stacking direction Position above electrode.

8. display device according to claim 2, wherein

The gate electrode and the semiconductor layer are stacked gradually from the side of the supporting substrate, wherein in the first substrate For insulating film between the gate electrode and the semiconductor layer, the gate electrode also serves as the scan line, and

The photomask extends to the position above the semiconductor layer from the surface of the supporting substrate in the stacking direction.

9. display device according to claim 1, wherein

The first substrate includes

Multiple pixels,

Open area, the open area are arranged for each pixel in the multiple pixel, and

Non-open areas, the non-open areas are arranged around the open area, and

The photomask is formed on the side surface of through-hole, and the through-hole includes a part of the open area and described non-opens The a part in mouth region domain.

10. a kind of projection display apparatus, the light-modulating cell including modulating the light from light source,

The light-modulating cell includes

First substrate, and

The first substrate includes

Supporting substrate,

Multi-strip scanning line,