JP7018687B2 - 液晶表示パネル - Google Patents
液晶表示パネル Download PDFInfo
- Publication number
- JP7018687B2 JP7018687B2 JP2017112603A JP2017112603A JP7018687B2 JP 7018687 B2 JP7018687 B2 JP 7018687B2 JP 2017112603 A JP2017112603 A JP 2017112603A JP 2017112603 A JP2017112603 A JP 2017112603A JP 7018687 B2 JP7018687 B2 JP 7018687B2
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- JP
- Japan
- Prior art keywords
- pixel
- liquid crystal
- crystal display
- display panel
- active matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Geometry (AREA)
Description
以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の各実施形態に限定されるものではない。図1に、本発明に係る液晶表示パネルの平面図を示す。
実施の形態1では特定の画素のみドレイン接続電極の形状を変えてフォトスペーサとスルーホールとの距離を変えることにより、フォトスペーサのスルーホールへの落ち込みを抑制した。本実施の形態2においては、実施の形態1で用いたフォトスペーサに加えて、当該フォトスペーサよりも低いスペーサをも用いることを特徴とする。以下、図を用いて説明する。
5 薄膜トランジスタ、6 画素電極、8 コモン電極、8a スリット、
10a 第1の透明基板、10b 第2の透明基板、
13a ゲート絶縁膜、13b、13c 層間絶縁膜、
14 ドレイン接続電極、14a ドレイン接続電極延在部、
20 アクティブマトリクス基板、22 有機樹脂膜、30 対向基板、
40 液晶層、41 ブラックマトリクス、42 着色層、
47 フォトスペーサ、47a フォトスペーサ対応位置、48 フォトスペーサ、
51 表示領域、52 額縁領域、53 引き出し配線、
54 ゲート駆動回路、55 ソース駆動回路、56 外部端子、
120 液晶表示パネル、
PXR1、PXR2、PXR3、PXR4 赤画素、
PXG1、PXG2、PXG3、PXG4 緑画素、
PXB1、PXB2、PXB3、PXB4 青画素、
OP 開口領域
Claims (9)
- アクティブマトリクス基板と、
上記アクティブマトリクス基板に対向して配置された対向基板と、
上記アクティブマトリクス基板及び対向基板の間に設けられた液晶層と、を備える液晶表示パネルであって、
上記アクティブマトリクス基板は、
第1の透明基板と、
上記第1の透明基板上に形成されたゲート配線と、
上記ゲート配線と交差するソース配線と、
上記ゲート配線と上記ソース配線とで区切られる画素内に形成されるスイッチング素子であって、上記ゲート配線と少なくとも一部が重なる半導体層を有するスイッチング素子と、
上記スイッチング素子の一部を覆う絶縁膜と、
各画素内に形成され、上記絶縁膜に開口するスルーホールを介して上記スイッチング素子と接続する画素電極と、を備えており、
上記対向基板は、
第2の透明基板と、
上記第2の透明基板上に形成されて一部の画素内で上記アクティブマトリクス基板と当接するスペーサと、を備えており、
各画素は、複数種類の色のいずれかに対応し、光を透過しない遮光領域と、対応する色の光を透過する開口領域と、を有しており、
上記複数種類の色のうちある1色に対応する画素には、上記アクティブマトリクス基板が上記遮光領域において上記スペーサと当接する第1画素と、上記アクティブマトリクス基板が上記スペーサと当接しない第2画素とが含まれ、
上記複数種類の色のうち上記1色以外の色に対応する画素には、上記アクティブマトリクス基板が上記スペーサと当接しない第3画素が含まれ、
上記第1画素と上記第2画素のそれぞれにおける上記開口領域の面積は、上記第3画素における上記開口領域の面積よりも小さく、
上記第1画素及び上記第2画素のそれぞれにおける上記スルーホールの相対位置が、上記第3画素における上記スルーホールの相対位置と異なるように、上記第1画素及び上記第2画素のそれぞれにおける上記半導体層と上記スルーホールとの間の間隔が、上記第3画素における上記半導体層と上記スルーホールとの間の間隔よりも大きく空いていることを特徴とする液晶表示パネル。 - 上記第1画素及び上記第2画素と対応する色と、上記第3画素と対応する色とで白色バランスをとることが可能であることを特徴とする請求項1に記載の液晶表示パネル。
- 上記スイッチング素子はドレイン接続電極を有し、
上記ドレイン接続電極と上記画素電極とが上記スルーホールを介して直接接続しており、
上記第1画素及び上記第2画素のそれぞれにおける上記ドレイン接続電極の上記ゲート配線の延在方向における長さは、上記第3画素における上記ドレイン接続電極の上記ゲート配線の延在方向における長さよりも長いことを特徴とする請求項1または2に記載の液晶表示パネル。 - 上記第1画素及び上記第2画素のそれぞれにおける上記画素電極の形状は、上記第3画素における上記画素電極の形状とほぼ同様であることを特徴とする請求項1から3のいずれか1項に記載の液晶表示パネル。
- 上記スペーサよりも高さが低い第2スペーサを上記第3画素に形成したことを特徴とする請求項1から4のいずれか1項に記載の液晶表示パネル。
- 上記絶縁膜は有機樹脂膜であることを特徴とする請求項1から5のいずれか1項に記載の液晶表示パネル。
- 上記液晶表示パネルは湾曲していることを特徴とする請求項1から6のいずれか1項に記載の液晶表示パネル。
- 上記第1画素と上記第2画素とでは、上記スイッチング素子形状及び上記スルーホール形状、及び上記スイッチング素子と上記スルーホールとの位置関係、は同一であることを特徴とする請求項1から7のいずれか1項に記載の液晶表示パネル。
- 上記スペーサは、上記第1画素内においては上記遮光領域において上記スイッチング素子と重なるように上記アクティブマトリクス基板と当接することを特徴とする請求項1から8のいずれか1項に記載の液晶表示パネル。
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DE102018208518.8A DE102018208518A1 (de) | 2017-06-07 | 2018-05-29 | Flüssigkristallanzeigefeld |
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US20180356667A1 (en) | 2018-12-13 |
DE102018208518A1 (de) | 2018-12-13 |
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