JP7017428B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7017428B2 JP7017428B2 JP2018019900A JP2018019900A JP7017428B2 JP 7017428 B2 JP7017428 B2 JP 7017428B2 JP 2018019900 A JP2018019900 A JP 2018019900A JP 2018019900 A JP2018019900 A JP 2018019900A JP 7017428 B2 JP7017428 B2 JP 7017428B2
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- insulator
- oxide
- conductor
- region
- transistor
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Description
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図1(A)、図1(B)、および図1(C)は、本発明の一態様に係るトランジスタ200、容量素子100、およびトランジスタ200周辺の上面図、および断面図である。なお、本明細書では、1つの容量素子、および少なくとも1つのトランジスタを有する半導体装置をセルと称する。
ここで、本実施の形態のセルアレイの一例を、図2に示す。例えば、図1に示すトランジスタ200、および容量素子100を有するセル600を、マトリクス状に配置することで、セルアレイを構成することができる。図2(A)、および図2(B)は、図1に示すセル600を、マトリクス状に配置した場合における、行の一部を抜き出した断面図である。
図1、および図3に示すように、トランジスタ200は、基板(図示せず)の上に配置された絶縁体214および絶縁体216と、絶縁体214および絶縁体216に埋め込まれるように配置された導電体205と、絶縁体216と導電体205の上に配置された絶縁体220と、絶縁体220の上に配置された絶縁体222と、絶縁体222の上に配置された絶縁体224と、絶縁体224の上に配置された酸化物230(酸化物230a、酸化物230b、および酸化物230c)と、酸化物230の上に配置された絶縁体250と、絶縁体250の上に配置された導電体260(導電体260a、導電体260b、および導電体260c)と、導電体260の上に配置された絶縁体270、および絶縁体271と、少なくとも絶縁体250、および導電体260の側面に接して配置された絶縁体272と、酸化物230、および絶縁体272と接して配置された絶縁体274と、を有する。
図1、および図3に示すように、容量素子100は、トランジスタ200と共通の構造を有する構成である。本実施の形態では、トランジスタ200の酸化物230に設けられた領域231bが、容量素子100の電極の一方として機能する容量素子100の例について示す。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどの半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えばSOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウムなどから選ばれた金属元素を1種以上含む材料を用いることができる。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
酸化物230として、酸化物半導体として機能する金属酸化物(以下、酸化物半導体ともいう)を用いることが好ましい。以下では、本発明に係る酸化物230に適用可能な金属酸化物について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud-Aligned Composite)-OSの構成について説明する。
酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC-OS(c-axis aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc-OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a-like OS:amorphous-like oxide semiconductor)および非晶質酸化物半導体などがある。
続いて、上記酸化物半導体をトランジスタに用いる場合について説明する。
ここで、酸化物半導体中における各不純物の影響について説明する。
以下では、図5を用いて、本発明の一態様に係るセル600を有する半導体装置の一例について説明する。
図5に示すように、セル600は、<半導体装置の構成例1>に示した半導体装置とは、少なくとも容量素子100の形状が異なる。
以下では、図6を用いて、本発明の一態様に係るセル600を有する半導体装置の一例について説明する。
図6に示すように、セル600は、<半導体装置の構成例1>に示した半導体装置とは、少なくともトランジスタ200と電気的に接続する導電体252bの形状が異なる。
次に、本発明に係るトランジスタ200を有する半導体装置について、作製方法を図7乃至図20を用いて説明する。また、図7乃至図20において、各図の(A)は上面図を示す。また、各図の(B)は(A)に示すA1-A2の一点鎖線で示す部位に対応する断面図である。また、各図の(C)は、(A)にA3-A4の一点鎖線で示す部位に対応する断面図である。
以下では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図21(A)、図21(B)、および図21(C)は、本発明の一態様に係るトランジスタ200、容量素子100、およびトランジスタ200周辺の上面図、および断面図である。なお、本明細書では、1つの容量素子、および少なくとも1つのトランジスタを有する半導体装置をセルと称する。
ここで、本実施の形態のセルアレイの一例を、図23、および図24に示す。例えば、図21に示すトランジスタ200、および容量素子100を有するセル600を、行列、またはマトリクス状に配置することで、セルアレイを構成することができる。
本発明の一態様の半導体装置は、トランジスタ200と、容量素子100、および層間膜として機能する絶縁体280を有する。また、トランジスタ200と電気的に接続し、プラグとして機能する導電体252(導電体252a、導電体252b、導電体252c、および導電体252d)とを有する。
以下では、図26を用いて、本発明の一態様に係るセル600を有する半導体装置の一例について説明する。
図26に示すように、セル600は、<半導体装置の構成例1>に示した半導体装置とは、少なくとも容量素子100の形状が異なる。
本実施の形態では、半導体装置の一形態を、図27、および図28を用いて説明する。
図27、および図28に示す記憶装置は、トランジスタ200、および容量素子100を有するセル600と、トランジスタ300と、を有している。
本発明の一態様の半導体装置は、図27、および図28に示すようにトランジスタ300、トランジスタ200、容量素子100を有する。トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ300、およびトランジスタ200の上方に設けられている。
本実施の形態では、図29および図30を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ。)、および容量素子が適用されている記憶装置の一例として、NOSRAMについて説明する。NOSRAM(登録商標)とは「Nonvolatile Oxide Semiconductor RAM」の略称であり、ゲインセル型(2T型、3T型)のメモリセルを有するRAMを指す。なお、以下において、NOSRAMのようにOSトランジスタを用いたメモリ装置を、OSメモリと呼ぶ場合がある。
図29にNOSRAMの構成例を示す。図29に示すNOSRAM1600は、メモリセルアレイ1610、コントローラ1640、行ドライバ1650、列ドライバ1660、出力ドライバ1670を有する。なお、NOSRAM1600は、1のメモリセルで多値データを記憶する多値NOSRAMである。
図30(A)はメモリセル1611の構成例を示す回路図である。メモリセル1611は2T型のゲインセルであり、メモリセル1611はワード線WWL、RWL、ビット線BL、ソース線SL、配線BGLに電気的に接続されている。メモリセル1611は、ノードSN、OSトランジスタMO61、トランジスタMP61、容量素子C61を有する。OSトランジスタMO61は書き込みトランジスタである。トランジスタMP61は読み出しトランジスタであり、例えばpチャネル型Siトランジスタで構成される。容量素子C61はノードSNの電圧を保持するための保持容量である。ノードSNはデータの保持ノードであり、ここではトランジスタMP61のゲートに相当する。
本実施の形態では、図31および図32を用いて、本発明の一態様に係る、OSトランジスタ、および容量素子が適用されている記憶装置の一例として、DOSRAMについて説明する。DOSRAM(登録商標)とは、「Dynamic Oxide Semiconductor RAM」の略称であり、1T(トランジスタ)1C(容量)型のメモリセルを有するRAMを指す。DOSRAMも、NOSRAMと同様に、OSメモリが適用されている。
図31にDOSRAMの構成例を示す。図31に示すように、DOSRAM1400は、コントローラ1405、行回路1410、列回路1415、メモリセルおよびセンスアンプアレイ1420(以下、「MC-SAアレイ1420」と呼ぶ。)を有する。
MC-SAアレイ1420は、メモリセルアレイ1422をセンスアンプアレイ1423上に積層した積層構造をもつ。グローバルビット線GBLL、GBLRはメモリセルアレイ1422上に積層されている。DOSRAM1400では、ビット線の構造に、ローカルビット線とグローバルビット線とで階層化された階層ビット線構造が採用されている。
コントローラ1405は、DOSRAM1400の動作全般を制御する機能を有する。コントローラ1405は、外部からの入力されるコマンド信号を論理演算して、動作モードを決定する機能、決定した動作モードが実行されるように、行回路1410、列回路1415の制御信号を生成する機能、外部から入力されるアドレス信号を保持する機能、内部アドレス信号を生成する機能を有する。
行回路1410は、MC-SAアレイ1420を駆動する機能を有する。デコーダ1411はアドレス信号をデコードする機能を有する。ワード線ドライバ回路1412は、アクセス対象行のワード線WLを選択する選択信号を生成する。
列回路1415は、データ信号WDA[31:0]の入力を制御する機能、データ信号RDA[31:0]の出力を制御する機能を有する。データ信号WDA[31:0]は書き込みデータ信号であり、データ信号RDA[31:0]は読み出しデータ信号である。
本実施の形態では、図33から図36を用いて、本発明の一態様に係る、OSトランジスタ、および容量素子が適用されている半導体装置の一例として、FPGA(フィールドプログラマブルゲートアレイ)について説明する。本実施の形態のFPGAは、コンフィギュレーションメモリ、およびレジスタにOSメモリが適用されている。ここでは、このようなFPGAを「OS-FPGA」と呼ぶ。
図33(A)にOS-FPGAの構成例を示す。図33(A)に示すOS-FPGA3110は、マルチコンテキスト構造によるコンテキスト切り替えとPLE毎の細粒度パワーゲーティングを実行するNOFF(ノーマリオフ)コンピューティングが可能である。OS-FPGA3110は、コントローラ3111、ワードドライバ3112、データドライバ3113、プログラマブルエリア3115を有する。
“H”の信号storeがOS-FF3140に入力されると、シャドウレジスタ3142はFF3141のデータをバックアップする。ノードN36は、ノードQのデータが書き込まれることで、“L”となり、ノードNB36は、ノードQBのデータが書き込まれることで、“H”となる。しかる後、パワーゲーティングが実行され、パワースイッチ3127をオフにする。FF3141のノードQ、QBのデータは消失するが、電源オフであっても、シャドウレジスタ3142はバックアップしたデータを保持する。
パワースイッチ3127をオンにし、PLE3121に電源を供給する。しかる後、“H”の信号loadがOS-FF3140に入力されると、シャドウレジスタ3142はバックアップしているデータをFF3141に書き戻す。ノードN36は“L”であるので、ノードN37は“L”が維持され、ノードNB36は“H”であるので、ノードNB37は“H”となる。よって、ノードQは“H”になり、ノードQBは“L”になる。つまり、OS-FF3140はバックアップ動作時の状態に復帰する。
本実施の形態では、図37を用いて、上記実施の形態に示す半導体装置を適用した、AIシステムについて説明を行う。
<AIシステムの応用例>
本実施の形態では、上記実施の形態に示すAIシステムの応用例について図38を用いて説明を行う。
本実施の形態は、上記実施の形態に示すAIシステムが組み込まれたICの一例を示す。
<電子機器>
本発明の一態様に係る半導体装置は、様々な電子機器に用いることができる。図40に、本発明の一態様に係る半導体装置を用いた電子機器の具体例を示す。
Claims (1)
- 第1の領域と、前記第1の領域を挟むように設けられた第2の領域と第3の領域と、前記第1の領域乃至前記第3の領域を挟むように設けられた第4の領域と第5の領域を有する第1の酸化物と、
前記第1の酸化物上に設けられ、前記第1の領域乃至前記第3の領域と重なる第2の酸化物と、
前記第2の酸化物上の第1の絶縁体と、
前記第1の絶縁体上の第1の導電体と、
前記第1の絶縁体および前記第1の導電体の側面に設けられ、且つ前記第2の酸化物上の一部に接する第2の絶縁体と、を有し、
前記第4の領域及び前記第5の領域は、前記第2の酸化物とは重ならず、
前記第4の領域及び前記第5の領域は、前記第1の絶縁体とは重ならず、
前記第4の領域及び前記第5の領域は、前記第1の導電体及び前記第2の絶縁体とは重ならず、
前記第4の領域は、前記第4の領域上の第3の絶縁体を介して第2の導電体と重なることで、容量素子の一方の電極として機能する、ことを特徴とする半導体装置。
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KR102440302B1 (ko) * | 2015-04-13 | 2022-09-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제작 방법 |
JP6710504B2 (ja) | 2015-07-27 | 2020-06-17 | パイオニア株式会社 | 生体音聴診装置 |
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2018
- 2018-01-31 DE DE112018000776.6T patent/DE112018000776T5/de not_active Withdrawn
- 2018-01-31 KR KR1020197026263A patent/KR20190116998A/ko unknown
- 2018-01-31 CN CN201880011285.5A patent/CN110709998A/zh active Pending
- 2018-01-31 US US16/483,302 patent/US20200006328A1/en not_active Abandoned
- 2018-01-31 WO PCT/IB2018/050581 patent/WO2018146580A1/en active Application Filing
- 2018-02-07 JP JP2018019900A patent/JP7017428B2/ja active Active
- 2018-02-09 TW TW107104806A patent/TW201834149A/zh unknown
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JP2012256821A (ja) | 2010-09-13 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置 |
JP2013093573A (ja) | 2011-10-07 | 2013-05-16 | Semiconductor Energy Lab Co Ltd | 半導体装置及び半導体装置の作製方法 |
JP2014192418A (ja) | 2013-03-28 | 2014-10-06 | Sony Corp | 半導体装置、表示装置および電子機器 |
US20160260835A1 (en) | 2015-03-02 | 2016-09-08 | Semiconductor Energy Laboratory Co., Ltd. | Transistor, method for manufacturing transistor, semiconductor device, and electronic device |
JP2016174147A (ja) | 2015-03-02 | 2016-09-29 | 株式会社半導体エネルギー研究所 | トランジスタ、トランジスタの作製方法、半導体装置および電子機器 |
JP2016178297A (ja) | 2015-03-19 | 2016-10-06 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP2016219801A (ja) | 2015-05-22 | 2016-12-22 | 株式会社半導体エネルギー研究所 | 半導体装置、該半導体装置を有する表示装置 |
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WO2018146580A1 (en) | 2018-08-16 |
DE112018000776T5 (de) | 2019-12-05 |
TW201834149A (zh) | 2018-09-16 |
JP2018133563A (ja) | 2018-08-23 |
KR20190116998A (ko) | 2019-10-15 |
US20200006328A1 (en) | 2020-01-02 |
CN110709998A (zh) | 2020-01-17 |
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