JP6974446B2 - 誘電体材料層を使用してチャネル領域に応力を加えるフィン電界効果トランジスタ（ＦＥＴ）（ＦｉｎＦＥＴ） - Google Patents

誘電体材料層を使用してチャネル領域に応力を加えるフィン電界効果トランジスタ（ＦＥＴ）（ＦｉｎＦＥＴ） Download PDF

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JP6974446B2
JP6974446B2 JP2019513978A JP2019513978A JP6974446B2 JP 6974446 B2 JP6974446 B2 JP 6974446B2 JP 2019513978 A JP2019513978 A JP 2019513978A JP 2019513978 A JP2019513978 A JP 2019513978A JP 6974446 B2 JP6974446 B2 JP 6974446B2
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dielectric material
material layer
fin
finfet
channel region
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JP2019530227A (ja
JP2019530227A5 (enExample
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ウクジン・ロー
ヨン・ソン・チェ
シャシャンク・エクボテ
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クアルコム，インコーポレイテッド
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    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
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    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
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    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
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    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Engineering & Computer Science (AREA)
JP2019513978A 2016-09-15 2017-08-11 誘電体材料層を使用してチャネル領域に応力を加えるフィン電界効果トランジスタ（ＦＥＴ）（ＦｉｎＦＥＴ） Active JP6974446B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/266,840 US9882051B1 (en) 2016-09-15 2016-09-15 Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions
US15/266,840 2016-09-15
PCT/US2017/046525 WO2018052591A1 (en) 2016-09-15 2017-08-11 Fin field effect transistors (fets) (finfets) employing dielectric material layers to apply stress to channel regions

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JP2019530227A JP2019530227A (ja) 2019-10-17
JP2019530227A5 JP2019530227A5 (enExample) 2020-08-27
JP6974446B2 true JP6974446B2 (ja) 2021-12-01

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US (1) US9882051B1 (enExample)
EP (1) EP3513437B1 (enExample)
JP (1) JP6974446B2 (enExample)
KR (1) KR102550579B1 (enExample)
CN (1) CN109844957A (enExample)
BR (1) BR112019004507B1 (enExample)
WO (1) WO2018052591A1 (enExample)

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US10109507B2 (en) * 2016-06-01 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Fluorine contamination control in semiconductor manufacturing process
US11211243B2 (en) * 2018-11-21 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of filling gaps with carbon and nitrogen doped film
KR102760190B1 (ko) * 2019-05-16 2025-01-23 삼성전자주식회사 반도체 장치 및 그 제조 방법

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US7081395B2 (en) 2003-05-23 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
JP2007207837A (ja) 2006-01-31 2007-08-16 Toshiba Corp 半導体装置および半導体装置の製造方法
US7939862B2 (en) 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers
US7943531B2 (en) * 2007-10-22 2011-05-17 Applied Materials, Inc. Methods for forming a silicon oxide layer over a substrate
US7915112B2 (en) 2008-09-23 2011-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate stress film for mobility enhancement in FinFET device
US9953885B2 (en) * 2009-10-27 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. STI shape near fin bottom of Si fin in bulk FinFET
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US8937353B2 (en) * 2010-03-01 2015-01-20 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial process for a finFET device
JP2013093438A (ja) * 2011-10-26 2013-05-16 Renesas Electronics Corp 半導体装置の製造方法
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US9263585B2 (en) * 2012-10-30 2016-02-16 Globalfoundries Inc. Methods of forming enhanced mobility channel regions on 3D semiconductor devices, and devices comprising same
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BR112019004507A2 (pt) 2019-06-04
JP2019530227A (ja) 2019-10-17
CA3032965A1 (en) 2018-03-22
KR20190047696A (ko) 2019-05-08
EP3513437A1 (en) 2019-07-24
US9882051B1 (en) 2018-01-30
WO2018052591A1 (en) 2018-03-22
EP3513437C0 (en) 2024-10-30
EP3513437B1 (en) 2024-10-30
BR112019004507B1 (pt) 2023-10-03
CN109844957A (zh) 2019-06-04
KR102550579B1 (ko) 2023-07-03

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