JP6967656B2 - 2つの埋込電極を有する基板支持体 - Google Patents
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- H01L21/67103—Apparatus for thermal treatment mainly by conduction
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
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Description
本明細書で説明される諸実施形態は、概して、半導体製造で用いられる処理チャンバに関する。より具体的には、上に配置された基板にバイアスをかけるように構成された基板支持アセンブリを有する処理チャンバ、及び基板にバイアスをかける方法に関する。
高アスペクト比のフィーチャーを確実に作り出すことは、半導体デバイスの超大規模集積(VLSI)及び超超大規模集積(ULSI)という次世代に向けた重要な技術課題の1つである。高アスペクト比のフィーチャーを形成する、ある1つの方法では、プラズマ支援エッチング処理を用いて、基板の誘電体層などの材料層に高アスペクト比の開口部を形成している。典型的なプラズマ支援エッチング処理では、処理チャンバ内でプラズマを形成し、プラズマからのイオンを、基板とその上のマスクに形成された開口部とに向けて加速させて、マスク表面の下の材料層に開口部を形成する。通常は、400kHzから2MHzの範囲の低周波RF電力を基板に結合させることにより、イオンは基板に向かって加速され、これにより、そこにバイアス電圧が発生する。しかしながら、RF電力を基板に結合すると、基板にはプラズマに対する単一の電圧が印加されない。一般的に用いられる構成では、基板とプラズマの間の電位差は、ゼロに近い値から最大となる負の値までRF電力の周波数で振動する。プラズマから基板へイオンを加速させている電位が単一でないことにより、基板表面及びその材料層に形成される開口部(フィーチャー)では広範囲のイオンエネルギーがもたらされる。加えて、RFバイアスに起因するイオン軌跡の相違により、基板表面に対するイオンの角度分布は大きくなる。アスペクト比の高いフィーチャーの開口部をエッチングする場合、イオンエネルギーの範囲が広いことは望ましくない。それは、イオンが、望ましいエッチング速度を維持するのに十分な高エネルギーを有してフィーチャーの底部にまで到達しないからである。基板表面に対するイオンの角度分布が大きいことも望ましくない。それは、大きな角度分布は、フィーチャープロファイルの変形(その垂直側壁のくびれや曲がりなど)を引き起こすからである。
Claims (13)
- 第2誘電体層上に配置され、基板を支持する第1誘電体層と、
第1誘電体層と第2誘電体層との間に配置され、第1誘電体層の静電容量によって基板にパルスDC電力を容量結合する第1電極であって、
第1電極は、
平面部分と、
平面部分と基板支持面との間に配置された複数の伝導性フィーチャーと、
平面部分を複数の伝導性フィーチャーに電気的に接続する複数のコネクタとを備え、
平面部分は、
基板支持体の中心の周りに同心状に配置された複数の方位方向部分と、
複数の半径方向部分とを含み、
複数の半径方向部分の各半径方向部分は複数の方位方向部分の1つ以上の方位方向部分と接触している、第1電極と、
基板と第2電極の間に電位を与えることにより、基板を基板支持体に電気的にクランプする第2電極であって、第1電極から電気的に絶縁された第2電極とを備える基板支持体を備える基板支持アセンブリ。 - 第1電極及び第2電極は、互いに組み合わせられた構造を有している、請求項1に記載の基板支持アセンブリ。
- 第1電極の少なくとも一部が、第2電極よりも基板支持面の近くにある、請求項1に記載の基板支持アセンブリ。
- 第2電極の表面積の、第1電極の表面積に対する比が約80:10よりも大きい、請求項1に記載の基板支持アセンブリ。
- 第1誘電体層は、第1電極の少なくとも一部と基板支持面との間に配置され、約2μmから約200μmの間の厚さを有している、請求項4に記載の基板支持アセンブリ。
- 第1誘電体層は、第2誘電体層の上に形成された誘電体コーティングを含み、
複数の伝導性フィーチャーは第2誘電体層上に配置されている、請求項1に記載の基板支持アセンブリ。 - 第1誘電体層は約5μmから約200μmの間の厚さを有している、請求項1に記載の基板支持アセンブリ。
- 第1誘電体層は、約100V/μmから約200V/μmの絶縁破壊電圧を有している、請求項1に記載の基板支持アセンブリ。
- 処理容積を画定する1つ以上の側壁及び底部と、
処理容積内に配置された基板支持アセンブリであって、
熱伝導性材料で形成された冷却ベースと、
冷却ベースに熱的に結合された基板支持体であって、誘電体材料の第1層と誘電体材料の第2層とを含む基板支持体と、
誘電体材料の第1層と誘電体材料の第2層の間に配置され、誘電体材料の第1層の静電容量によってパルスDC電力を基板に容量結合する第1電極であって、
第1電極は、
平面部分と、
平面部分と基板支持面との間に配置された複数の伝導性フィーチャーと、
平面部分を複数の伝導性フィーチャーに電気的に接続する複数のコネクタとを備え、
平面部分は、
基板支持体の中心の周りに同心状に配置された複数の方位方向部分と、
複数の半径方向部分とを含み、
複数の半径方向部分の各半径方向部分は複数の方位方向部分の1つ以上の方位方向部分と接触している、第1電極と、
基板と第2電極の間に電位を与えることにより、基板を基板支持体に電気的にクランプする第2電極であって、第1電極から電気的に絶縁された第2電極とを備える基板支持アセンブリとを備える処理チャンバ。 - 第1電極と、第2電極の少なくとも一部とが平面的に配置されている、請求項9に記載の処理チャンバ。
- 第1電極の少なくとも一部が、第2電極よりも基板支持面の近くにある、請求項9に記載の処理チャンバ。
- 処理ガスを処理チャンバに流入させる工程と、
処理ガスからプラズマを形成する工程と、
基板と基板支持体に配置された第1電極との間に電位を与えることにより、処理チャンバに配置された基板支持体に基板を電気的にクランプする工程であって、
基板支持体は第1誘電体層及び第2誘電体層を含み、
第1電極は、
平面部分と、
平面部分と基板支持面との間に配置された複数の伝導性フィーチャーと、
平面部分を複数の伝導性フィーチャーに電気的に接続する複数のコネクタとを備え、
平面部分は、
基板支持体の中心の周りに同心状に配置された複数の方位方向部分と、
複数の半径方向部分とを含み、
複数の半径方向部分の各半径方向部分は複数の方位方向部分の1つ以上の方位方向部分と接触している、工程と、
第2電極に供給されるパルスDC電力を、第1誘電体層の静電容量によって基板に容量結合する工程であって、第2電極の少なくとも一部は第1誘電体層と第2誘電体層との間に配置されている工程とを含む、基板を処理する方法。 - 第1電極及び第2電極は互いに平面的に配置され、
第1電極の第1表面積の、第2電極の第2表面積に対する比が、約80:10よりも大きい、請求項12に記載の方法。
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US15/710,700 US10811296B2 (en) | 2017-09-20 | 2017-09-20 | Substrate support with dual embedded electrodes |
US15/710,700 | 2017-09-20 | ||
PCT/US2018/042961 WO2019060029A1 (en) | 2017-09-20 | 2018-07-19 | SUBSTRATE SUPPORT WITH DOUBLE INTEGRATED ELECTRODES |
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