JP6958300B2 - 多層回路基板 - Google Patents
多層回路基板 Download PDFInfo
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- JP6958300B2 JP6958300B2 JP2017229349A JP2017229349A JP6958300B2 JP 6958300 B2 JP6958300 B2 JP 6958300B2 JP 2017229349 A JP2017229349 A JP 2017229349A JP 2017229349 A JP2017229349 A JP 2017229349A JP 6958300 B2 JP6958300 B2 JP 6958300B2
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- 239000004020 conductor Substances 0.000 claims description 227
- 239000004744 fabric Substances 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 257
- 238000004519 manufacturing process Methods 0.000 description 21
- 238000000034 method Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 12
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 238000000059 patterning Methods 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- 230000001902 propagating effect Effects 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
図1は、本発明の第1の実施形態による多層回路基板100の構成を説明するための模式的な断面図である。
図17は、本発明の第2の実施形態による多層回路基板200の構成を説明するための模式的な断面図である。
図18は、本発明の第3の実施形態による多層回路基板300の構成を説明するための模式的な断面図である。
110,120,121,122,130,140,150,160 絶縁層
190 半導体チップ
191 端子電極
300a 基板の主面
300b 基板の側面
310 電子部品
320 モールド部材
CL クリアランス領域
L1〜L4 導体層
M 側面導体
OP1,OP2,OP4 開口部
P1〜P4 導体パターン
P3g 導体パターン(グランドパターン)
S1,S2 シールド層
S3 シールド導体
V1〜V4 ビア
VM1〜VM4 ビア導体
Claims (8)
- 絶縁層を介して積層された複数の導体層を備える多層回路基板であって、
前記複数の導体層は、第1及び第2の導体層と、前記第1の導体層と前記第2の導体層の間に配置された第1のシールド層とを含み、
前記第1のシールド層は、前記第1及び第2の導体層よりも導体厚が薄く、且つ、面内において前記複数の導体層のいずれにも接続されておらず、
前記第1のシールド層は、導体パターンが存在しないクリアランス領域を有し、
前記第1の導体層と前記第2の導体層は、前記クリアランスを貫通して設けられたビア導体を介して互いに接続されており、
前記ビア導体は、前記第1の導体層に接続された部分の径が前記第2の導体層に接続された部分の径よりも大きく、
前記絶縁層は、前記第1の導体層と前記第1のシールド層の間に設けられた第1の絶縁層と、前記第2の導体層と前記第1のシールド層の間に設けられた第2の絶縁層とを含み、
前記第1の絶縁層は、前記第2の絶縁層よりも厚いことを特徴とする多層回路基板。 - 側面に形成された側面導体をさらに備え、
前記第1のシールド層は、前記側面導体を介して前記複数の導体層のいずれかに接続されていることを特徴とする請求項1に記載の多層回路基板。 - 主面に搭載された電子部品と、
前記電子部品を埋め込むよう前記主面を覆うモールド部材と、
前記モールド部材の表面を覆うシールド導体と、をさらに備え、
前記シールド導体は、前記側面導体を介して前記第1のシールド層に接続されていることを特徴とする請求項2に記載の多層回路基板。 - 前記第1の絶縁層は、前記第2の絶縁層よりもガラスクロスの含有量が多いことを特徴とする請求項1乃至3のいずれか一項に記載の多層回路基板。
- 前記第2の絶縁層は、前記第1の絶縁層よりも誘電率が低いことを特徴とする請求項1乃至4のいずれか一項に記載の多層回路基板。
- 前記絶縁層に埋め込まれた半導体チップをさらに備えることを特徴とする請求項1乃至5のいずれか一項に記載の多層回路基板。
- 前記複数の導体層は、第3及び第4の導体層と、前記第3の導体層と前記第4の導体層の間に配置された第2のシールド層とをさらに含み、
前記半導体チップは、前記第1のシールド層と前記第2のシールド層の間に配置され、
前記第2のシールド層は、前記第1乃至第4の導体層よりも導体厚が薄く、且つ、面内において前記複数の導体層のいずれにも接続されていないことを特徴とする請求項6に記載の多層回路基板。 - 前記第1のシールド層の導体厚は、前記第1及び第2の導体層の導体厚の1/5以下であることを特徴とする請求項1乃至7のいずれか一項に記載の多層回路基板。
Priority Applications (2)
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JP2017229349A JP6958300B2 (ja) | 2017-11-29 | 2017-11-29 | 多層回路基板 |
US16/185,596 US10741502B2 (en) | 2017-11-29 | 2018-11-09 | Multilayer circuit board |
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JP2017229349A JP6958300B2 (ja) | 2017-11-29 | 2017-11-29 | 多層回路基板 |
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JP2019102536A JP2019102536A (ja) | 2019-06-24 |
JP6958300B2 true JP6958300B2 (ja) | 2021-11-02 |
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JP (1) | JP6958300B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW202112670A (zh) | 2019-05-31 | 2021-04-01 | 日商三菱綜合材料股份有限公司 | 壓電體膜之製造方法、壓電體膜及壓電元件 |
WO2020250795A1 (ja) * | 2019-06-10 | 2020-12-17 | 株式会社ライジングテクノロジーズ | 電子回路装置 |
CN110783318B (zh) * | 2019-10-28 | 2022-09-16 | 潍坊歌尔微电子有限公司 | 一种传感器封装结构以及电子设备 |
CN113132853A (zh) * | 2019-12-30 | 2021-07-16 | 楼氏电子(苏州)有限公司 | 麦克风组件、印刷电路板、印刷电路板阵列和制造方法 |
CN111863406B (zh) * | 2020-08-14 | 2022-05-24 | 阳光电源股份有限公司 | 一种线圈绕组、变压器和串并型电力电子装置 |
US12055633B2 (en) * | 2020-08-25 | 2024-08-06 | Lumentum Operations Llc | Package for a time of flight device |
US11610847B2 (en) * | 2021-05-07 | 2023-03-21 | STATS ChipPAC Pte. Ltd. | Laser-based redistribution and multi-stacked packages |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002335058A (ja) * | 2001-05-09 | 2002-11-22 | Matsushita Electric Ind Co Ltd | 積層セラミック基板及びその製造方法 |
JP2003168862A (ja) * | 2001-12-03 | 2003-06-13 | Fujikura Ltd | 銅張積層板、フレキシブルプリント回路及びこれらの製造方法 |
CN101653053B (zh) * | 2008-01-25 | 2012-04-04 | 揖斐电株式会社 | 多层线路板及其制造方法 |
JP5416458B2 (ja) * | 2009-04-02 | 2014-02-12 | タツタ電線株式会社 | シールドおよび放熱性を有する高周波モジュールの製造方法 |
JP5672091B2 (ja) | 2011-03-17 | 2015-02-18 | 株式会社村田製作所 | 多層基板 |
US20140061877A1 (en) * | 2012-08-14 | 2014-03-06 | Bridge Semiconductor Corporation | Wiring board with embedded device, built-in stopper and electromagnetic shielding |
US9362234B2 (en) * | 2014-01-07 | 2016-06-07 | Freescale Semiconductor, Inc. | Shielded device packages having antennas and related fabrication methods |
JP2015141904A (ja) * | 2014-01-27 | 2015-08-03 | アルプス電気株式会社 | 電子回路モジュール及びその製造方法 |
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- 2017-11-29 JP JP2017229349A patent/JP6958300B2/ja active Active
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- 2018-11-09 US US16/185,596 patent/US10741502B2/en active Active
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US20190164904A1 (en) | 2019-05-30 |
JP2019102536A (ja) | 2019-06-24 |
US10741502B2 (en) | 2020-08-11 |
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