JP6921799B2 - 基板処理方法および基板処理システム - Google Patents
基板処理方法および基板処理システム Download PDFInfo
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- JP6921799B2 JP6921799B2 JP2018225894A JP2018225894A JP6921799B2 JP 6921799 B2 JP6921799 B2 JP 6921799B2 JP 2018225894 A JP2018225894 A JP 2018225894A JP 2018225894 A JP2018225894 A JP 2018225894A JP 6921799 B2 JP6921799 B2 JP 6921799B2
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/042—Coating on selected surface areas, e.g. using masks using masks
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Description
本実施形態に係る基板処理に使用する装置の一例を説明する。以下では、プラズマ処理装置と加熱装置によって本実施形態に係る基板処理する場合を例に説明する。
11 SiO2膜
20 SiO2膜
100 プラズマ処理装置
200 加熱装置
P パターン
W ウエハ
Claims (14)
- マスクを備える基板を提供する工程と、
前記マスク上に膜を成膜する工程と、
前記膜の表層に反応層を形成する工程と、
前記反応層にエネルギーを与えて前記反応層を除去する工程と、
を有する基板処理方法。 - 前記形成する工程では、形成する反応層の厚さに応じて前記基板の温度を設定する
請求項1に記載の基板処理方法。 - 前記成膜する工程は、Chemical Vapor Deposition(CVD)、Physical Vapor Deposition(PVD)、Atomic Layer Deposition(ALD)の何れか1つ、または、複数の組み合わせによりシリコン含有膜を成膜する
請求項1または2に記載の基板処理方法。 - 前記マスクは、パターンを有し、
前記成膜する工程は、前記パターンの上部側に下部側よりも多くシリコン含有膜を成膜する場合、CVD、QALD(Quasi-ALD)の何れか1つ、または、何れか含んだ複数の組み合わせによりシリコン含有膜を成膜し、前記パターンの上部側と下部側に同程度シリコン含有膜を成膜する場合、ALDにより成膜する
請求項1〜3の何れか1つに記載の基板処理方法。 - 前記マスクは、粗密にパターンを含み、
前記形成する工程は、前記反応層を形成する際の前記基板の温度を制御することにより、密に形成されたパターンと粗く形成されたパターンのパターン幅を制御する
請求項1〜4の何れか1つに記載の基板処理方法。 - 前記成膜する工程、前記形成する工程および前記除去する工程を順に複数サイクル繰り返す
請求項1〜5の何れか1つに記載の基板処理方法。 - 前記マスクは、ハードマスクである
請求項1〜6の何れか1つに記載の基板処理方法。 - 前記マスクは、SiO2で形成される
請求項1〜7の何れか1つに記載の基板処理方法。 - 前記基板は、被エッチング膜上に前記マスクが設けられ、
前記反応層を形成する工程の後かつ前記反応層を除去する工程の前、または、前記反応層を除去する工程の後、前記被エッチング膜をエッチングする工程をさらに有する
請求項1〜8の何れか1つに記載の基板処理方法。 - マスクを備える基板が配置される処理室と、
前記処理室内に成膜用のガスおよび反応層形成用のガスをそれぞれ供給可能なガス供給部と、
前記処理室内にエネルギーを供給可能なエネルギー供給部と、
前記ガス供給部から前成膜用のガスを供給して前記マスク上に膜を成膜し、前記ガス供給部から前記反応層形成用のガスを供給して前記膜の表層に反応層を形成し、前記エネルギー供給部から前記反応層にエネルギーを与えて前記反応層を除去するよう制御する制御部と、
を有する、基板処理システム。 - 前記処理室として、第1処理室と第2処理室とが設けられ、
前記第1処理室において前記マスク上に膜を成膜し、前記第2処理室において前記反応層を除去する
請求項10に記載の基板処理システム。 - 前記処理室として、第1処理室と第2処理室とが設けられ、
前記第1処理室において前記反応層を形成し、前記第2処理室において前記反応層を除去する
請求項10または11に記載の基板処理システム。 - 前記反応層を形成する工程においては、前記基板の温度を100℃以下にし、
前記反応層を除去する工程においては、前記基板の温度を100℃超にする、
請求項1〜9の何れか1つに記載の基板処理方法。 - 前記膜は、SiO 2 であり、
前記反応層は、Ammonium FluoroSilicate(AFS)である
請求項1〜9及び13の何れか1つに記載の基板処理方法。
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