JP6904044B2 - Substrate for semiconductor package and its manufacturing method - Google Patents

Description

The present invention relates to a substrate for a semiconductor package and a method for manufacturing the same.

The method for manufacturing a semiconductor package substrate (hereinafter, also simply referred to as a package substrate) is a large-format wiring board (hereinafter, also simply referred to as a package substrate) in which a package substrate is multifaceted by laminating a wiring layer and an insulating layer on the front and back surfaces of the core substrate. After forming the substrate panel), it is usual to dice the wiring board and separate it into a package substrate.

As the core substrate of a packaging substrate in recent years, a material typified by a glass substrate, which has excellent electrical characteristics but has a fragile cut surface, is used. Further, when the wiring board is manufactured, a plurality of resin layers and wiring layers having different linear expansion coefficients from the core substrate are laminated on the core substrate. Therefore, when there is a temperature change, the core due to the difference in linear expansion coefficient. It is known that stress is generated on the outer peripheral portion of the core substrate because the amount of expansion differs between the substrate, the resin layer, and the wiring layer. Therefore, when the core substrate is a brittle material such as a glass substrate in which cracks are likely to occur, the core substrate may crack (Non-Patent Document 1). In the case of a laminated body in which the core substrate is a glass substrate, a glass substrate thicker than several tens of μm tends to have a problem of tearing from its end face.

The cracks in the cross section of the core substrate may cause cracks in the direction in which the core substrate is torn because the internal stress accumulated inside the core substrate is released from the scratched portion immediately after dicing or in a subsequent step.

As a technique for solving this problem, in Patent Document 1, a plurality of resin layers and wiring layers having different linear expansion coefficients from the core substrate are laminated on the front and back surfaces of a core substrate formed of a brittle material such as a glass substrate. The wiring board is disclosed. In this wiring board, a groove is formed inward from the surface of the side surface of the wiring board of the resin layer in contact with the peripheral edge of the core substrate, thereby separating the peripheral edge of the core substrate from the resin layer. Thermal stress is not generated at the peripheral edge of the substrate.

However, in this technique, since the metal layer on the core substrate is cut by the dicing blade, there is a concern that many cracks may be generated in the cross section of the core substrate due to a decrease in cutting force due to clogging of the dicing blade. In addition, there is a concern that the core substrate may be destroyed immediately after being separated by the dicing process.

JP 2015-231005

“Empirical investigations on Die Edge Defects Glass-Panel Based Interposer for Advanced Packaging” Frank Wei, et, al, 2015 Electronic Components & Technology Conference (2015)

Therefore, in the present invention, an insulating layer and a wiring layer are laminated on a core substrate made of a brittle material (the laminate of the insulating layer and the wiring layer is hereinafter referred to as a build-up layer). An object of the present invention is to provide a wiring board that does not cause damage to the cut surface of the board so as to affect reliability.

As a means for solving the above problems, the invention according to claim 1 of the present invention is a build-up in which at least a pair of wiring layers and an insulating layer are laminated in this order on the front and back surfaces of a core substrate made of a brittle material. A substrate for a semiconductor package having layers
A stress relaxation structure is provided between the core substrate and the insulating layer at the side end of the semiconductor package substrate .
The stress relaxation structure includes a resin layer provided on the core substrate and an adhesion layer provided on the resin layer in contact with the insulating layer.
The adhesive layer is a layer that reacts with the functional groups of organic substances contained in the insulating layer.
The resin layer contains an inorganic material
The bonding force between the resin layer and the adhesive layer, or at least one of the bonding force between the adhesive layer and the insulating layer is smaller than the bonding force inside the resin layer and the bonding force inside the insulating layer. It is a characteristic substrate for a semiconductor package.

The invention according to claim 2 is the package substrate for a semiconductor according to claim 1 , wherein the adhesion layer contains a silane coupling agent.

The invention according to claim 3 is the substrate for a semiconductor package according to claim 1 or 2, wherein the brittle material is glass.

The invention according to claim 4 is to manufacture a substrate for a semiconductor package, which comprises a build-up layer in which at least a pair of wiring layers and an insulating layer are laminated in this order on the front and back surfaces of a core substrate made of a brittle material. It's a method
The process of forming wiring layers on the front and back of the board panel,
A process of forming a resin layer at a position that becomes a peripheral edge of a substrate for a semiconductor package of a substrate panel, and forming a stress relaxation structure by forming an adhesion layer on the entire surface of the substrate panel including the resin layer.
By dicing a predetermined position of the substrate panel, Bei example a step of singulating a substrate for a semiconductor package, a,
The adhesive layer is a layer that reacts with the functional groups of organic substances contained in the insulating layer.
The resin layer contains an inorganic material
A semiconductor package in which at least one of the bonding force between the resin layer and the adhesive layer or the bonding force between the adhesive layer and the insulating layer is smaller than the bonding force inside the resin layer and the bonding force inside the insulating layer. This is a method for manufacturing a substrate.

The invention according to claim 5 is the method for manufacturing a semiconductor package substrate according to claim 4, wherein the adhesion layer contains a silane coupling agent.

The invention according to claim 6 is the method for manufacturing a substrate for a semiconductor package according to claim 4 or 5 , wherein the brittle material is glass.

According to the semiconductor package substrate of the present invention, although the core substrate made of a brittle material is used, since the stress relaxation structure is provided at the side end of the package substrate, the panel substrate on which the package substrate is multi-imposed. The core substrate made of a brittle material is not damaged or damaged even when the package substrate is manufactured or the package substrate undergoes various thermal histories. It is possible to provide a highly reliable semiconductor package substrate.

Further, according to the method for manufacturing a semiconductor package substrate of the present invention, the semiconductor package substrate of the present invention can be manufactured.

It is sectional drawing which illustrates the schematic structure of the substrate (structure 1) for a package of this invention. It is sectional drawing which illustrates the schematic structure of the substrate (structure 2) for a package of this invention. It is sectional drawing explaining the manufacturing process of the packaging substrate (structures 1 and 2) of this invention. It is sectional drawing explaining the manufacturing process of the packaging substrate (structures 1 and 2) of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 1) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 1) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 1) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 1) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 1) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 2) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 2) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 2) for a package of this invention. It is sectional drawing explaining the manufacturing process of the substrate (structure 2) for a package of this invention.

Hereinafter, embodiments of the wiring board and its manufacturing method according to the present invention will be described in detail with reference to the drawings. The embodiments shown below are merely examples of the present invention, and those skilled in the art can appropriately change the design.

As used herein, the term "packaged substrate" refers to an individualized laminate. Further, the “board panel” refers to a state in which the packaging boards before being separated into individual pieces by dicing are connected (multi-imposed). Generally, in the substrate manufacturing stage, the substrate is manufactured in the state of a substrate panel, and then individualized in a dicing step to obtain a substrate for packaging.

<Structure 1>
The structure 1 which is the first embodiment of the packaging substrate of this invention will be described.
FIG. 1 is an end view of a cut portion showing a schematic configuration of a structure 1 which is a first embodiment of a packaging substrate of the present application. The packaging substrate 100 in this embodiment includes a core substrate 10 and a build-up layer 50 composed of a wiring layer 20 laminated on both sides of the core substrate 10 in the thickness direction and an insulating layer 30.

(Core board)
The material of the core substrate 10 is not particularly limited as long as it is a material that improves the electrical characteristics of the substrate panel (not shown) and the packaging substrate 100 after the substrate panel is separated into individual pieces. For example, as the core substrate 10, a glass substrate, a silicon substrate, a ceramic substrate, a plastic plate, a plastic tape, or the like can be used. A glass substrate is preferable. The glass substrate used for the core substrate 10 of the present invention may have a surface treated by a method generally used in the art. For example, the surface may be roughened, hydrofluoric acid may be used, or the surface of the glass substrate may be siliconized. In one aspect of the present invention, the glass substrate used for the core substrate 10 may have a base layer (not shown) formed on the surface thereof.

The thickness of the core substrate 10 is not particularly limited, but is preferably 100 μm to 500 μm.

(Through hole formation)
First, a through hole 70 is formed in the core substrate 10. Examples of the method for forming the through hole 70 include electric discharge machining, laser machining, treatment with a chemical solution such as hydrofluoric acid, or a combination thereof, but any method may be used, and the method is limited thereto. It's not a thing.

(Wiring layer formation)
Next, the wiring layer 20 is formed. The wiring layer 20 can be formed by using a conductive material usually used in the art. Specifically, the wiring layer 20 can be formed by using copper, silver, tin, gold, tungsten, a conductive resin, or the like. As a means for forming the metal layer, various film forming methods such as plating, vacuum deposition, ion plating, and sputtering can be used. For the wiring layer made of the conductive resin, various conductive inks can be formed by using various printing methods (inkjet method, screen printing, gravure offset printing, etc.). As the material of the wiring layer 20, copper is preferably used from the viewpoint of easy handling, high conductivity, and cost. The wiring forming method is not limited, but can be formed by a method generally used in the art. For example, it is possible to use a subtractive method using various metal materials or a full additive method using Cu plating, but a Cu plated wiring by a semi-additive method can be preferably used. As a method for forming an etching resist pattern in the subtractive method, when a photosensitive etching resist is used, it can be carried out by a normal photolithography step. When a non-photosensitive etching resist is used, pattern formation can be performed by using various printing methods such as an inkjet method, screen printing, and gravure offset printing.

(Stress relaxation structure formation)
Next, the resin layer 60 is formed. Examples of the method for forming the resin layer 60 include, but are not limited to, pattern formation using a photosensitive resist and printing patterning of a liquid resist. The position where the resin layer 60 is formed is the peripheral edge of the package substrate 100 of the substrate panel on which the package substrate 100 is multifaceted. The substrate panel is diced and separated into individual pieces to form a package substrate, which is formed at a position where the resin layer 60 is exposed at the side end portion (side cross section cut out by the dicing process) of the package substrate 100. To do.

Next, the adhesion layer 1 is formed. Examples of the adhesion layer 1 include, but are not limited to, a silane coupling agent and the like. By this step, it is possible to obtain a packaging substrate 100 having a core substrate / resin layer interface having partially different adhesions on the side end faces.
In the structure in which the adhesive layer 1 is formed on the resin layer 60, the adhesive layer 1 can weaken the adhesive force with the insulating layer 30 and relieve stress. Therefore, even if stress is applied to the side end portion of the package substrate 100, it functions as a stress relaxation structure 300 in which the stress is relaxed.

As the adhesion layer 1 that functions in this way, a material such as the above-mentioned silane coupling agent can be applied. Since the silane coupling agent has a functional group that binds to an organic material at one end and a functional group that can bind to an inorganic material at the other end, it is a material that can bind them.

In such a structure of the organic material layer / silane coupling agent layer / inorganic material layer, the bonding force between the organic material layer and the silane coupling agent layer or the bonding force between the silane coupling agent layer and the inorganic material layer is organic. It can be made smaller than the binding force inside the material layer or the binding force inside the inorganic material layer.

As such, by weakening the bonding force between the organic material layer / silane coupling agent layer or between the silane coupling agent layer / inorganic material layer, when stress is applied, it slides between them. The stress can be relieved by the occurrence of

For example, by adjusting the concentration of the inorganic material added to the resin layer 60, it is possible to weaken the bonding force between the layers. In this way, the stress relaxation structure 300 can be formed.

(Build-up layer formation)
The build-up layer 50 is formed on the surface of the core substrate 10 in the thickness direction. The build-up layer 50 is composed of a wiring layer 20 and an insulating layer 30, and may be a pair of layers, or the pair of layers may be a plurality of layers.

The wiring layer 20 can be formed by using a conductive material usually used in the art. Specifically, the wiring layer 20 can be formed by using copper, silver, tin, gold, tungsten, a conductive resin, or the like. Copper is preferably used.

Further, the wiring layer 20 can be formed by a method generally used in the art. The method for forming the wiring layer 20 is not limited to these, but a subtractive method, a semi-additive method, an inkjet method, screen printing, and gravure offset printing can be used. The semi-additive method is preferable.

The insulating layer 30 can be formed by using an insulating material commonly used in the art. Specifically, the insulating layer 30 can be formed by using an epoxy resin-based material, an epoxy acrylate-based resin, a polyimide-based resin, or the like. These insulating materials may include a filler. As the insulating material forming the insulating layer 30 of the present invention, an epoxy compound resin having a linear expansion coefficient of 7 to 130 ppm is generally easily available and preferable.

Further, the insulating material may be in the form of a liquid or a film. When the insulating material is liquid, the insulating layer 30 is formed by a method generally used in the art such as a spin coating method, a die coater method, a curtain coater method, a roll coater method, a doctor blade method, and screen printing. be able to. When the insulating material is in the form of a film, the insulating layer 30 can be formed by, for example, a vacuum laminating method. The insulating layer 30 formed as described above may be cured by heating or light irradiation.

Further, the above-mentioned through hole 70 may be filled at the time of forming the insulating layer. The through hole 70 may be filled by Cu plating at the time of forming the wiring, filling with a conductive paste after forming the wiring, or filling with a resin, and any method may be used.

(SR formation, surface treatment)
The method and material for forming the outermost layer are not particularly limited, but a photosensitive resin material 40 called a solder resist is often formed. Further, as the surface treatment of the wiring layer, OSP (Organic Soldereraviity Preservatives, a kind of heat-resistant surface treatment for preventing copper oxidation due to heat) treatment, gold plating treatment, Sn plating treatment and the like may be formed. It is not limited to.

The method and material for forming the outermost layer are not particularly limited, but a photosensitive resin material 40 called a solder resist is often formed. Further, as the surface treatment of the wiring layer, an OSP treatment, a gold plating treatment, a Sn plating treatment and the like may be formed, but this is also not limited.

(Individualization)
Next, the substrate panel on which the packaging substrate 100 is mounted on multiple surfaces is diced and individualized to obtain the packaging substrate 100. At this time, cracks are likely to occur near the interface with the core substrate 10. This is because the impact generated during dicing causes minute cracks on the end faces of the core substrate 10, and the thermal stresses of the wiring layer 20 and the insulating layer 30 generate tensile stress on the core substrate 10 to cause the core. This is to enlarge cracks on the side end faces of the substrate 10.
However, according to the present invention, the core substrate 10 and the resin layer 60 in the region where microcracks occur are not in close contact with each other, or are in a state of being peeled off by a minute stress. Therefore, it is possible to suppress the phenomenon that the wiring layer 10 and the resin layer 60 generate tensile stress and expand cracks on the side end faces of the core substrate 10.

Next, the structure 2 which is the second embodiment of the packaging substrate of the present invention will be described.

<Structure 2>
FIG. 2 is an end view of a cut portion showing a schematic configuration of a structure 2 which is a second embodiment of the packaging substrate of the present application. The packaging substrate 101 in this embodiment is the core substrate 1
Includes 0 and a build-up layer 50 composed of a wiring layer 20 laminated on both sides of the core substrate 10 in the thickness direction and an insulating layer 30.

(Core board)
The core substrate 10 may be any material that improves the electrical characteristics of the substrate panel on which the core substrate 10 is mounted on multiple surfaces and the packaging substrate 100 after the substrate panels are separated into individual pieces. For example, as the core substrate 10, a glass substrate, a silicon substrate, a ceramic substrate, a plastic plate, a plastic tape, or the like can be used. A glass substrate is preferable. The glass substrate used for the core substrate 10 of the present invention may have a surface treated by a method generally used in the art. For example, the surface may be roughened, hydrofluoric acid may be used, or the surface of the glass substrate may be siliconized. In one aspect of the present invention, the glass substrate used for the core substrate 10 may have a base layer (not shown) formed on the surface thereof.

The thickness of the core substrate 10 is not particularly limited, but is preferably 100 μm to 500 μm.

(Through hole formation)
First, a through hole 70 is formed in the core substrate 10. The method of forming the through hole 70 includes, but is not limited to, an electric discharge machining, a laser machining, a chemical treatment such as hydrofluoric acid, or a combination thereof.

(Wiring layer formation)
Next, the wiring layer 20 is formed. The wiring layer 20 can be formed by using a conductive material usually used in the art. Specifically, the wiring layer 20 can be formed by using copper, silver, tin, gold, tungsten, a conductive resin, or the like. Copper is preferably used. The wiring formation method is not limited. As a wiring forming method, for example, there is a Cu-plated wiring by a semi-additive method.

(Stress relaxation structure formation)
In the method for producing structure 2 according to the second embodiment of the present application, the resin 61, which can be easily removed in a subsequent step, is then formed with, for example, an alkali-developed photosensitive resist. At this time, the thickness of the resin layer 61 that can be peeled or dissolved is preferably 5 μm or less. By setting the thickness to 5 μm or less, the thickness of the groove after removal can be set to 5 μm or less, and it is possible to suppress the problem that the insulating layer is chipped during dicing due to the partial step. The position where the peelable or soluble resin layer 61 is formed is the peripheral edge of the package substrate 101 of the substrate panel on which the package substrate 101 is multi-imposed. A package substrate 101 is obtained by dicing the substrate panel into individual pieces, and the resin layer 61 is exposed at the side end portion (side cross section cut out by the dicing process) of the package substrate 101. Form.
The groove or space formed by removing the resin layer 61 after being separated into the package substrate 101 becomes the stress relaxation structure 301.

(Build-up layer formation)
The build-up layer 50 is formed on the surface of the core substrate 10 in the thickness direction. The build-up layer 50 is composed of a wiring layer 20 and an insulating layer 30, and may be a pair of layers, or the pair of layers may be a plurality of layers.

The wiring layer 20 can be formed by using a conductive material usually used in the art. Specifically, the wiring layer 20 can be formed by using copper, silver, tin, gold, tungsten, a conductive resin, or the like. Copper is preferably used.

Further, the wiring layer 20 can be formed by a method generally used in the art. The method for forming the wiring layer 20 is not limited to these, but a subtractive method, a semi-additive method, an inkjet method, screen printing, and gravure offset printing can be used. The semi-additive method is preferable.

The insulating layer 30 can be formed by using an insulating material commonly used in the art. Specifically, the insulating layer 30 can be formed by using an epoxy resin-based material, an epoxy acrylate-based resin, a polyimide-based resin, or the like. These insulating materials may include a filler. As the insulating material forming the insulating layer 30 of the present invention, an epoxy compound resin having a linear expansion coefficient of 7 to 130 ppm is generally easily available and preferable.

Further, the insulating material may be in the form of a liquid or a film. When the insulating material is liquid, the insulating layer 30 is formed by a method generally used in the art such as a spin coating method, a die coater method, a curtain coater method, a roll coater method, a doctor blade method, and screen printing. be able to. When the insulating material is in the form of a film, the insulating layer 30 can be formed by, for example, a vacuum laminating method. The insulating layer 30 formed as described above may be cured by heating or light irradiation.

Further, the above-mentioned through hole 70 may be filled at the time of forming the insulating layer. The through hole 70 may be filled by Cu plating at the time of forming the wiring, filling with a conductive paste after forming the wiring, or filling with a resin, and any method may be used.

(SR formation, surface treatment)
The method and material for forming the outermost layer are not particularly limited, but a photosensitive resin material 40 called a solder resist is often formed. Further, as the surface treatment of the wiring layer, an OSP treatment, a gold plating treatment, a Sn plating treatment and the like may be formed, but this is also not limited.

(Individualization)
Next, the substrate panel on which the package substrate 101 is multi-imposed is separated into individual pieces to obtain the package substrate 101.

(Groove formation: stress relaxation structure formation)
In the structure 2, the removable resin 61 exposed after the individualization is removed. When an alkali-developed photosensitive dry film resist is used, it can be removed with a material generally used in the peeling step at the time of pattern formation, such as an amine-based stripping solution or an aqueous sodium hydroxide solution.
According to the present invention, a groove (space) is formed between the core substrate 10 and the insulating layer 30 in the region where microcracks are generated on the side end surface of the core substrate 10. Therefore, it is possible to suppress the phenomenon that the wiring layer 20 and the insulating layer 30 generate tensile stress and expand the cracks in the core substrate 10. This groove (space) functions as a stress relaxation structure 301.

Hereinafter, the present invention and its effects will be described with reference to specific examples, but the examples do not limit the scope of application of the present invention.

<Example 1>

First, as shown in FIG. 3, a substrate panel 200 (aluminosilicate glass) having a plate thickness of 300 μm was prepared, and through holes 70 were formed at necessary locations. The through hole 70 was formed by electric discharge machining.

Next, as shown in FIG. 4, a wiring layer 20 having a thickness of 10 μm was formed on the surface of the substrate panel 200 in the thickness direction by copper plating. The semi-additive method was used to form the wiring layer 20.

Next, as shown in FIG. 5, a solder resist, which is a photosensitive material, is applied to the front and back surfaces of the substrate panel 200 on which the wiring layer 20 is formed, and photolithography is performed at a position corresponding to the outer peripheral portion of the piece (package substrate 100). The resin layer 60 was formed by patterning.

Next, as shown in FIG. 6, a silane coupling agent was applied as the adhesion layer 1.

Next, as shown in FIG. 7, the build-up layer 50 was obtained by repeating the formation of the wiring layer 20, the formation of the insulating layer 30, and the via processing for obtaining continuity between the layers.

Next, as shown in FIG. 8, a solder resist 40 was formed, and the bonding pad 80 was exposed by a photolithography process.

Next, as shown in FIG. 9, the substrate panel 200 was diced with the dicing blade 90 to obtain the package substrate 100 shown in FIG. The width of the tip of the dicing blade 90 was 150 μm.

The packaging substrate 100 thus produced was not cracked or damaged from the side end surface of the core substrate 10 even after dicing and thermal history.

(Example 2)
First, as shown in FIG. 3, a substrate panel 201 (aluminosilicate glass) having a plate thickness of 300 μm was prepared, and a through hole 70 was formed in the substrate panel 201. The through hole 70 was formed by electric discharge machining.

Next, as shown in FIG. 4, a wiring layer 20 having a thickness of 10 μm was formed on the surface of the substrate panel 201 in the thickness direction by copper plating. The semi-additive method was used to form the wiring layer 20.

Next, as shown in FIG. 10, a liquid resist, which is a photosensitive material, is applied to the front and back surfaces of the substrate panel 201 with a thickness of 5 μm, and peeled off at a position corresponding to the outer peripheral portion of the piece (package substrate 101) by photolithography. Alternatively, the soluble resin layer 61 was patterned.

Next, as shown in FIG. 11, the build-up layer 50 was obtained by repeating the formation of the wiring layer 20, the formation of the insulating layer 30, and the via processing for obtaining continuity between the layers.

Next, as shown in FIG. 12, a solder resist 40 was formed and the bonding pad 80 was exposed by a photolithography process.

Next, as shown in FIG. 13, the substrate panel 201 was diced by the dicing blade 90. The width of the tip of the dicing blade 90 was 150 μm. Next, the exposed peelable or soluble resin layer 61 was removed with an amine-based stripping solution to obtain the packaging substrate 101 shown in FIG.

The packaging substrate 101 thus produced was not cracked or damaged from the side end surface of the core substrate 10 even after dicing and thermal history.

1 Adhesive layer 10 Core substrate 20 Wiring layer 30 Insulation layer 40 Solder resist 50 Build-up layer 60 Resin layer 61 Peelable or soluble resin layer 70 Through hole 80 Bonding pad 90 Dicing blade 100 Package substrate (structure 1)
101 Package board (Structure 2)
200 Board panel (Structure 1)
201 Board panel (structure 2)
300 Stress relaxation structure (Structure 1)
301 Stress relaxation structure (Structure 2)

Claims (6)

A substrate for a semiconductor package having a build-up layer in which at least a pair of wiring layers and an insulating layer are laminated in this order on the front and back surfaces of a core substrate made of a brittle material.
A stress relaxation structure is provided between the core substrate and the insulating layer at the side end of the semiconductor package substrate .
The stress relaxation structure includes a resin layer provided on the core substrate and an adhesion layer provided on the resin layer in contact with the insulating layer.
The adhesive layer is a layer that reacts with the functional groups of organic substances contained in the insulating layer.
The resin layer contains an inorganic material
At least one of the bonding force between the resin layer and the adhesive layer or the bonding force between the adhesive layer and the insulating layer is smaller than the bonding force inside the resin layer and the bonding force inside the insulating layer. A substrate for a semiconductor package. The semiconductor package substrate according to claim 1, wherein the adhesion layer contains a silane coupling agent. The substrate for a semiconductor package according to claim 1 or 2, wherein the brittle material is glass. A method for manufacturing a substrate for a semiconductor package, which comprises a build-up layer in which at least a pair of wiring layers and an insulating layer are laminated in this order on the front and back surfaces of a core substrate made of a brittle material.
The process of forming wiring layers on the front and back of the board panel,
A process of forming a resin layer at a position that becomes a peripheral edge of a substrate for a semiconductor package of a substrate panel, and forming a stress relaxation structure by forming an adhesion layer on the entire surface of the substrate panel including the resin layer.
By dicing a predetermined position of the substrate panel, Bei example a step of singulating a substrate for a semiconductor package, a,
The adhesive layer is a layer that reacts with the functional groups of organic substances contained in the insulating layer.
The resin layer contains an inorganic material
At least one of the bonding force between the resin layer and the adhesive layer or the bonding force between the adhesive layer and the insulating layer is smaller than the bonding force inside the resin layer and the bonding force inside the insulating layer. A method for manufacturing a substrate for a semiconductor package. The method for manufacturing a semiconductor package substrate according to claim 4, wherein the adhesion layer contains a silane coupling agent. The method for manufacturing a substrate for a semiconductor package according to claim 4 or 5, wherein the brittle material is glass.

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