JP6894289B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP6894289B2
JP6894289B2 JP2017098311A JP2017098311A JP6894289B2 JP 6894289 B2 JP6894289 B2 JP 6894289B2 JP 2017098311 A JP2017098311 A JP 2017098311A JP 2017098311 A JP2017098311 A JP 2017098311A JP 6894289 B2 JP6894289 B2 JP 6894289B2
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Prior art keywords
layer
wiring
wiring layer
via hole
surface roughness
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Japanese (ja)
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JP2018195702A (ja
JP2018195702A5 (enExample
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洋一 西原
洋一 西原
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2017098311A priority Critical patent/JP6894289B2/ja
Priority to US15/978,500 priority patent/US10297540B2/en
Publication of JP2018195702A publication Critical patent/JP2018195702A/ja
Publication of JP2018195702A5 publication Critical patent/JP2018195702A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2017098311A 2017-05-17 2017-05-17 配線基板及びその製造方法 Active JP6894289B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017098311A JP6894289B2 (ja) 2017-05-17 2017-05-17 配線基板及びその製造方法
US15/978,500 US10297540B2 (en) 2017-05-17 2018-05-14 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017098311A JP6894289B2 (ja) 2017-05-17 2017-05-17 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2018195702A JP2018195702A (ja) 2018-12-06
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