JP6840310B2 - 密封電子モジュールのウェーハスケール製造のための工程 - Google Patents
密封電子モジュールのウェーハスケール製造のための工程 Download PDFInfo
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- JP6840310B2 JP6840310B2 JP2017233987A JP2017233987A JP6840310B2 JP 6840310 B2 JP6840310 B2 JP 6840310B2 JP 2017233987 A JP2017233987 A JP 2017233987A JP 2017233987 A JP2017233987 A JP 2017233987A JP 6840310 B2 JP6840310 B2 JP 6840310B2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 238000000151 deposition Methods 0.000 description 9
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- 229910052814 silicon oxide Inorganic materials 0.000 description 7
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- 230000001070 adhesive effect Effects 0.000 description 4
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
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- 239000003822 epoxy resin Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/036—Multilayers with layers of different types
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
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- H05K2201/01—Dielectrics
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1327—Moulding over PCB locally or completely
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- H05K3/22—Secondary treatment of printed circuits
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Description
− パッケージがプリント回路の表面に付加される前にパッケージの内部へ湿気が侵入することにより、260℃の最高温度で行われる、ボールを再溶融するステップの間に、このパッケージの内側に内部蒸気圧が作り出される。この現象は図2に例示されており、この図では、大気にさらされて、拡散P1による気体のH2Oを受ける、非密封ボール・グリッド・アレイ・パッケージ1を見ることが可能である(図に負荷をかけ過ぎないように構成部品は示されていない)。結果として生じる圧力P2は、大気圧からそのおよそ2倍((273+260)/273=1.95Kg/cm2)まで、数秒にわたって増加することになる。この圧力が内部応力を作り出し、そのエネルギーはパッケージに内部亀裂を形成することにより放散される。
− 水蒸気の侵入は、酸性(Cl、SO4など)または塩基性(Na、Kなど)のイオンの存在下で行われるので、チップの金属部分、特に、両性金属である、相互接続パッドを形成しているアルミニウムを攻撃するおそれがある、酸または塩基が形成される。
− 仏国特許出願第90 10631号明細書の下、1990年8月24日に申請された、”Method and device for hermetic encapsulation of electronic components”。
− 仏国特許出願第94 12726号明細書の下、1994年10月25日に申請された、”Method and device for hermetic protection of electronic circuit”。
− 仏国特許出願第01 14543号明細書の下、2001年11月9日に申請された、”Device for the hermetic encapsulation of a component that must be protected against all stresses”。
A) マスクまたは局所的剥離動作が必要とされる。
B) マスクの場合、特にはんだ付けするときのボールの再溶融の後に、ボールを取り囲む薄い無機物層がボールと完璧な密閉を形成しない危険性がある。隙間が存在してアセンブリの密封状態に悪影響を与える場合がある。
C) プラズマトーチなどの、パッケージを密封するためにこの付加的な堆積動作に必要とされる装置は、一般に、電子モジュールの製造業者によって彼らの自動化された保護生産ライン上で使用されない。
− 電気、磁気などの遮蔽の場合に金属層を堆積させること、または、
− 例えば、SiOxもしくは任意の他の酸化物(Al2O3など)、窒化物(Si3N4など)、または炭化物などで電気絶縁層を堆積させること
によって達成される。
− 薄い(数μmから数百μmの間の厚さ)シリカ充填エポキシ樹脂パネルを作り出し、次に、この技術が選択されるときの大気プラズマ蒸着の低いコストを考慮して、パネルの1つの面の上に、または2つの向かい合った面の上に(図に示されるように、それらを完全に覆うように)、厚さが0.1から1μmの間に含まれるSiOxなどの無機物被覆を堆積させる方法であって、任意選択で、このように密封されたこのパネルは、特にそれが薄いとき、その後両側に接着剤の層で被覆してもよい。不活性な密封層(またはレベル)がこのように得られる。
− 一般的に0.1mmから0.8mmの間に含まれる厚さを有する、その面の片方または両方に導電素子をすでに含むシリカ充填エポキシ樹脂パネルを使用し、SiOxの無機材料の層(0.1から1μm)を片面または両面に直接堆積させて、図に示されるように、それらを完全に覆う方法。
Claims (6)
- 電子モジュールの外部電気接続のための電気接続ボール(4)を1つの面に備える多層PCB回路(2)に電気接続している1つまたは複数の電子部品(32)を含む前記電子モジュールであって、前記多層PCB回路は密封保護用電気絶縁性無機物内層(7)を備えることと、前記電子モジュールは6つの面を備え、前記多層PCB回路によって形成される前記面以外の5つの前記面を電気絶縁性または導電性無機物密封保護層(5)が完全に覆うことと、を特徴とする、電子モジュール。
- 前記1つまたは複数の電子部品(32)は、前記多層PCB回路(2)の前記電気接続ボールを含む前記面の反対側の1つの面に封入されることを特徴とする、請求項1に記載の電子モジュール。
- 前記封入される電子部品は、前記多層PCB回路上にスタックを形成し、したがって3D電子モジュールを得るために、複数のレベルにわたって分散されることを特徴とする、請求項2に記載の電子モジュール。
- 前記多層PCB回路は、前記多層PCB回路内に組み込まれている1つまたは複数の電子部品を含むことを特徴とする、請求項1〜3のいずれか一項に記載の電子モジュール。
- 前記多層PCB回路は、別の密封保護用電気絶縁性無機物内層(7)を含むことを特徴とする、請求項1〜4のいずれか一項に記載の電子モジュール。
- 前記電子部品(32)は、能動部品および/または受動部品および/またはMEMSであることを特徴とする、請求項1〜5のいずれか一項に記載の電子モジュール。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1663418 | 2016-12-27 | ||
FR1663418A FR3061404B1 (fr) | 2016-12-27 | 2016-12-27 | Procede de fabrication collective de modules electroniques hermetiques |
Publications (2)
Publication Number | Publication Date |
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JP2018107435A JP2018107435A (ja) | 2018-07-05 |
JP6840310B2 true JP6840310B2 (ja) | 2021-03-10 |
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Application Number | Title | Priority Date | Filing Date |
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JP2017233987A Active JP6840310B2 (ja) | 2016-12-27 | 2017-12-06 | 密封電子モジュールのウェーハスケール製造のための工程 |
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Country | Link |
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US (1) | US10483180B2 (ja) |
EP (1) | EP3343604A1 (ja) |
JP (1) | JP6840310B2 (ja) |
FR (1) | FR3061404B1 (ja) |
TW (1) | TWI732076B (ja) |
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GB201814347D0 (en) * | 2018-09-04 | 2018-10-17 | Pilkington Group Ltd | Electrical device, interlayer ply including an electrical device and methods for making said electrical device and interlayer ply |
CN114391306A (zh) * | 2020-08-21 | 2022-04-22 | 京东方科技集团股份有限公司 | 控制模组及其制造方法、电子设备 |
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US20180182683A1 (en) | 2018-06-28 |
US10483180B2 (en) | 2019-11-19 |
TWI732076B (zh) | 2021-07-01 |
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