JP6823669B2 - 2つの回路支持体の間に配置されたデバイスを有する電子モジュールおよびこのような電子モジュールの接合方法 - Google Patents
2つの回路支持体の間に配置されたデバイスを有する電子モジュールおよびこのような電子モジュールの接合方法 Download PDFInfo
- Publication number
- JP6823669B2 JP6823669B2 JP2018560067A JP2018560067A JP6823669B2 JP 6823669 B2 JP6823669 B2 JP 6823669B2 JP 2018560067 A JP2018560067 A JP 2018560067A JP 2018560067 A JP2018560067 A JP 2018560067A JP 6823669 B2 JP6823669 B2 JP 6823669B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit support
- mounting surface
- contact region
- module
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 13
- 238000005304 joining Methods 0.000 title claims description 10
- 239000000463 material Substances 0.000 claims description 23
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 14
- 230000002829 reductive effect Effects 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- -1 polysiloxane Polymers 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 238000005245 sintering Methods 0.000 claims description 2
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000036961 partial effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- 239000011265 semifinished product Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 210000002867 adherens junction Anatomy 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000012783 reinforcing fiber Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/051—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/164—Material
- H01L2924/1659—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
電子デバイスのための第1の実装面を有する第1の回路支持体と、
電子デバイスのための第2の実装面を有する第2の回路支持体であって、第2の実装面が第1の回路支持体の第1の実装面の方向に向けられて第1の実装面に結合されている、第2の回路支持体と、
第1の実装面にも第2の実装面にも結合されている少なくとも1つの電子デバイスと、を有する電子モジュールに関する。
さらに、本発明はこのような電子モジュールの接合方法に関する。
12 第1の実装面
13 第2の回路支持体
14 第2の実装面
15 空洞部
16 電子デバイス
17 はんだ結合部
18 接触パッド
19 接着結合部
20 凹部
21 接触領域
22 質量片
23 層
24 回路支持体の材料
25 カバー
26 スリット
27 ブリッジ部
28 溝
29 反対側
30 嵌め合い部材
31 切り抜き部
32 台座
33 焼結成形部
34 接合間隙
35 たわみ曲線
F 接合力
G 重力
Claims (20)
- 電子デバイスのための第1の実装面(12)を有する第1の回路支持体(11)と、
電子デバイスのための第2の実装面(14)を有する第2の回路支持体(13)であって、前記第2の実装面(14)を前記第1の回路支持体(11)の第1の実装面(12)の方向に向けられて前記第1の回路支持体に結合されている第2の回路支持体(13)と、
前記第1の実装面(12)にも前記第2の実装面(14)にも結合されている少なくとも1つの電子デバイス(16)と、
を有する電子モジュールであって、
前記第1の回路支持体(11)が、前記第1の回路支持体(11)と前記デバイス(16)との間に形成された接触領域(21)において、
前記接触領域(21)を取り囲んでいる前記第1の回路支持体(11)に比べても、前記第2の回路支持体(13)に比べても、
前記第1の実装面(12)に対して垂直の方向に撓みやすく形成されていることを特徴とするモジュール。 - 前記接触領域(21)が嵌め合い部材(30)上にあり、前記嵌め合い部材が、前記第1の回路支持体(11)における切り抜き部(31)への嵌め合わせにより取り付けられており、前記嵌め合い部材(30)が前記切り抜き部(31)内で前記第1の実装面(12)に対して垂直に移動可能であることを特徴とする請求項1記載のモジュール。
- 前記接触領域(21)が、前記接触領域(21)を取り囲んでいる前記第1の回路支持体(11)に比べても、前記第2の回路支持体(13)に比べても、前記第1の実装面(12)に対して垂直の方向に撓みやすく形成されていることを特徴とする請求項1または2記載のモジュール。
- 前記接触領域(21)が台座(32)を有し、前記台座の材料が前記第1の回路支持体(11)の残りの部分の材料よりも大きい弾性を有することを特徴とする請求項3記載のモジュール。
- 弾性の前記台座(32)がポリシロキサンからなることを特徴とする請求項4記載のモジュール。
- 前記接触領域(21)内において、前記第1の回路支持体(11)の材料が、前記接触領域を取り囲んでいる回路支持体に比べて厚さが薄くなっていることを特徴とする請求項3から5のいずれか1項に記載のモジュール。
- 厚さが薄くなった領域の材料が、前記第1の回路支持体(11)内で積層されており、前記接触領域(21)内で露出していることを特徴とする請求項6記載のモジュール。
- 厚さが薄くなった領域の材料がポリイミドであることを特徴とする請求項7記載のモジュール。
- 前記接触領域(21)の縁部が切り抜き部によって弱められていることを特徴とする請求項3から8のいずれか1項に記載のモジュール。
- 前記切り抜き部が前記第1の回路支持体(11)を突き抜けるスリット(26)からなり、前記スリット(26)の間に、前記接触領域(21)を前記第1の回路支持体(11)の残りの部分に結合するブリッジ部(27)が設けられていることを特徴とする請求項9記載のモジュール。
- 前記ブリッジ部(27)が前記第1の実装面(12)の平面内に分岐および少なくとも1つの方向変更を持った経路の少なくとも一方を有することを特徴とする請求項10記載のモジュール。
- 前記切り抜き部が溝(28)からなることを特徴とする請求項9記載のモジュール。
- 複数の平行に延びる溝(28)が設けられており、前記溝が、前記第1の実装面(12)と、前記第1の実装面(12)と反対の方向を向いている前記第1の回路支持体(11)の反対側(29)とに、交互に形成されていることを特徴とする請求項12記載のモジュール。
- 前記第1の回路支持体(11)が前記第1の実装面(12)、および、前記第2の回路支持体(13)が前記第2の実装面(14)の少なくとも一方に、前記デバイス(16)が配置される凹部(20)を有することを特徴とする請求項1から13のいずれか1項に記載のモジュール。
- 前記第1の回路支持体(11)と前記第2の回路支持体(13)とが、外部に対して封止された空洞部(15)を形成していることを特徴とする請求項14記載のモジュール。
- 前記デバイス(16)が、前記第1の実装面(12)および前記第2の実装面(14)の少なくとも一方と材料結合されていることを特徴とする請求項1から15のいずれか1項に記載のモジュール。
- 前記デバイス(16)が、前記第1の実装面(12)または前記第2の実装面(14)と摩擦結合されていることを特徴とする請求項1から12のいずれか1項に記載のモジュール。
- 前記デバイス(16)が、前記第1の回路支持体(11)または前記第2の回路支持体(13)に実装され、
その後、前記第1の回路支持体(11)が前記第2の回路支持体(13)と接合され、
前記デバイスと前記第1の回路支持体(11)および前記第2の回路支持体(13)の少なくとも一方との間の結合が形成されることを特徴とする請求項1から17のいずれか1項に記載の電子モジュールの接合方法。 - 前記第1の回路支持体(11)、前記第2の回路支持体(13)および前記デバイス(16)の間の結合の少なくとも一部が、焼結、はんだ付けおよび導電接着剤の少なくとも一つによって形成されることを特徴とする請求項18記載の方法。
- 前記第1の回路支持体(11)と前記第2の回路支持体(13)とを結合する際に、接合力Fが、撓みやすい前記接触領域(21)に加えられることを特徴とする請求項18または19記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP16170185.9 | 2016-05-18 | ||
EP16170185.9A EP3246941A1 (de) | 2016-05-18 | 2016-05-18 | Elektronische baugruppe mit einem zwischen zwei schaltungsträgern angeordneten bauelement und verfahren zum fügen einer solchen baugruppe |
PCT/EP2017/060361 WO2017198447A1 (de) | 2016-05-18 | 2017-05-02 | Elektronische baugruppe mit einem zwischen zwei schaltungsträgern angeordneten bauelement und verfahren zum fügen einer solchen baugruppe |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2019515512A JP2019515512A (ja) | 2019-06-06 |
JP2019515512A5 JP2019515512A5 (ja) | 2019-07-11 |
JP6823669B2 true JP6823669B2 (ja) | 2021-02-03 |
Family
ID=56068705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018560067A Active JP6823669B2 (ja) | 2016-05-18 | 2017-05-02 | 2つの回路支持体の間に配置されたデバイスを有する電子モジュールおよびこのような電子モジュールの接合方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10420220B2 (ja) |
EP (2) | EP3246941A1 (ja) |
JP (1) | JP6823669B2 (ja) |
CN (1) | CN109219875B (ja) |
WO (1) | WO2017198447A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3246941A1 (de) | 2016-05-18 | 2017-11-22 | Siemens Aktiengesellschaft | Elektronische baugruppe mit einem zwischen zwei schaltungsträgern angeordneten bauelement und verfahren zum fügen einer solchen baugruppe |
DE102017211330A1 (de) * | 2017-07-04 | 2019-01-10 | Siemens Aktiengesellschaft | Toleranzausgleichselement für Schaltbilder |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4563725A (en) * | 1983-01-06 | 1986-01-07 | Welwyn Electronics Limited | Electrical assembly |
US5904499A (en) * | 1994-12-22 | 1999-05-18 | Pace; Benedict G | Package for power semiconductor chips |
US7906376B2 (en) | 2008-06-30 | 2011-03-15 | Intel Corporation | Magnetic particle-based composite materials for semiconductor packages |
US8033014B2 (en) * | 2008-07-07 | 2011-10-11 | Unimicron Technology Corp. | Method of making a molded interconnect device |
JP5637156B2 (ja) * | 2012-02-22 | 2014-12-10 | トヨタ自動車株式会社 | 半導体モジュール |
US9355997B2 (en) * | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
DE102014206601A1 (de) | 2014-04-04 | 2015-10-08 | Siemens Aktiengesellschaft | Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube |
DE102014206608A1 (de) | 2014-04-04 | 2015-10-08 | Siemens Aktiengesellschaft | Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube |
DE102014115201A1 (de) * | 2014-10-20 | 2016-04-21 | Infineon Technologies Ag | Verfahren zum verlöten eines schaltungsträgers mit einer trägerplatte |
DE102014115815B4 (de) | 2014-10-30 | 2022-11-17 | Infineon Technologies Ag | Verfahren zur herstellung eines schaltungsträgers, verfahren zur herstellung einer halbleiteranordung, verfahren zum betrieb einer halbleiteranordnung und verfahren zur herstellung eines halbleitermoduls |
EP3246941A1 (de) | 2016-05-18 | 2017-11-22 | Siemens Aktiengesellschaft | Elektronische baugruppe mit einem zwischen zwei schaltungsträgern angeordneten bauelement und verfahren zum fügen einer solchen baugruppe |
-
2016
- 2016-05-18 EP EP16170185.9A patent/EP3246941A1/de not_active Withdrawn
-
2017
- 2017-05-02 EP EP17720498.9A patent/EP3443589B1/de active Active
- 2017-05-02 JP JP2018560067A patent/JP6823669B2/ja active Active
- 2017-05-02 WO PCT/EP2017/060361 patent/WO2017198447A1/de unknown
- 2017-05-02 CN CN201780030565.6A patent/CN109219875B/zh active Active
- 2017-05-02 US US16/301,064 patent/US10420220B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP3246941A1 (de) | 2017-11-22 |
CN109219875A (zh) | 2019-01-15 |
EP3443589B1 (de) | 2021-09-29 |
US10420220B2 (en) | 2019-09-17 |
EP3443589A1 (de) | 2019-02-20 |
JP2019515512A (ja) | 2019-06-06 |
CN109219875B (zh) | 2020-06-19 |
US20190191566A1 (en) | 2019-06-20 |
WO2017198447A1 (de) | 2017-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100849592B1 (ko) | 파워 모듈 구조 및 이것을 이용한 솔리드 스테이트 릴레이 | |
US7291914B2 (en) | Power semiconductor module | |
JP6068649B2 (ja) | 電子素子実装用基板および電子装置 | |
US8878072B2 (en) | High reliability fluid-tight low-profile electrically conductive interconnects for large scale frame attachment | |
US10306750B2 (en) | Circuit board and method for manufacturing a circuit board | |
JP2008147254A (ja) | 多層基板及び多層基板の製造方法 | |
KR20080083359A (ko) | 복합 기판 및 복합 기판의 제조 방법 | |
JP6823669B2 (ja) | 2つの回路支持体の間に配置されたデバイスを有する電子モジュールおよびこのような電子モジュールの接合方法 | |
JP5426730B2 (ja) | 光モジュール用パッケージ | |
JP6592102B2 (ja) | 電子素子実装用基板および電子装置 | |
JP6433604B2 (ja) | 非可逆回路素子、非可逆回路装置およびこれらの製造方法 | |
JP6702019B2 (ja) | 半導体装置 | |
JP2018512724A (ja) | 電子コンポーネントおよびその製造方法 | |
US9516750B2 (en) | Control unit for a motor vehicle | |
KR20180054618A (ko) | 특히 변속기 제어 모듈용 전자 어셈블리, 그리고 상기 전자 어셈블리의 제조 방법 | |
JP2017152521A (ja) | 撮像素子実装用基板および撮像装置 | |
JP6560076B2 (ja) | 撮像装置 | |
JP2020505791A (ja) | 電子構成素子を機械的に接続させる方法及び電子構成素子アセンブリ | |
CN110168721B (zh) | 半导体装置以及半导体装置的制造方法 | |
JP2016134552A (ja) | パワーモジュール構造 | |
JP5800076B2 (ja) | 電子装置および電子装置の取付構造 | |
JP2021115637A (ja) | Mems装置 | |
WO2023227266A1 (en) | Method of attaching a terminal to a metal substrate structure for a semiconductor power module and semiconductor power module | |
JP2013026280A (ja) | 素子内蔵配線基板、及びその製造方法 | |
JP2020088156A (ja) | プリント基板、電子装置及びそれらの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190530 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190530 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200728 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200731 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201215 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20210108 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6823669 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |